KR101132491B1 - Systems and methods for generalized slot-to-interlace mapping - Google Patents

Abstract

The transmitter or receiver apparatus includes a processing system configured to have one or more pilot interlace vectors and one or more distance vectors. The processing system is configured to generate a first slot interlace for the first slot based on the one or more pilot interlace vectors, and a second slot interlace for the second slot based on the first slot interlace and the one or more distance vectors. It is further configured to generate. Additional slot interlaces for all other slots may also be generated based on the first slot interlaces and one or more distance vectors.

Description

SYSTEMS AND METHODS FOR GENERALIZED SLOT-TO-INTERLACE MAPPING}

This patent application is provisional application number 60 / 951,951, entitled "Systems and Methods for Generalized Slot-to-Interlace Mapping", and is a provisional application filed on July 25, 2007; And Provisional Application No. 60 / 951,950, entitled “Multiplexing and Transmission of Multiple Data Streams in a Wireless Multi-Carrier Communication System,” claiming the priority of a provisional application filed on July 25, 2007, all of which are herein filed. Was assigned to the assignee of and is here referred to.

The present technology is generally related to telecommunications, and more particularly to systems and methods for generalized slot-to-interlace mapping.

Forward Link Only (FLO) is a digital wireless technology that has been developed by an industry-led group of wireless providers. FLO technology is designed in one case of a mobile multimedia environment and exhibits suitable performance characteristics for use in cellular headsets. This takes advantage of advances in coding and interleaving to achieve high-quality reception for both real-time content streaming and other data services. FLO technology can deliver robust mobile performance and high capacity without compromising power consumption. This technique also reduces the network cost of delivering multimedia content by dramatically reducing the number of transmitting devices that need to be used. FLO technology-based multimedia multicasting also complements the wireless operator's cellular network data and voice services and delivers content to the same cellular handsets used in 3G networks.

FLO wireless systems are designed to broadcast real-time audio and video signals to mobile users separately from non-real-time services. Each FLO transmission is performed using tall large power transmitter devices to ensure wide coverage in a given geographic area. It is also common to use 3-4 transmitter devices in most markets to ensure that the FLO signal reaches the majority of the population in a given market. During the process acquisition of the FLO data packet, several decisions and operations are performed to determine aspects such as frequency offset for each wireless receiver device. Given the nature of FLO broadcasts that support multimedia data acquisition, efficient processing of such data and associated overhead information is excellent. For example, in determining frequency offsets or other parameters, complex processing and determinations are required when the determination of phase and associated angles is used to facilitate FLO transmission and reception of data.

Wireless communication systems such as FLO are designed to operate in a mobile environment where channel characteristics, path gains and path delays in terms of the number of channels with large energy are expected to vary considerably over time periods. In an orthogonal frequency division multiplexing (OFDM) system, the timing synchronization block of the receiver device responds to changes in the channel profile by selecting an OFDM symbol boundary appropriately to maximize the energy captured in the fast Fourier transform (FFT) window. When such timing corrections occur, it is important for the channel estimation algorithm to consider the timing correction, etc., and compute the channel estimate used to demodulate a given OFDM symbol. In some implementations, channel tracking can also be used to determine timing adjustments to symbol boundaries that need to be applied to future symbols, thus timing corrections to be determined for already introduced timing corrections and future symbols. Cause subtle interactions between them. It is also common for the channel estimation block to process pilot observations from multiple OFDM symbols to cause channel estimation with better noise averaging and to solve longer channel delay spreads. If pilot observations from multiple OFDM symbols are processed together to produce a channel estimate, it is important that the underlying OFDM symbols are aligned with respect to symbol timing.

The following presents a simplified summary of the various configurations of the present technology to provide a basic understanding of certain aspects of the present configuration. This summary is not a comprehensive overview. It is not intended to identify key / critical elements or to cover the scope of the configurations described herein. Its sole purpose is to present the concept of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

According to one aspect of the present disclosure, a communication device includes a processor configured to include one or more file interlace vectors and one or more distance vectors. The processor is further configured to provide a first slot interlace based on the one or more pilot interlace vectors, and the processor is further configured to provide a second slot interlace based on the first slot interlace and the one or more distance vectors. It is composed.

In another aspect of the present invention, a communications apparatus includes means for including one or more pilot interlace vectors, means for including one or more distance vectors, and means for providing a first slot interlace based on the one or more pilot interlace vectors. And means for providing a second slot interlace based on the first slot interlace and the one or more distance vectors.

In a further aspect of the invention, a method for providing communication at a transmitter or receiver is disclosed. The method includes receiving one or more pilot interlace vectors, receiving one or more distance vectors, providing a first slot interlace based on the one or more pilot interlace vectors, and the first slot interlace and the one or more distances. Providing a second slot interlace based on the vectors.

In yet a further aspect of the present disclosure, the readable medium includes instructions executable by a transmitter or receiver device. The instructions include code for receiving one or more pilot interlace vectors, code for receiving one or more distance vectors, code for providing a first slot interlace based on the one or more pilot interlace vectors, and the first slot interlace and the Codes for providing a second slot interlace based on one or more distance vectors.

In yet a further aspect of the present invention, a communication apparatus includes a pilot interlace vector unit configured to include one or more pilot interlace vectors and a distance vector unit configured to include one or more distance vectors. The communications device is configured to provide a first slot interlace based on the one or more pilot interlace vectors and is further configured to provide a second slot interlace based on the first slot interlace and the one or more distance vectors. It further includes a calculation unit.

In another further aspect of the invention, additional slot interlaces for all other slots may be generated based on the first slot interlace and one or more distance vectors.

It will be appreciated that other configurations may be readily apparent to those skilled in the art from the following detailed description, wherein the detailed description shows and describes only some of the various configurations for purposes of illustration. As will be appreciated, the instructions herein may be different and extended to different configurations, some of which may be modified in other aspects, all of which do not depart from the scope of the present disclosure. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

1 is a conceptual block diagram illustrating an example of a wireless network system for forward link only networks.
2 is a conceptual block diagram illustrating an example of a receiver device that may be used in a wireless communication environment.
3 is a conceptual block diagram illustrating an example of a system that includes a transmitter device and one or more receiver devices.
4 illustrates an example FLO physical layer superframe.
5 illustrates an example interlace structure.
6 is an example table for slot-to-interlace mapping.
7 is a conceptual block diagram illustrating an example hardware implementation structure for generalized slot-to-interlace maps.
8 is a conceptual block diagram illustrating an example of the functionality of a processing system at a transmitter or receiver device.
9 is a flowchart illustrating an exemplary operation of providing communication or providing slot interlaces at a transmitter or receiver device.

The detailed description described in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present technology. However, one skilled in the art will understand that the techniques may be practiced without these specific details. In some cases, well-known structures and components are shown in the form of a block diagram to avoid obscuring the concepts of the present technology.

1 is a conceptual block diagram illustrating an example of a wireless network system 100 for Forward Link Only networks. System 100 includes one or more transmitter devices 110 that can communicate via wireless network 112 to one or more receiver devices 120.

Receiver device 120 includes a cellular telephone, a cordless telephone, a landline telephone, a laptop computer, a desktop computer, a personal digital assistant (PDA), a data transceiver, a modem, a pager, a camera, a game console, an MPEG audio layer-3 (MP3) player, Media gateway systems, audio communication devices, video communication devices, multimedia communication devices, any component of the aforementioned devices (eg, printed circuit board (s), integrated circuit (s) or circuit component (s)) or any It may be any suitable communication device such as another suitable audio, video or multimedia device or a combination thereof. The transmitter device 110 may be any suitable communication device capable of transmitting, such as a base station or broadcast station. In addition, any of the devices described above in this paragraph can be a receiver if it can receive a signal, and can be a transmitter device if it can transmit a signal. Thus, any of the receiver devices described above can be a transmitter device if it can transmit a signal, and any transmitter devices described above can be a receiver device if it can receive a signal. A device can also be referred to as a user device when used or used by a user.

Some of the receiver devices 120 may be used to decode the symbol subset 130 and other data such as multimedia data. The symbol subset 130 may be sent to an orthogonal frequency division multiplexing (OFDM) network using Forward Link Only (FLO) protocols for multimedia data delivery. Channel estimation may be based on uniformly spaced pilot tones inserted in the frequency domain in each OFDM symbol.

2 is a conceptual block diagram illustrating an example of a receiver apparatus 200 that may be used in a wireless communication environment in accordance with one or more aspects described herein. The receiver device 200 receives, for example, a signal from a receiving antenna (not shown) and performs general operations (e.g., filtering, amplifying, down-converting, etc.) on the received signal, and to obtain samples. And a receiver 202 that digitizes the conditioned signal. Demodulator 204 can demodulate and provide the received pilot symbols to processing system 206 for channel estimation. FLO channel component 210 may be provided to process FLO signals. This may include, for example, a digital stream that processes and / or positions positioning calculations among other processes. The processing system 206 may be one or more of a processor, transmitter apparatus 200 designated, for example, for analyzing information received by the receiver 202 and / or generating information for transmission by the transmitter 206. A processor that controls the components, or a processor that analyzes the information received by the receiver 202, generates information for transmission by the transmitter 216, and controls one or more components of the receiver device.

Processing system 206 may be implemented using software, hardware, or a combination thereof. Software should be understood broadly to mean instructions, data, or a combination thereof, whether or not they are referred to as software, firmware, middleware, microcode, hardware description language, or the like. For example, the processing system 206 may be implemented using one or more processors. Processors include general purpose processors, microcontrollers, digital signal processors (DSPs), application specific semiconductors (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components Or any other suitable entity capable of performing calculations or other manipulations of information.

Receiver device 200 may additionally include a memory 208 that is operatively coupled to processing system 206 and capable of storing information related to data processing.

The readable medium may include external processor storage such as storage and / or memory 208 integrated into the processor as in the case of an ASIC. For illustrative purposes, the readable medium may include one or more volatile memory, nonvolatile memory, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM). , Registers, hard disks, removable disks, CD-ROMs, DVDs, or any other suitable storage device. In addition, the readable medium may include a carrier wave that encodes a transmission line or a data signal. A readable medium may be a computer-readable medium on which a computer program or instructions are encoded and stored. The computer program or instructions may be executable by the processing system of the transmitter or receiver device by the transmitter or receiver device.

The receiver device 200 may further include a background monitor 214 for processing FLO data, a symbol modulator 214, and a transmitter 216 for transmitting the modulated signal.

3 is a conceptual block diagram illustrating an example of a system 300 that includes a transmitter device 302 and one or more receiver devices 304. Transmitter device 302 receives one or more receivers via one or more transmit antennas 308 and one or more receivers 310 that receive signal (s) from one or more receiver devices 304 via one or more receive antennas 306. It may include a transmitter 322 for transmitting to the devices (304). Receiver 310 may be operatively associated with a demodulator 312 that demodulates the received information. The modulated symbols can be analyzed by a processing system 314 similar to the processing system 206 described above, and the processing system 315 can be coupled to a memory 316 that stores information related to data processing.

Processing system 314 may be further coupled to FLO channel component 318 that facilitates processing of FLO information associated with one or more respective receiver devices 304. The FLO channel component 318 attaches information to a signal associated with the updated data stream for a given transport stream for communication with receiver devices 304 to provide an indication that a new optimal channel has been identified and acknowledged. Can be. Modulator 320 may be provided to multiplex the signal for transmission by transmitter 322. The descriptions provided above for the processing system and readable medium in connection with FIG. 2 apply similarly to the components of FIG. 3.

4 illustrates an example FLO physical layer superframe 400. Superframe 400 may include, among others, time division multiplexing (TDM) pilots (eg, TDM pilot 1, TDM pilot 2), wide-area identification channel (WIC), local-area identification channel (LIC), Overhead information symbols (OIS), four frames of data (eg, frames 1 through 4), a positioning pilot channel (PPC), and a signaling parameter channel (SPC). TDM pilots may allow for fast acquisition of OIS. The OIS may describe the location of data for each media service in the superframe. The superframe structure is not limited to that shown in FIG. 4, and the superframe may be composed of fewer or more elements than shown in FIG. 4.

OFDM is a form of multi-carrier modulation. The usable bandwidth may be divided into N bins and may be referred to as subcarriers, where each subcarrier is modulated by, for example, a quadrature amplitude modulated (QAM) symbol. In FLO, transmission and reception may be based on using 4096 (4K) subcarriers, and the QAM modulation symbols may be selected from, for example, QPSK or 16-QAM alphabet.

Each superframe may include a number of OFDM symbols. For illustrative purposes, a superframe may include 200 OFDM symbols per MHz of available bandwidth (eg, 1200 OFDM symbols for 6 MHz). In each symbol, there may be multiple subcarriers (eg 4000 subcarriers). These subcarriers can be grouped separately into interlaces.

As shown in FIG. 5, an example interlace structure may include eight interlaces, for example. In this example, the interlace indexes range from 0 to 7 (ie, I0, I1, I2, I3, I4, I5, I6, I7, and I8). Each interlace may consist of 500 subcarriers equally spaced through, for example, a signal bandwidth. Between adjacent subcarriers in each interlace, there are seven subcarriers, each of which belongs to a different interlace. In each OFDM symbol, one interlace can be assigned to a pilot interlace and can be used for channel estimation. Thus, 500 subcarriers can be modulated with known (pilot) modulation symbols. The remaining seven interlaces, or 3500 subcarriers, can be used for data symbols and modulation. Although FIG. 5 illustrates an exemplary interlace structure / function, the interlace structure / function is not limited to this configuration, which may be another type of configuration (eg, having any number of interlaces).

Each interlace can be evenly distributed in frequency to achieve total frequency diversity within the available bandwidth. These interlaces may be assigned to logical channels that vary in terms of duration and the number of interlaces actually used. This provides flexibility in the time diversity achieved by any given data source. Lower data rate channels can be assigned fewer interlaces to improve time diversity, while higher data rate channels can be assigned more interlaces to minimize wireless on-time and reduce power consumption. Can be used.

6 is an example table for slot-to-interlace mapping. The vertical axis represents the slot indices. The horizontal axis represents symbol indices. The values in the table represent the interface indices. According to one aspect of the present disclosure, a slot refers to a group of symbols, an interlace refers to a group of subcarriers, and each slot is assigned to interlaces in each symbol period based on a slot-to-interlace mapping scheme. Can be mapped. A slot, which may be referred to as a transmission slot, may correspond to a group of interlace or modulation symbols in one symbol period. In another aspect of the present disclosure, a slot may be mapped to one or more interlaces, and the interlace may be mapped to one or more slots. The time unit for the frame may include a MAC time unit in the MAC (or allocation) layer and an OFDM symbol period in the physical (PHY) layer. The symbol period may be referred to as a MAC time unit in terms of physical layer channel (PLC) allocation, and an OFDM symbol period in terms of subcarrier allocation. The symbol period may be referred to as a time unit of symbol index.

The number of subcarriers (eg, FFT size) may be 4K, and as described above, the present technology is not limited to the FFT size or the size of the subcarriers. The present technology can multiplex and transmit multiple data streams in OFDM systems of various FFT sizes. In an OFDM system having a 4K FFT size, a group of 500 modulation symbols forming a slot may be mapped to one interlace.

According to one aspect of the present disclosure, the slot may be fixed through different FFT sizes. In addition, the size of the interlace can be one-eighth the number of active subcarriers, and the slot can be mapped to a fractional or multiple (including 1) interlaces based on the FFT size. The interlace (s) assigned to the slot may reside in multiple OFDM symbol periods. For example, for a 2K FFT size, a slot (ie 500 modulation symbols) maps into four interlaces over two consecutive 1K OFDM symbols. Similarly, for a 1K FFT size, a slot is mapped into four interlaces over four consecutive 1K OFDM symbols. Also, for example, the number of subcarriers available for 1K, 2K, 4K, and 8K FFT sizes can be 1000, 2000, 4000, and 8000, respectively, which means that the available subcarriers are, for example, It may not include guard subcarriers. That is, an FFT size of 1K includes 1024 subcarriers, 24 of which may be used as guard subcarriers, for example. The number of guard subcarriers can increase proportionally to the FFT size, for example.

For 8K FFT size, slots may be mapped to half of the interlace over half of the 8K OFDM symbol. Note that regardless of the FFT size, the MAC time unit may include eight slots, for example. Table 1 below shows an exemplary relationship between FFT sizes of 1K, 2K, 4K and 8K and their respective number of OFDM symbols per MAC time unit, the number of subcarriers per interface, and the number of interlaces per slot.

FFT size Number of OFDM Symbols Per MAC Time Unit Number of subcarriers per interlace Number of interlaces per slot 1024 (1K) 4 125 4 2048 (2K) 2 250 2 4096 (4K) One 500 One 8192 (8K) ½ 1000 ½

An exemplary relationship between OFDM symbol indices and MAC time indices is shown in Table 2 below.

FFT size OFDM symbol indices for MAC time index m
(m = 4, 5, ...) 1024 (1K) 4m-12, 4m-11, 4m-10, 4m-9 2048 (2K) 2m-4, 2m-3 4096 (4K) m 8192 (8K) (m + 3) / 2

According to one aspect of the present disclosure, depending on the relationship between MAC time units and OFDM symbols and the relationship between slots and interlaces, the present technology is based on MAC time units, regardless of the FFT size of the OFDM system. Hierarchical multiplexing is possible. The physical layer may map MAC time units into OFDM symbols and interlaces, respectively, for various FFT sizes.

Although the foregoing examples refer only to 1K, 2K, 4K and 8K FFT sizes, the present technology is not limited to a specific FFT size and other FFT sizes can be implemented without departing from the scope of the present technology.

The system may include a number of slots per symbol (eg, eight slots per symbol as shown in FIG. 6). One slot (eg slot 0) may be assigned to pilot symbols, and other slots (eg slots 1 to 7) may be capable of assigning data symbols. Pilot symbols are known apriori by transmitter and receiver devices. Pilot symbols may be used by the transmitter or receiver device, for example, for frame synchronization, frequency acquisition, timing acquisition, and / or channel estimation. In this example, slot 0 is referred to as a pilot slot and slots 1 to 7 can be referred to as data slots. Optionally, multiple slots (eg, slots 1 and 3) can be pilot symbols and the remaining slots can be assigned data symbols. In this optional example, slots 1 and 3 are referred to as pilot slots and the remaining slots are referred to as data slots. 6 illustrates an exemplary slot structure / function, but the slot structure / function is not limited to this configuration. The slot structure / function may be of different kinds of configurations (e.g., the slot structure may have any number of slots and the slots may be allocated for various kinds of information and in many different ways). .

In FIG. 6, each of the slots is assigned or mapped to an interlace. For example, slot 1 is assigned to interlaces 3, 1, 0, 7, 5, 4, etc. over successive OFDM symbol indices 4, 5, 6, 6, 7, 8, 0, etc. do. According to one aspect of the present disclosure, a slot interlace may refer to an interlace to which a slot is mapped or to be mapped. Pilot interlaces may be referred to as slot interlaces associated with pilot slots. In another aspect of the present disclosure, slot interlace may refer to the slot to which the interlace is to be mapped or mapped. The pilot interlace may refer to the slot interlace associated with the pilot interlace. In another aspect of the present disclosure, slot interlace may be referred to as slot-to-interlace map function or interlace-to-slot map function. The slot-to-interlace map function and the interlace-to-slot map function can be the same or even, but the slot-to-interlace map function takes a slot (or slot index) as input and uses an interlace (or interlace index). The exception is that the interlace-to-slot map function uses an interlace (or interlace index) as input and provides a slot (or slot index) as output. Slots, interlaces, pilot slots, pilot interlaces, symbols, and the like are sometimes used to refer to slot indexes, interlace indexes, pilot slot indexes, pilot interlace indexes, and symbol indexes, respectively.

The FLO system can multicast various services such as live video and audio streams (eg, news, music or sports channels). A service can be viewed as a collection of one or more related data components, such as video, audio, text, or signaling associated with a service. Each FLO service may be delivered over one or more logical channels, referred to as multicast logical channels (MLCs). For example, video and audio components of a given service may be transmitted on multiple MLCs (eg, two different MLCs). One or more slots for data symbols may be used for MLCs. For example, slots 1-3 may be used for video components of a given service, and slots 4-7 may be used for audio components of a given service.

Example systems and methods for a generalized slot-to-interlace map for FLO are described in detail below. Such systems and methods may support the entire family of slot-to-interlace maps of FLO transmitter and receiver devices. Generalized slot-to-interlace maps can provide different length channel estimation and better Doppler resilience calculated at the receiver device. Generalized slot-to-interlace members are sometimes referred to as flexible slot-to-interlace maps. The particular slot-to-interlace map can sometimes be referenced by the corresponding pilot staggering pattern used in the slot-to-interlace map.

The FLO air interface specification (TIA-1099) for 4K mode according to its associated implementation may support a staggering pattern referred to as the (2,6) pattern. In this case, the pilot interface alternates between interlaces 2 and 6 over successive OFDM symbols of the superframe. The (2,6) staggering pattern provides pilot observation from two separate interlaces 2 and 6. This allows the calculation of channel estimation to have a maximum length of 1024 in 4K mode operation. While 1024 length channel estimates may be sufficient for use in regions such as the United States, longer channel estimates (longer than two pilot interlaces) may be found in other modes of FLO deployment (eg, HF band deployment or 2K mode). May be required.

Slot-to-interlace map patterns such as (0,3,6) and (0,2,4,6) pilot staggering patterns can be used to allow for flexibility of channel estimation. Such patterns may provide up to 4096 and 2048 length channel estimates, respectively, according to one example implementation. It is possible to estimate a longer channel delay spread (eg, greater than 4096 or greater than 2048) where there is a higher channel estimation error.

According to one aspect of the present disclosure, flexible slot-to-interlace maps may be used for OIS and data symbols. TDM pilot, WIC, LIC, PPC and SPC symbols (such as TDM Pilot 1 and TDM Pilot 2) may have interlaces fixed independently to the slot-to-interlace map used for the rest of the superframe. Under normal operating conditions, the FLO receiver device can determine the slot-to-interlace map to be used after decoding the SPC symbols, which occurs at the end of the superframe.

Example implementations of generalized slot-to-interlace maps using (0,3,6), (0,2,4,6) and (2,6) pilot staggering patterns are described in detail below. Slot-to-interlace maps and associated implementations are based on the concept of distance vectors and pilot interlaces for different data slots. The length of the distance vector may be a subtraction of the number of interlaces and the number of pilot interlaces. In this example, eight interlaces and eight slots can be used. However, the present technology is not limited to this number, and any number of interlaces and any number of slots may be used.

(0,3,6) Staggering  pattern

The pilot interlace vector I ₀ may be determined by the staggering pattern. One or more distance vectors D may be defined for each slot-to-interlace map. The distance vectors can be used to determine the interlace index for each data slot. After determining the pilot interlace, the data slots can be arranged using the remaining interlaces such that the relative distance of the resulting interlace for a given slot can be obtained from the rotation of one or more distance vectors. An example implementation of this is described below.

For illustration, for the (0,3,6) staggering pattern, I ₀ = [0,3,6,1,4,7,2,5], and D = [7,2,4,6 , 1,5,3]. For the (0,3,6) staggering pattern, the pilot jump is 3 and I ₀ is determined as follows: (i) Starting at 0 from the staggering pattern, (ii) obtaining 3 as Add pilot jump 3 to the initial value 0, (iii) add 3 to obtain 6, (iv) add 3 to obtain 9, which translates as 1, (v) add 3 to obtain 12 Add, which translates to 4, (vi) adds 3 to obtain 15, which translates to 7, (vii) adds 3 to obtain 18, which translates to 2, and (vii) to obtain 21 Add 3, which translates to 5. The above-described translation can be performed using, for example, the total number of interlaces and the modulo operation.

Let n denote the OFDM symbol index in the superframe, and n is 0 to 1999. Note that symbol index 0 corresponds to TDM1. Let s represent the slot index and let s be from 0 to 7. Assume that slot interlace I [s, n] corresponds to an interlace in which slot s is mapped at OFDM symbol index n. Note that s in I [s, n] has a value from 0 to 7. Slot 0 (ie, s = 0) corresponds to the pilot slot for the interlaces given by the selected staggering pattern. Thus, slot interlace I [0, n] may be referred to as pilot interlace.

1. Given an OFDM symbol index n, the pilot interlace I [0, n] can be determined by indexing to I ₀ using n. For example, I [0, n] = I ₀ [(n mod 8)].

이라고 한다. 그리고 나서, OFDM 심벌 인덱스 n에서 데이터 슬롯들에 대한 슬롯-대-인터레이스 맵은 I[s,n] = (I[0,n] +

[s])mod 8(여기서, s=1,2,...,7)에 의해 주어질 수 있다.2. For data slots, first calculate the rotation factor R _n for the distance vector D based on the OFDM symbol index n. For example, R _n = 2n mod 7. Then, perform a right cyclic shift of the vector D by R _n . Vector after right cyclic shift

It is called. Then, the slot-to-interlace map for the data slots at OFDM symbol index n is given by I [s, n] = (I [0, n] +

[s]) mod 8 (where s = 1,2, ..., 7).

The resulting map confirms that in a block of seven successive OFDM symbols, every slot occurs at all possible distances from the pilot interlace. Also, in a block of 56 consecutive OFDM symbols, each slot occupies all available interlaces exactly seven times. Each slot passes through all available interlaces at least once in a window of 17 OFDM symbols. It is guaranteed that at least three intermediate OFDM symbols exist before a particular interlace is assigned to the same slot.

(2.6) Staggering  pattern

An exemplary generalized slot-to-interlace map based on the (2,6) staggering pattern can be realized using pilot interlace and distance vectors. In this example, one pilot interlace vector I ₀ and two different distance vectors D ₀ and D ₁ are used to realize the entire slot-to-interlace pattern.

For illustration, for the (2,6) staggering pattern, I ₀ = [2,6,2,6,2,6,2,6], and D ₀ = [6,2,4,7, Let 3,1,5] and D ₁ = [2,6,4,3,7,5,1]. Using the foregoing indication, the slot interlace I [s, n], which is the interlace corresponding to the slot s at OFDM symbol index n, can be determined as follows.

1. Given the OFDM symbol index n, the pilot interlace I [0, n] can be determined by indexing to I ₀ using n. For example, I [0, n] = I ₀ [(n mod 8)].

2. If n is even, set D to be D ₀ . If n is odd, set D to be D ₁ .

이라고 한다. 그리고 나서, OFDM 심벌 인덱스 n에서 데이터 슬롯들에 대한 슬롯-대-인터레이스 맵은 I[s,n] = (I[0,n] +

[s])mod 8(여기서, s=1,2,...,7)에 의해 주어질 수 있다.3. For data slots, first calculate the rotation factor R _n for the distance vector D based on the OFDM symbol index n. For example, R _n = 2n mod 7. Then, perform a right cyclic shift of the vector D by R _n . Vector after right cyclic shift

It is called. Then, the slot-to-interlace map for the data slots at OFDM symbol index n is given by I [s, n] = (I [0, n] +

[s]) mod 8 (where s = 1,2, ..., 7).

Note that with two different vectors, there is an additional step of selecting a suitable distance vector based on the OFDM symbol index n. To generalize the structure, eight separate distance vectors can be used for any pilot interlace vector. Also, two pilot staggering patterns can be generated using the same structure, where the pilot interlace and distance vectors can be appropriately selected in software.

(0,2,4,6) Staggering  pattern

An exemplary generalized slot-to-interlace map based on the (0,2,4,6) staggering pattern can be realized using pilot interlace and distance vectors. In this example, one pilot interlace vector I ₀ and a distance vector D are used to realize the entire slot-to-interlace pattern.

For illustration, for a (0,2,4,6) staggering pattern, I ₀ = [0,2,4,6,0,2,4,6] and D = [1,6,4 , 2,7,5,3]. Using the foregoing indication, the slot interlace I [s, n] can be determined as follows:

1. Given the OFDM symbol index n, the pilot interlace I [0, n] can be determined by indexing to I ₀ using n. For example, I [0, n] = I ₀ [(n mod 8)].

이라고 한다. 그리고 나서, OFDM 심벌 인덱스 n에서 데이터 슬롯들에 대한 슬롯-대-인터레이스 맵은 I[s,n] = (I[0,n] +

[s])mod 8(여기서, s=1,2,...,7)에 의해 주어질 수 있다.2. For data slots, first calculate the rotation factor R _n for the distance vector D based on the OFDM symbol index n. For example, R _n = 2n mod 7. Then, perform a right cyclic shift of the vector D by R _n . Vector after right cyclic shift

It is called. Then, the slot-to-interlace map for the data slots at OFDM symbol index n is given by I [s, n] = (I [0, n] +

[s]) mod 8 (where s = 1,2, ..., 7).

For this example implementation, each slot (except the pilot slot) is allocated to all interlaces at least once in every ten successive OFDM symbols. The interlace is repeated for the slot only after three OFDM symbols. Given a distance vector with seven lengths, every slot occupies all possible distances from the pilot interlace in a block of seven successive OFDM symbols. Further, in a block of 28 consecutive OFDM symbols, each slot occupies interlaces 0, 2, 4 and 6 three times, and occupies four times of interlaces 1, 3, 5 and 7.

Referring again to FIG. 6, this concept is described in detail. For the (0,2,4,6) staggering pattern described above, each of slots 1 through 7 has at least once interlaces 0, 1, 2, 3, 4, 5, 6 in every 10 consecutive OFDM symbols. And 7 respectively. For example, slot 1 is assigned to interlace 3 for OFDM symbol index 3, assigned to interlace 1 for OFDM symbol index 5, assigned to interlace 0 for OFDM symbol index 6, and interlaced for OFDM symbol index 7. Assigned to interlace 5 for OFDM symbol index 8, assigned to interlace 4 for OFDM symbol index 9, assigned to interlace 2 for OFDM symbol index 10, and assigned to interlace 1 for OFDM symbol index 11 Assigned to interlace 7 for OFDM symbol index 12 and assigned to interlace 6 for OFDM symbol index 13.

Still referring to FIG. 6, the interlace index is repeated only after three symbols. For example, for slot 0, interlace 0 is repeated only after three successive OFDM symbol indices. This is the same for interlace 2, interlace 4 and interlace 6. 6 also shows that every slot occupies all possible distances from the pilot interlace in seven consecutive OFDM symbols. For example, slot 0 is for pilot interlace, and for interlaces 0, 2, 4, 6, 0, 2, and 4 for OFDM symbol indices 4, 5, 6, 7, 8, 9, and 10, respectively. Is assigned to. Slot 3 is assigned to interlaces 6, 5, 3, 2, 1, 7, and 6 for OFDM symbol indices 4, 5, 6, 7, 8, 9, and 10, respectively. Thus, the distance between slot 3 and slot 0 is the absolute value of the difference between the interlace indices of slot 3 and slot 0. In this example, the distance is 6, 3, 7 (which translates to -1), 4 (which translates to -4), 1, for OFDM symbol indices 4, 5, 6, 7, 8, 9, and 10, respectively. 5 and 2. The absolute value can be obtained, for example, by performing a modulo operation.

According to one aspect of the present disclosure, one or more pilot interlace vectors (eg, I ₀ , I ₁ , I ₂ , etc.) may be used, and one or more distance vectors (eg, D ₀ , D ₁₎ , D ₂ , etc.) may be used. The number of slots and the number of interlaces are not limited to eight, each of which may be any number. Thus, there may be p slots and q interlaces. Variables p and q can be the same. The length of each pilot interlace vector may be q. An example implementation is described as follows:

1. Given an OFDM symbol index n, the pilot interlace vector I can be selected from one or more pilot interlace vectors based, for example, on n. The pilot interlace can be determined by indexing with I selected using n. For example, I [0, n] = I [(n mod m1)], where m1 is any integer. It is possible that there is more than one pilot interlace. For example, pilot interlaces may be expressed as follows: I [x, n] = I [(n mod m1)], where x may represent indices of pilot slots. The indices for pilot slots need not be contiguous. For example, pilot slots may occupy slot 1, slot 3, and slot 7, where x = 1, 3, 7.

2. Given an OFDM symbol index n, the distance vector D is one based on n (eg, based on n mod m2, where m2 is any integer) and / or based on the pilot interlace selected in step 1 above. It may be selected from the above distance vectors.

이라고 한다. 그리고 나서, OFDM 심벌 인덱스 n에서 데이터 슬롯들에 대한 슬롯-대-인터레이스 맵은 I[s,n]=(I[0,n] +

[s])mod m4에 의해 주어지며, 여기서, s = 1,2,...,p-1,p, m4는 임의의 정수이다. I[x,n]과 같은 다수의 파일럿 인터레이스들이 존재하는 경우, 슬롯-대-인터레이스 맵은 다음과 같이 표현된다: I[s,n] = (I[x,n] +

[s])mod m4, 여기서 s는 비-파일럿 슬롯들(예를 들어, 데이터 슬롯들)의 인덱스들을 나타낼 수 있다. 변수 k, m1, m2, m3 및 m4는 동일하거나 상이할 수 있다. 하나 이상의 로테이션 인자가 존재하는 것도 가능하다.3. For data slots, first calculate the rotation factor R _n for the distance vector D based on the OFDM symbol index n. For example, R _n = k * n mod 3, where k and m3 are each an integer. Then, a right cyclic shift of the vector D is performed by R _n . Vector after right cyclic shift

It is called. Then, the slot-to-interlace map for the data slots at OFDM symbol index n is given by I [s, n] = (I [0, n] +

[s]) mod m4, where s = 1,2, ..., p-1, p, m4 is any integer. If there are multiple pilot interlaces such as I [x, n], then the slot-to-interlace map is expressed as follows: I [s, n] = (I [x, n] +

[s]) mod m4, where s may represent indices of non-pilot slots (eg, data slots). The variables k, m1, m2, m3 and m4 can be the same or different. It is also possible for more than one rotation factor to exist.

According to one aspect of the present disclosure, one or more (or all) features of the following features may be associated with generalized slot-to-interlace mapping:

1. Interlace is associated with non-contiguous subcarriers (eg, I0 is associated with non-contiguous subcarrier indices, such as 48, 56, etc., as shown in FIG. 5).

2. Each of the slots occupies as many different interlaces as possible through a subsequent set of symbols. For example, in FIG. 6, slot 2 occupies interlaces 1, 7, 6, 4 and 3 over symbol indices 4, 5, 6, 7, and 8. Thus, each slot may occupy all available interlaces through successive symbols, and the slot-to-interlace assignment may change over time.

3. Each slot occupies all possible distances from the pilot interlace through the set of symbols that follow. The number of symbols continuing in the set may be a subtraction of the number of interlaces and the number of pilot interlaces. For example, in FIG. 6, the distance between slot 6 (data slot) and slot 0 (pilot slot) is 7, 4, 1, over symbol indices 4, 5, 6, 7, 8, 9, and 10. 5, 2, 6, and 3. Thus, slot 6 occupies all possible distances 1 to 7 from the pilot interlace over six consecutive symbols.

4. Each slot is assigned to the same interlace only after a predetermined number of successive symbols. In other words, the interlace index is repeated for a given slot only after a predetermined number of successive symbols. For example, in FIG. 6, slot 0 is assigned back to interlace 0 only after three successive symbols.

Hardware implementation structure

7 is a conceptual block diagram illustrating an example hardware implementation structure for generalized slot-to-interlace maps. The processing system 710 of the transmitter and receiver apparatus may include a pilot interlace vector unit 710, a distance vector unit 730, and a slot interlace calculation unit 740. In this example implementation, eight slots and eight interlaces are used, but the present technology is not limited to this number of slots and interlaces.

The various parameters required for computing the slot-to-interlace map, such as pilot interlace vector, distance vectors and other control parameters such as shift_enable, can be programmed by software to allow easy programmability in the mapping used. . The software may directly program hardware registers (eg, pilot interlace vector unit 710 and distance vector unit 730) that include some of these parameters. These parameters can be programmed at power up (based on basic parameters) or after processing the SPC symbols. In addition, the hardware may be awake when software attempts to program these registers. Since a hardware sleep timeline is available in software, the software can easily control sleep-related problems. Providing control directly in software can ensure that OIS decoding is enabled at the appropriate time in software. OIS decoding can be enabled after the slot-to-interlace parameters have been programmed in hardware.

Pilot interlace vector unit 710 may comprise a pilot interlace vector I ₀ , including, for example, an 8 × 1 vector programmed by software. Each element of the vector may be three bits long (to represent one of eight interlaces from 000 to 111). For staggering patterns such as (2,6), the pattern can be repeated periodically until all eight elements of the vector are used. For example, the (2,6) staggering pattern is (2,6,2,6,2,6,2,6) The pilot interlace vector I ₀ may be generated. The (0,3,6) staggering pattern may generate a pilot interlace vector I ₀ of (0,3,6,1,4,7,2,5). The (0,2,4,6) staggering pattern may generate a pilot interlace vector I ₀ of (0,2,4,6,0,2,4,6).

The software may also program the distance vector unit 730, which includes, for example, an 8 × 7 distance vector table. Each entry in this table can be represented using three bits. As a result, the table may contain eight rows, each of which is 21 bits long. Each column of this table corresponds to one distance vector. In the case of a pilot interlace vector, if the number of distance vectors is less than eight, the distance vectors are repeated periodically to fill the entire table. Thus, for the pattern (0, 3, 6), one vector is repeated eight times to fill the table. In the case of a (2,6) staggering pattern, there are two separate distance vectors, each of which appears four times at a relative position in the table. Software can control periodic iterations while writing to a table.

The shift_enable flag 775 (1 bit) may be used by hardware to enable or disable the cyclic rotation of the distance vector based on the OFDM symbol index. The shift_enable flag 775 may be initiated by software while initiating pilot interlace vector and distance vectors.

Once all software programming is complete, hardware operations can be performed as follows. Note that in the following description, the OFDM symbol index n corresponds to the OFDM symbol index of the superframe. The hardware first uses the OFDM symbol index n from which the slot-to-interlace map will be generated, selects the three least significant bits (LSBs), and indexes with the pilot interlace vector to obtain the pilot interlace. The three LSBs are used for this purpose. To save register space, the pilot interlace vector can be stored in packet form using 8x3 = 24 bits in a 32 bit register. The format may be for the pilot interlace for OFDM symbol index 0 to occupy the least significant three bits. The pilot interlace may be given by three bits in a vector occupying (n mod 8) * 3, (n mod 8) * 3 + 1 and (n mod 8) * 3 +2 positions. Let's denote this by I [0, n].

OFDM symbol index n may also be used to index the distance vector and the rotation factor used on the distance vector. The shift_enable flag 775 set by software (depending on the slot-to-interlace map used) may determine whether non-zero rotation is to be used for the distance vector. If the shift_enable flag 775 is set, the OFDM symbol index n is first shifted left by 1 using the left shift unit 795 (multiply by 2), and modulo 7 operations use modulo 7 units 790. Is performed on the result. The multiplier 770 multiplies the result by 3 to reach Rn (to take into account the 3 bits used by each entry in the distance vector table), which is an argument for the right cyclic shift unit 742. Used as

에 도달하기 위해 R_n에 의해 주어진 인수에 의해 오른쪽으로 순환적으로 쉬프팅된다. 이러한 특정한 예시에서, 벡터 D가 32 비트 레지스터에서 단 24비트만을 점유하기 때문에, 사이클릭 쉬프트 동작은 그것을 고려할 필요가 있다. 선택적으로, 하드웨어 동작을 단순화하기 위해, 소프트웨어는 전면에 8개의 LSB들을 위치시킴으로써 32비트들로의 24비트 벡터의 사이클릭 연장을 수행할 수 있다. 이러한 연장된 벡터는 하드웨어에 대한 사이클릭 쉬프트 동작을 도울 수 있다. 이러한 경우에,

은 순환적으로 쉬프팅된 벡터의 24 LSB들에 대응한다.OFDM symbol index n may also be used to select an appropriate distance vector column in the distance vector matrix. For example, three LSBs of an OFDM symbol index (eg, n mod 8) can be used as the column index to select a distance vector to derive D. Distance vector D and then

It is cyclically shifted to the right by the argument given by R _n to reach. In this particular example, since vector D occupies only 24 bits in a 32 bit register, the cyclic shift operation needs to take it into account. Optionally, to simplify hardware operation, software may perform cyclic extension of a 24-bit vector to 32 bits by placing eight LSBs in front. This extended vector can help with cyclic shift operations for the hardware. In this case,

Corresponds to 24 LSBs of the cyclically shifted vector.

의 세 개의 LDB들로 가산될 수 있다. 그리고 나서, 모듈로 8 연산이 모듈로 8 유닛(750)을 이용하여 그 결과상에 수행될 수 있다. 그 결과는 데이터 인터레이스 테이블 유닛(760)으로 위치될 수 있으며, 이는 1 x 7 벡터를 포함할 수 있다. 벡터의 각각의 엘리먼트는 3비트 길이일 수 있다. 최초 결과는 슬롯 1에 대응하는 슬롯 인터레이스일 수 있다. 슬롯 s에 대해 일반적으로, 인터레이스 인덱스는 연산 (I[0,n] +

(3s-3:3s-1))mod8에 의해 주어진다.

에서, (x:y)는 위의 표현에서, 비트 위치들 x, x-1,...,y에 대응한다.Slot interlaces 725 for data slots 1 through 7 of OFDM symbol index n may be obtained as follows. The previously obtained pilot interlace I [0, n] is added using adder 745.

Can be added to three LDBs. Modulo 8 operations may then be performed on the results using the modulo 8 unit 750. The result can be placed into the data interlace table unit 760, which can include a 1 x 7 vector. Each element of the vector may be three bits long. The initial result may be a slot interlace corresponding to slot 1. For slot s in general, the interlace index is computed (I [0, n] +

(3s-3: 3s-1)) is given by mod8.

(X: y) corresponds to the bit positions x, x-1, ..., y in the above representation.

Interlace indexes obtained for all seven data slots and pilot slots may be stored in a lookup table (not shown) that may be indexed using the slot index.

The processing system 710 shown in FIG. 7 may also be used to map an interlace to a slot when OFDM symbols are received. Pilot interlace 720 can provide pilot slot (s) for a given interlace (s), and slot interlaces 725 can provide slot (s) for a given interlace (s). Processing system 710 may be programmed using one or more pilot interlace vectors, one or more distance vectors, and optionally one or more rotation factors. Optionally, the processing system 710 may receive some or all of them via other suitable means (eg, FLO network, other type of network, other type of communication). For a given symbol index and interlace (s), the processing system 710 may use the slot interlace calculation unit to provide the corresponding pilot slot (s). Alternatively, for a given symbol index and pilot interlace (s), the processing system 710 may use the slot interlace calculation unit to provide the corresponding pilot slot (s). The implementation of the slot interlace calculation unit may be similar to or different from the implementation of the slot interlace calculation unit 740.

Modulo 7 implementation in hardware

An example modulo 7 operation that can be used in the slot-to-interlace map implementation is described in detail below. For example, a 2n mod 7 operation may be performed, where n is the OFDM symbol index of the superframe. According to one exemplary configuration, the modulo 7 operation may be performed using only the adder. The basic concept is explained below.

It is known that 8≡1. Thus, any square of 8 congruent to 1 modulo 7. In other words, for any integer m, it is 8 ^m ≡ 1 (mod 7). Based on this concept of congruence and the expansion of any square of 8, a 3m bit positive integer k uses a suitable integer k = 8 ^m-1 p _{m -1} +8 ^m-2 p _{m -2} + .. +8 ¹ p ₁ + p ₀ . This equation uses modulo 7 to k = p _{m -1} + p _{m -2} + .. + p ₁ + p ₀ Can be recorded as. Each P _i represents three consecutive bits at position (3i + 2: 3i) in the binary representation of k. Thus, three consecutive bits in the form (3i + 2: 3i) can be added until the final result is reduced to three bits.

According to an exemplary aspect of the present invention, this technique can be applied to OFDM symbol index n in a superframe as follows. Note that the OFDM symbol index n is 11 bits in the FLO system over all bandwidths, and 2n is 12 bits.

1. First group the bits into (0-2), (3-5), (6-8) and (9-11), then add them to be 5 bits.

2. Next, group the resulting 5-bit number back into bits (0-2) and (3-4), and add them to be 4-bit numbers.

3. In this step, the result number is guaranteed to be between 0 and 8 (decimal). Look-up tables can be used at this stage, or one last addition can be performed. If addition is performed, step 4 below is performed as follows.

4. Add bit 4 to the three LSBs. The result is guaranteed to be between 0 and 7.

5. If the number is 7, map it back to 0 (since 7 is 0 modulo 7). If the result is less than 7, the result is used as is.

This implementation uses six adders. It is also possible to use a higher square of 8 (eg 64) and reduce the operations to two additions. Lookup tables can be used to map the final result back to modulo 7.

According to another exemplary aspect of the present invention, the modulo 7 operation may be performed in the following manner.

1. For example, given OFDM symbol index n using a two's complement binary representation and given that 2n is a k ₁ -bit length number, select the size of the group (m bits), where m is 2 Greater than or equal to, m is less than k ₁ , m is an integer, and k ₁ is an integer.

2. Based on the size of the group (m bits), determine (n ₁ ) groups for the number of k ₁ -bit lengths, where each of the groups is m-bits long, n ₁ is an integer, and the group Are represented by groups 1 to n ₁ , where n ₁ may be roundup (k ₁ / m).

3. k- group a number of bits in length to the group 1 through group n and _1, k ₁ - starting from the least significant bit (s) of the bit length of the group 1 k ₁ - associated with the least significant bit (s) of the number of bits in length Be sure to

4. k ₂ -, and further the group 1 through group n ₁ to produce a number of bits long, where k ₂ is smaller than k _1, k ₂ is an integer.

5. Determine the number of n _i i-th groups for the number of k _i -bit lengths, each i-th group is m-bits long, i is an integer, i is greater than 1, and i-th groups are i second group 1 to the i-th group denoted as n _i. n _i may be round up (k _i / m).

6. Group k _i bit length numbers into i th group 1 to i th group n _i , where i th group 1 is associated with the least significant bit (s) of the k _i bit length number.

7. k _{i +1} - further to the i-th group of 1 to n _i i-th group to produce a number of bits long, where, k _{i + l} it is less than k _i, k _{i +1} is an integer.

8. Increment i

9. Repeat steps 5 to 8 until k _{i + l} is less than or equal to m.

10. If k _{i + l} is less than or equal to m and m is 3, step 9 may provide the final required result. If m is greater than 3 (eg 6), a lookup table can be used in this step. Optionally, steps similar to steps 5 to 8 can be repeated until m is three.

11. If the result number is 7, map it back to 0 (since 7 is 0 modulo 7). If the result is less than 7, the result is used as is.

Returning to FIG. 2, in an example process, the receiver 202 of the receiver device 200 may receive a signal. The demodulator may demodulate the received signal and provide OFDM symbols to the processing system 206, which separates the OFDM symbols into interlaces, and converts the interlaces into one or more pilot interlaces and one or more slot interlaces. To map into slots. Processing system 206 may also further generate modulation symbols from the slots and convert the modulation symbols into data streams.

Referring to FIG. 3, in an example process, the transmitter device 302 may receive data streams and convert the data streams into symbols. The processing system 314 of the transmitter device 302 may assign symbols to slots and map the slots to interlaces using one or more pilot interlaces and one or more slot interlaces. The modulator 320 may perform modulation to generate a modulated signal, and the transmitter 322 may transmit a modulated signal.

8 is a conceptual block diagram illustrating an example of the functionality of a processing system at a transmitter or receiver device. The processing system 314 or 206 (see FIGS. 2 and 3) of the transmitter or receiver device 302 or 200 (see FIGS. 2 and 3) includes a module 810 for containing one or more pilot interlace vectors and a module 820 for containing one or more distance vectors. ). Processing system 206 or 314 may also provide a module 830 for providing a first slot interlace based on one or more pilot interlace vectors and a second slot interlace based on the first slot interlace and one or more distance vectors. Module 840.

9 is a flowchart illustrating an exemplary operation of providing communication or providing slot interlaces at a transmitter or receiver device. In step 910 the processing system 314 or 206 (see FIGS. 2 and 3) of the transmitter or receiver device 302 or 200 may receive one or more pilot interlace vectors. At step 920, processing system 314 or 206 may receive one or more distance vectors. In step 930, it may provide a first slot interlace based on one or more pilot interlace vectors. Further, at step 940, processing system 314 or 206 provides a second slot interlace based on the first slot interlace and one or more distance vectors. The readable medium may be encoded or stored with instructions executable by a transmitter or receiver apparatus or a processing system of such apparatus, the instructions comprising codes for the steps 910, 920, 930 and 940 described above.

As mentioned above, the hardware structure can be used to implement a family of slot-to-interlace maps through any hardware registers. The structure may support slot-to-interlace maps using different pilot staggering patterns. Channel estimation capability and Doppler elasticity depend on pilot staggering patterns in OFDM systems such as FLO. In addition to the structure described above, a single FLO receiver device can support different slot-to-interlace maps that can be used in different networks. The architecture also supports backward compatibility of the FLO radio interlace specification.

According to one aspect of the present disclosure, it may be desirable for pilot observations obtained from multiple OFDM symbols to correspond with as many individual subcarriers as possible to correct the channel estimate that satisfies the delay spread requirements of the communication system. In addition to pilot symbols that occupy a wide array of subcarriers, data symbols are interspered across pilot subcarriers and the total set of subcarriers available in an OFDM system, so that data symbols benefit from channel estimation and frequency diversity. It may be desirable to have. Thus, slot-to-interlace maps play an important role in OFDM systems.

The hardware and software implementations described above are example implementations. The present technology is not limited to these implementations, and other suitable implementations may be used. The present technology is also not limited to FLO systems, which can be used in various communication systems. The staggering patterns (2,6), (0,3,6) and (0,2,4,6) have been described above, but these are merely examples, and the present technology is not limited to these examples. Descriptions relating to OFDM symbols and OFDM symbol index may be applicable to other symbols and symbol index. The term "symbol" as used herein may refer to an OFDM symbol, any other kind of symbol, data, or information. As used herein, the term “vector” may refer to an array, group, set, or plurality of items. As used herein, the term "map" may refer to assign or assign, and vice versa.

Those skilled in the art will appreciate that the various components, blocks, modules, elements, networks, apparatuses, processing systems, methods, systems and algorithms described above can be implemented in hardware, software or a combination thereof. . For example, a component may be, but is not limited to being, a processor, an object, an executable, a thread of execution, a program, and / or a process running on a computer. For illustrative purposes, both the communication device and the application running on the device can be components. One or more components can reside within a process and / or thread of execution and a component can be localized on one computer and / or distributed on two or more computers. In addition, these components can execute from various readable media having various data structures stored thereon. Components are local and local, such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a wireless or wired network such as a local system, a distributed system and / or the Internet). And / or communicate via a remote process.

It is to be understood that the specific order or hierarchy of steps in the processes described herein is a description of the exemplary manner. Based upon design preferences, it will be understood that the specific order or hierarchy of processes may be rearranged. The accompanying method claims represent elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy shown.

Various descriptions have been provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Accordingly, the claims are not intended to limit the aspects shown herein, but are to be accorded the full scope consistent with the language claims, and reference to singular elements refer to "one and one" unless specifically stated otherwise. It is not intended to mean, but rather to mean "one or more". The term "optional" refers to one or more unless specifically stated otherwise. Titles and subtitles underlined and / or italicized are for convenience only and do not limit this specification, and they are not referred to for understanding of this specification.

The structural and functional equivalents of the elements of the various aspects known to those skilled in the art or described later throughout this specification are expressly incorporated herein by reference and are intended to cover the claims. Moreover, nothing not disclosed herein is disclosed to the public regardless of whether such description is explicitly referenced in the claims. Unless an element is referenced using the phrase "means for," or in the case of a method claim, the element is referred to using the phrase "step for," the claim element is 35 USC §112, paragraph 6 It will not be interpreted under. Also, in the context of the terms "include" and "have", as used in the claims or the description, these terms are intended to be included in a manner similar to the term "comprising". This is because "comprising" is used as a mutable word in the claims.

Claims (55)

As a communication device,
A processor configured to include one or more pilot interlace vectors and one or more distance vectors,
The processor is further configured to provide a first slot interlace based on the one or more pilot interlace vectors,
And the processor is further configured to provide a second slot interlace based on the first slot interlace and the one or more distance vectors. The apparatus of claim 1, wherein the processor is further configured to provide the first slot interlace based on the one or more pilot interlace vectors and symbol index. The method of claim 1,
The one or more distance vectors include a plurality of distance vectors,
And the processor is further configured to select one distance vector from the plurality of distance vectors based on a symbol index. 4. The communications apparatus of claim 3, wherein the processor is further configured to provide the second slot interlace based on the first slot interlace and the selected distance vector. The method of claim 3, wherein
The one or more pilot interlace vectors comprises a plurality of pilot interlace vectors,
The processor is further configured to select one pilot interlace vector from the plurality of pilot interlace vectors based on a symbol index,
And the processor is further configured to select the one distance vector from the plurality of distance vectors based on the symbol index and the selected pilot interlace. The method of claim 1,
The first slot interlace comprises one or more pilot interlaces,
And the second slot interlace comprises one or more slot interlaces for data. The apparatus of claim 1, wherein the processor is further configured to rotate the one or more distance vectors to provide the second slot interlace. The apparatus of claim 1, wherein the processor is further configured to provide the one or more pilot interlace vectors based on one or more staggering patterns. 10. The apparatus of claim 1, wherein the processor is further configured to select one pilot interlace vector from the one or more pilot interlace vectors based on a symbol index. The method of claim 1,
The first slot interlace is for a first slot,
The second slot interlace is for a second slot,
And the processor is further configured to provide additional slot interlaces for all other slots based on the first slot interlace and the one or more distance vectors. 2. The communications apparatus of claim 1, wherein the processor is further configured to determine a length of a channel estimate of a transmit or receive channel. The method of claim 1,
The second slot interlace is configured to map a slot to one or more interlaces or to map an interlace to one or more slots,
Wherein the symbol corresponds to one or more media access control (MAC) time units or the MAC time unit corresponds to one or more symbols. As a communication device,
Means for including one or more pilot interlace vectors;
Means for including one or more distance vectors;
Means for providing a first slot interlace based on the one or more pilot interlace vectors; And
Means for providing a second slot interlace based on the first slot interlace and the one or more distance vectors. The apparatus of claim 13, wherein the means for providing the first slot interlace is configured to provide the first slot interlace based on the one or more pilot interlace vectors and a symbol index. Following the claim 13,
The one or more distance vectors include a plurality of distance vectors,
And the communication device further comprises means for selecting one distance vector from the plurality of distance vectors based on a symbol index. 16. The apparatus of claim 15, wherein the means for providing the second slot interlace is configured to provide the second slot interlace based on the first slot interlace and the selected distance vector. The method of claim 15,
The one or more pilot interlace vectors comprises a plurality of pilot interlace vectors,
The communication device,
Means for selecting one pilot interlace vector from the plurality of pilot interlace vectors based on a symbol index; And
And means for selecting the one distance vector from the plurality of distance vectors based on the symbol index and the selected pilot interlace. The method of claim 13,
The first slot interlace comprises one or more pilot interlaces,
And the second slot interlace comprises one or more slot interlaces for data. 14. The communications apparatus of claim 13, further comprising means for rotating the one or more distance vectors to provide the second slot interlace. The apparatus of claim 13, further comprising means for providing the one or more pilot interlace vectors based on one or more staggering patterns. 14. The communications apparatus of claim 13, further comprising means for selecting one pilot interlace vector from the one or more pilot interlace vectors based on a symbol index. The method of claim 13,
The first slot interlace is for a first slot,
The second slot interlace is for a second slot,
And the communication apparatus further comprises means for providing additional slot interlaces for all other slots based on the first slot interlace and the one or more distance vectors. 14. The communications apparatus of claim 13, further comprising means for determining the length of a channel estimate of a transmit or receive channel. The method of claim 13,
The second slot interlace is configured to map a slot to one or more interlaces or to map an interlace to one or more slots,
And the symbol corresponds to one or more MAC time units or the MAC time unit corresponds to one or more symbols. A method of providing communication at a transmitter or receiver,
Receiving one or more pilot interlace vectors;
Receiving one or more distance vectors;
Providing a first slot interlace based on the one or more pilot interlace vectors; And
Providing a second slot interlace based on the first slot interlace and the one or more distance vectors. 26. The method of claim 25, wherein providing the first slot interlace comprises providing the first slot interlace based on the one or more pilot interlace vectors and symbol index. How to. The method of claim 25,
The one or more distance vectors include a plurality of distance vectors,
Wherein the method further comprises selecting one distance vector from the plurality of distance vectors based on a symbol index. 28. The method of claim 27, wherein providing the second slot interlace comprises providing the second slot interlace based on the first slot interlace and the selected distance vector. How to. The method of claim 27,
The one or more pilot interlace vectors comprises a plurality of pilot interlace vectors,
The method comprises:
Selecting one pilot interlace vector from the plurality of pilot interlace vectors based on a symbol index; And
Selecting the one distance vector from the plurality of distance vectors based on the symbol index and the selected pilot interlace. The method of claim 25,
The first slot interlace comprises one or more pilot interlaces,
And wherein the second slot interlace comprises one or more slot interlaces for data. 27. The method of claim 25, further comprising rotating the one or more distance vectors to provide the second slot interlace. 27. The method of claim 25, further comprising providing the one or more pilot interlace vectors based on one or more staggering patterns. 27. The method of claim 25, further comprising selecting one pilot interlace vector from the one or more pilot interlace vectors based on a symbol index. The method of claim 25,
The first slot interlace is for a first slot,
The second slot interlace is for a second slot,
The method further comprises providing additional slot interlaces for all other slots based on the first slot interlace and the one or more distance vectors. 27. The method of claim 25, further comprising determining a length of a channel estimate of a transmit or receive channel. The method of claim 25,
The second slot interlace maps a slot to one or more interlaces or maps an interlace to one or more slots,
Wherein a symbol corresponds to one or more media access control (MAC) time units, or wherein the MAC time unit corresponds to one or more symbols. 27. The method of claim 25, wherein providing the second slot interlace comprises:
k ₁ - step indicating twice the symbol index (two times) as the number of bit length? Where k ₁ is an integer?;
Wherein k ₁ - determining n ₁ of the first group to the bit length? Wherein each of the first groups is m-bits long, m is greater than or equal to 2, m is less than k ₁ , m is an integer, n ₁ is an integer, and the first groups are the first group 1 through Represented as the first group n ₁ ?;
Grouping the k ₁ -bit length numbers into a first group 1 to a first group n ₁ ; And
adding the first group 1 to the first group n ₁ to produce a k ₂ -bit length number? Where k ₂ is less than k ₁ and k ₂ is an integer? And providing communication at the transmitter or receiver. 38. The method of claim 37, wherein providing the second slot interlace comprises:
Determining n _i i-th groups for the number of k _i -bit lengths? Wherein each of the i th groups is m-bits long, i is an integer, i is greater than 1, and the i th groups are represented as i th groups 1 to i th group n _i ;
Grouping the k _i -bit length numbers into an i th group 1 th i th group n _i ;
adding the i th group 1 to i th group n _i to generate a k _{i + 1} -bit length number? Here, k _{i + 1} is less than k _i, is an integer k _{i + 1?;}
incrementing i; And
Determining the n _i i-th groups, grouping the k _i -bit length numbers, adding the i-th group 1 to i-th group n _i , and incrementing _i with k _{i +} Repeating until ₁ is less than or equal to m. The method of claim 25,
Converting data streams into symbols;
Allocating the symbols to slots;
Mapping the slots to interlaces using the first slot interlace and the second slot interlace. Wherein the first slot interlace includes one or more pilot interlaces and the second slot interlace includes one or more slot interlaces for data;
Performing modulation;
Generating a modulated signal; And
Transmitting the modulated signal further comprising providing a communication at the transmitter or receiver. The method of claim 25,
Obtaining symbols;
Separating the symbols into interlaces;
Mapping the interlaces to slots using the first slot interlace and the second slot interlace. Wherein the first slot interlace includes one or more pilot interlaces and the second slot interlace includes one or more slot interlaces for data;
Generating modulation symbols from the slots; And
Converting the modulation symbols into data streams. A readable medium containing instructions executable by a transmitter or receiver device, the instructions comprising:
Code for receiving one or more pilot interlace vectors;
Code for receiving one or more distance vectors;
Code for providing a first slot interlace based on the one or more pilot interlace vectors; And
And code for providing a second slot interlace based on the first slot interlace and the one or more distance vectors. 42. The readable medium of claim 41, wherein the code for providing the first slot interlace comprises code for providing the first slot interlace based on the one or more pilot interlace vectors and symbol index. 42. The method of claim 41 wherein
The one or more distance vectors include a plurality of distance vectors,
And the instructions further comprise code for selecting one distance vector from the plurality of distance vectors based on a symbol index. 44. The readable medium of claim 43, wherein the code for providing the second slot interlace comprises code for providing the second slot interlace based on the first slot interlace and the selected distance vector. The method of claim 43,
The one or more pilot interlace vectors comprises a plurality of pilot interlace vectors,
The commands are
Code for selecting one pilot interlace vector from the plurality of pilot interlace vectors based on a symbol index; And
And code for selecting the one distance vector from the plurality of distance vectors based on the symbol index and the selected pilot interlace. 42. The method of claim 41 wherein
The first slot interlace comprises one or more pilot interlaces,
And the second slot interlace comprises one or more slot interlaces for data. 42. The readable medium of claim 41 wherein the instructions further comprise code for rotating the one or more distance vectors to provide the second slot interlace. 42. The readable medium of claim 41 wherein the instructions further comprise code for providing the one or more pilot interlace vectors based on one or more staggering patterns. 42. The readable medium of claim 41 wherein the instructions further comprise code for selecting one pilot interlace vector from the one or more pilot interlace vectors based on a symbol index. 42. The method of claim 41 wherein
The first slot interlace is for a first slot,
The second slot interlace is for a second slot,
And the instructions further comprise code for providing additional slot interlaces for all other slots based on the first slot interlace and the one or more distance vectors. 42. The readable medium of claim 41 wherein the instructions further comprise code for determining a length of a channel estimate of a transmit or receive channel. 42. The method of claim 41 wherein the second slot interlace maps a slot to one or more interlaces or an interlace to one or more slots,
Readable medium in which a symbol corresponds to one or more MAC time units, or a MAC time unit corresponds to one or more symbols. The method of claim 41, wherein the instructions are:
k A code to represent twice the symbol index as a ₁ -bit length? Where k ₁ is an integer?;
Wherein k ₁ - code for determining the n ₁ of the first group to the bit length? Wherein each of the first groups is m-bits long, m is greater than or equal to 2, m is less than k ₁ , m is an integer, n ₁ is an integer, and the first groups are the first group 1 through Represented as the first group n ₁ ?;
Code for grouping the k ₁ -bit length numbers into a first group 1 to a first group n ₁ ; And
code for adding the first group 1 to the first group n ₁ to generate a k ₂ -bit length number? Where k ₂ is less than k ₁ and k ₂ is an integer? Further comprising a readable medium. 54. The method of claim 53 wherein the instructions are:
k _i -code for determining the n _i i-th groups for the number of bits in length? Wherein each of the i th groups is m-bits long, i is an integer, i is greater than 1, and the i th groups are represented as i th groups 1 to i th group n _i ;
Code for grouping the k _i -bit length numbers into an i th group 1 th i th group n _i ;
k _{i + 1} -code for adding the i th group 1 to i th group n _i to generate a number of bits length? Here, k _{i + 1} is less than k _i, is an integer k _{i + 1?;}
code for incrementing i; And
determining n _i i-th groups, grouping k _i -bit length numbers, adding i-th group 1 to i-th group n _i , and incrementing _i with k _{i + 1} greater than m And further comprising code for repeating the same or less than. As a communication device,
A pilot interlace vector unit configured to include one or more pilot interlace vectors;
A distance vector unit configured to include one or more distance vectors; And
A slot interlace calculation unit configured to provide a first slot interlace based on the one or more pilot interlace vectors and further configured to provide a second slot interlace based on the first slot interlace and the one or more distance vectors. Communication device.

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