KR101128691B1 - Non volatile memory device and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a non-volatile memory device and a method of manufacturing the same, which can prevent the operating characteristics of the device is changed by preventing the CD change of the gate when forming the gate of the non-volatile memory device, the present invention for this purpose A floating gate formed to be electrically separated from the substrate, a first dielectric layer formed of a nitride based material in a portion of the floating gate, and an oxide based series formed on the floating gate to cover the first dielectric layer. A nonvolatile memory device including a second dielectric layer, a select gate formed on the second dielectric layer, and a source / drain formed in the substrate exposed to both sides of the floating gate is provided.

Nonvolatile Memory, EPROM, Dielectric, Nitride, Oxide.

Description

Nonvolatile memory device and manufacturing method thereof {NON VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing a nonvolatile memory device according to the prior art.

2A to 2C are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the related art shown in FIG. 1.

3 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention.

4A through 4D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10, 20: substrate

11, 21: tunnel oxide film

12, 14, 25: polysilicon film

13, 23, 24: dielectric film

15, 26: photosensitive film pattern

16, 27: etching process

12a, 22: floating gate

14a, 25a: Select gate

17, 28: source / drain

13a, 13c, 23a, 23c: oxide film

13b, 23b: nitride film

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a gate electrode of an EPROM (Erasable Programmable Readd Only Memory) device and a method of forming the same.

In general, semiconductor memory is classified into volatile memory, in which stored information is lost when electricity supply is interrupted, and non-volatile memory, which can maintain information even when electricity supply is interrupted. do.

Representative examples of the nonvolatile memory described above include erasable programmable read only memory (EPROM), electrically EPROM (EEPROM), and flash memory.

1 is a cross-sectional view illustrating an EPROM device among nonvolatile memory devices according to the prior art.

Referring to FIG. 1, a gate electrode of an EPROM device according to the related art has a structure in which different gates are stacked up and down with a dielectric layer 13 interposed therebetween. Specifically, it has a structure in which a floating gate 12a / dielectric film 13 / select gate 14a (or a control gate) is stacked.

Usually, the dielectric film 13 has a stacked structure of an oxide film 13a / nitride film 13b / oxide film 13c, that is, an ONO structure.

The floating gate 12a is separated from the substrate 10 through the tunnel oxide film 11, and the source / drain 17 is formed in the substrate 10 exposed to both sides of the floating gate 12a.

Hereinafter, a method of manufacturing a nonvolatile memory device such as an EPROM device according to the related art shown in FIG. 1 will be described with reference to FIGS. 2A to 2C.

First, as shown in FIG. 2A, the tunnel oxide film 11 is formed on the substrate 10, and the polysilicon film 12 (hereinafter, referred to as first polysilicon) is formed as the electrode material for the floating gate on the tunnel oxide film 11. A polysilicon film 14 (hereinafter referred to as a second polysilicon film) is sequentially deposited using the dielectric material 13 and the electrode material for the select gate. In general, the dielectric film 13 is formed by sequentially depositing the oxide film 13a, the nitride film 13b, and the oxide film 13c.

Subsequently, as illustrated in FIG. 2B, a photo process is performed to form the photoresist pattern 15 on the second polysilicon film 14. Here, the photoresist pattern 15 is for defining a select gate and a floating gate.

Subsequently, an etching process 16 using the photoresist pattern 15 as an etching mask is carried out to form the second polysilicon film 14 (see FIG. 2A), the dielectric film 13, and the first polysilicon film 12 (FIG. 2a) and the tunnel oxide film 11 are sequentially etched. As a result, the floating gate 12a and the select gate 14a electrically separated through the dielectric film 13 are formed on the substrate 10 in a stacked structure.

Subsequently, as shown in FIG. 2C, a strip process is performed to remove the photoresist pattern 15 (see FIG. 2B).

Subsequently, a mask process and a source / drain ion implantation process are performed to form the source / drain 17 in the substrate 10 exposed to both sides of the floating gate 12a.

However, in the etching process 16 for forming the floating gate 12a and the select gate 14a, as shown in FIG. 2B, the first and the first photosensitive film patterns 15 for forming the select gate 14a may be used. Since the second polysilicon films 12 and 14 and the dielectric film 13 are etched, the floating gate 12a and the dielectric film are changed according to the difference in etching selectivity between the polysilicon films 12 and 14 and the dielectric film 13 made of ONO. A CD (Critical Dimension) change occurs between 13 and the select gate 14a.

In particular, the etching selectivity is not significantly different between the polysilicon films 12 and 14 and the oxide films 13a and 13c, but the etching selectivity is significantly different between the polysilicon films 12 and 14 and the nitride film 13b. Accordingly, the CD of the dielectric film 13 and the floating gate 12a changes from the CD of the select gate 14a from the moment when the nitride film 13b is exposed by the etching process 16.

The CD change between the floating gate 12a and the dielectric layer 13 and the select gate 14a is a factor of changing the threshold voltage and breakdown voltage characteristics that determine the operation of the gate. Therefore, a problem arises in that the operating characteristics change to match the operating characteristics required by the EPROM device.

Accordingly, the present invention has been made to solve the above problems of the prior art, a non-volatile memory device that can prevent the change in the operating characteristics of the device by preventing the CD change of the gate when forming the gate of the non-volatile memory device and Its purpose is to provide its manufacturing method.

According to an aspect of the present invention, there is provided a floating gate formed on an upper surface of a substrate, the substrate being electrically separated from the substrate, and a first dielectric layer formed of a nitride-based material in a portion of the floating gate; A ratio including an oxide-based second dielectric layer formed on the floating gate to cover the first dielectric layer, a select gate formed on the second dielectric layer, and a source / drain formed in the substrate exposed to both sides of the floating gate; Provided is a volatile memory device.

In one aspect of the present invention, the first dielectric layer has an ONO structure.

In one aspect of the invention, the floating gate is electrically separated from the substrate by a tunnel oxide film.

In one aspect of the invention, the floating gate and the select gate is made of a polysilicon film.

According to another aspect of the present invention, there is provided a method of forming a floating gate electrically separated from a substrate on a substrate, and including a first nitride-based material in a portion of the floating gate. Forming a dielectric layer, sequentially depositing an oxide-based second dielectric layer and a select gate electrode material along a step of an upper portion of the entire structure including the first dielectric layer, and forming the second dielectric layer and the select gate electrode Etching a material to form a select gate on the second dielectric layer while forming a second dielectric layer covering the floating gate and the first dielectric layer, and forming a source / drain in the substrate exposed to both sides of the floating gate; It provides a method of manufacturing a nonvolatile memory device comprising the step of.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention. As an example, an EPROM device is shown.

Referring to FIG. 3, a nonvolatile memory device according to an exemplary embodiment of the present invention may include a tunnel oxide film 21 formed on a semiconductor substrate 20, a floating gate 22 formed on a tunnel oxide film 21, and a floating gate. A dielectric layer 23 (hereinafter, referred to as a first dielectric layer) formed of a nitride-based material in a portion of the region 22 and an oxide layer formed on the floating gate 22 to cover the first dielectric layer 23. A dielectric film 24 (hereinafter referred to as a second dielectric film) and a select gate 25a (or control gate) formed on the second dielectric film 24.

At this time, the first dielectric film 23 has a stacked structure of an oxide film 23a / nitride film 23b / oxide film 23c, that is, an ONO structure. That is, since the first dielectric layer 23 has a structure in which the nitride layer 23b is interposed between two oxide layers 23a and 23c, the nitride layer 23b is exposed during the etching process for forming the select gate 25a. The CD change of the existing gate occurs as it is.

Therefore, in the exemplary embodiment of the present invention, an oxide-based second dielectric layer 24 covering the first dielectric layer 23 is further formed to prevent the nitride layer 23b from being exposed during the etching process for forming the select gate 25a.

In addition, the floating gate 22 of the nonvolatile memory device according to the embodiment of the present invention is electrically separated from the substrate 20 through the tunnel oxide layer 21 and exposed to both sides of the floating gate 22. ), Source / drain 28 is formed.

Hereinafter, a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention shown in FIG. 3 will be described with reference to FIGS. 4A to 4D.

First, as shown in FIG. 4A, a tunnel oxide film 21 is formed on a substrate 20 by performing an oxidation process, and a polysilicon film (not shown) is used as an electrode material for a floating gate on the tunnel oxide film 21. Hereinafter, a first polysilicon film) is deposited. In this case, the first polysilicon film is formed as a doped silicon film to have conductivity. For example, in the case of the doped silicon film, a vapor pressure gas vapor deposition (LPCVD) method is deposited using a gas obtained by mixing SiH ₄ with PH ₃ , PCl ₅ , BCl _3, or B ₂ H ₆ .

Subsequently, a mask process and an etching process are performed to etch the first polysilicon film and the tunnel oxide film 21. As a result, the floating gate 22 is formed on the tunnel oxide film 21.

Subsequently, a dielectric film 23 (hereinafter referred to as a first dielectric film) is deposited along the stepped portion of the substrate 20 including the floating gate 22. For example, the first dielectric film 23 is formed by sequentially depositing the oxide film 23a, the nitride film 23b, and the oxide film 23c.

Subsequently, a mask process and an etching process are performed to etch the first dielectric layer 23 to expose a portion of both sides of the floating gate 22.

Subsequently, as illustrated in FIG. 4B, an oxide-based dielectric layer 24 (hereinafter referred to as a second dielectric layer) is deposited along the step of the entire structure including the first dielectric layer 23. Then, a polysilicon film 25 (hereinafter referred to as a second polysilicon film) is deposited using the electrode material for the select gate. In general, the dielectric film 13 is formed by sequentially depositing the oxide film 13a, the nitride film 13b, and the oxide film 13c.

In addition, the second polysilicon film 25 is formed of a doped or undoped silicon film. For example, in the case of an undoped silicon film, SiH ₄ may be deposited by LPCVD, and a dopant may be implanted in a subsequent source / drain ion implantation process. On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Subsequently, as illustrated in FIG. 4C, a photolithography process is performed to form the photosensitive film pattern 26 on the second polysilicon film 25 (see FIG. 4B). Here, the photoresist pattern 26 is used to define the select gate 25a and is formed of the same CD as the photoresist pattern 26 used for forming the floating gate 22.

Subsequently, an etching process 27 using the photoresist pattern 26 as an etching mask is performed to sequentially etch the second polysilicon layer 25 and the second dielectric layer 24. Accordingly, the second dielectric layer 24 covering the first dielectric layer 23 is formed on the floating gate 22 to overlap both sides of the floating gate 22, and the select gate 25a is formed on the second dielectric layer 24. Is formed.

In the etching process 27, the nitride film 23b constituting the first dielectric film 23 is not immediately exposed by the oxide-based second dielectric film 24. Therefore, no CD change occurs between the select gate 25a and the floating gate 22. Through this, the threshold voltage and the breakdown voltage characteristics are maintained as it is, thereby preventing a change in operating characteristics of the device.

In addition, it is possible to prevent the occurrence of a fence in the first dielectric layer 23 and to prevent the occurrence of a short between the select gate 25a and the floating gate 22.

Subsequently, as shown in FIG. 4D, a strip process is performed to remove the photoresist pattern 26 (see FIG. 4C).

Subsequently, a mask process and a source / drain ion implantation process are performed to form the source / drain 28 in the substrate 20 exposed to both sides of the floating gate 22.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after forming the floating gate, an oxide-based second dielectric layer is separately formed on the floating gate to cover the first dielectric layer formed of the nitride layer, thereby forming an etching for forming the select gate. CD change of the gate generated as the nitride film is exposed during the process can be prevented.

Through this, the threshold voltage and the breakdown voltage characteristics are maintained as it is, thereby preventing a change in operating characteristics of the device. As a result, it is possible to secure low voltage characteristics of the EPROM device that is recently required.

In addition, it is possible to prevent the occurrence of a fence in the first dielectric layer and to prevent the occurrence of a short between the select gate and the floating gate.

In addition, since the photoresist pattern used for forming the select gate is used as a mask in the second dielectric layer etching process, an additional mask additional cost does not occur.

Claims (10)

A floating gate formed on the substrate and electrically separated from the substrate; A first dielectric layer formed of a nitride layer-based material in a portion of the floating gate; An oxide-based second dielectric layer formed on the floating gate to cover the first dielectric layer; A select gate formed on the second dielectric layer; And Source / drain formed in the substrate exposed to both sides of the floating gate Nonvolatile memory device comprising a. The method of claim 1, And the first dielectric layer has an ONO structure. The method according to claim 1 or 2, And the floating gate is electrically separated from the substrate by a tunnel oxide layer. The method of claim 3, wherein And the floating gate and the select gate are formed of a polysilicon layer. Forming a floating gate on the substrate, the floating gate being electrically separated from the substrate; Forming a first dielectric layer including a nitride based material on a portion of the floating gate; Sequentially depositing an oxide-based second dielectric layer and a select gate electrode material along a step of an upper portion of the entire structure including the first dielectric layer; Forming a select gate on the second dielectric layer by etching the second dielectric layer and the electrode material for the select gate to form a second dielectric layer covering the floating gate and the first dielectric layer; And Forming a source / drain in the substrate exposed to both sides of the floating gate Nonvolatile memory device manufacturing method comprising a. The method of claim 5, Forming the first dielectric layer, Depositing the first dielectric layer along a stepped portion of the substrate including the floating gate; And Etching the first dielectric layer to expose both sides of the floating gate. Nonvolatile memory device manufacturing method comprising a. The method of claim 6, And forming the first dielectric layer in an ONO structure. The method according to any one of claims 5 to 7, Forming the floating gate, Forming a tunnel oxide film on the substrate; Depositing an electrode material for the floating gate on the tunnel oxide layer; And Etching the floating gate electrode material and the tunnel oxide layer Nonvolatile memory device manufacturing method comprising a. The method of claim 8, And the floating gate is electrically separated from the substrate by the tunnel oxide layer. The method according to any one of claims 5 to 7, And the floating gate and the select gate are formed of a polysilicon layer.

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