KR101116943B1 - 스위칭 네트워크를 사용하여 프로그래머블 로직을 구축하기 위한, 집적 회로, 전자 시스템, 방법, 상기 집적 회로의 접속 방법 및 상기 전자 시스템을 제공하는 방법 - Google Patents
스위칭 네트워크를 사용하여 프로그래머블 로직을 구축하기 위한, 집적 회로, 전자 시스템, 방법, 상기 집적 회로의 접속 방법 및 상기 전자 시스템을 제공하는 방법 Download PDFInfo
- Publication number
- KR101116943B1 KR101116943B1 KR1020067022720A KR20067022720A KR101116943B1 KR 101116943 B1 KR101116943 B1 KR 101116943B1 KR 1020067022720 A KR1020067022720 A KR 1020067022720A KR 20067022720 A KR20067022720 A KR 20067022720A KR 101116943 B1 KR101116943 B1 KR 101116943B1
- Authority
- KR
- South Korea
- Prior art keywords
- conductors
- leads
- switches
- sets
- switching network
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/814,943 US6975139B2 (en) | 2004-03-30 | 2004-03-30 | Scalable non-blocking switching network for programmable logic |
| US10/814,943 | 2004-03-30 | ||
| PCT/US2005/006583 WO2005104375A1 (en) | 2004-03-30 | 2005-02-28 | A scalable non-blocking switching network for programmable logic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070024520A KR20070024520A (ko) | 2007-03-02 |
| KR101116943B1 true KR101116943B1 (ko) | 2012-03-16 |
Family
ID=35053582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020067022720A Expired - Fee Related KR101116943B1 (ko) | 2004-03-30 | 2005-02-28 | 스위칭 네트워크를 사용하여 프로그래머블 로직을 구축하기 위한, 집적 회로, 전자 시스템, 방법, 상기 집적 회로의 접속 방법 및 상기 전자 시스템을 제공하는 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (9) | US6975139B2 (https=) |
| EP (1) | EP1730841A4 (https=) |
| JP (1) | JP4588068B2 (https=) |
| KR (1) | KR101116943B1 (https=) |
| CN (2) | CN1938950B (https=) |
| WO (1) | WO2005104375A1 (https=) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5457410A (en) | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
| US6975139B2 (en) * | 2004-03-30 | 2005-12-13 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
| US7460529B2 (en) * | 2004-07-29 | 2008-12-02 | Advantage Logic, Inc. | Interconnection fabric using switching networks in hierarchy |
| US7423453B1 (en) * | 2006-01-20 | 2008-09-09 | Advantage Logic, Inc. | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
| US9345921B2 (en) | 2007-07-11 | 2016-05-24 | Performance Solutions, Llc | Therapeutic, fitness, and sports enhancement device |
| US7924052B1 (en) | 2008-01-30 | 2011-04-12 | Actel Corporation | Field programmable gate array architecture having Clos network-based input interconnect |
| US7924053B1 (en) | 2008-01-30 | 2011-04-12 | Actel Corporation | Clustered field programmable gate array architecture |
| WO2009147789A1 (ja) * | 2008-06-06 | 2009-12-10 | 日本電気株式会社 | 回路設計システムおよび回路設計方法 |
| US7714611B1 (en) * | 2008-12-03 | 2010-05-11 | Advantage Logic, Inc. | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
| US7705629B1 (en) | 2008-12-03 | 2010-04-27 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
| US7999570B2 (en) * | 2009-06-24 | 2011-08-16 | Advantage Logic, Inc. | Enhanced permutable switching network with multicasting signals for interconnection fabric |
| US8341580B2 (en) * | 2009-09-28 | 2012-12-25 | Advantage Logic, Inc. | Modular routing fabric using switching networks |
| US8665727B1 (en) | 2010-06-21 | 2014-03-04 | Xilinx, Inc. | Placement and routing for a multiplexer-based interconnection network |
| US8098081B1 (en) | 2010-06-21 | 2012-01-17 | Xilinx, Inc. | Optimization of interconnection networks |
| US7982497B1 (en) * | 2010-06-21 | 2011-07-19 | Xilinx, Inc. | Multiplexer-based interconnection network |
| KR101646431B1 (ko) * | 2012-03-30 | 2016-08-05 | 인텔 코포레이션 | 프로그램가능 장치 어레이들을 위한 스핀 전달 토크 기반 메모리 요소들 |
| US9118325B1 (en) * | 2014-08-27 | 2015-08-25 | Quicklogic Corporation | Routing network for programmable logic device |
| CN108287935B (zh) * | 2017-12-13 | 2020-08-04 | 京微齐力(北京)科技有限公司 | 一种包含可预分配布线结构的可编程器件 |
| CN111753486B (zh) * | 2020-06-30 | 2021-12-24 | 无锡中微亿芯有限公司 | 一种多裸片结构fpga的布局方法 |
| CN115496024B (zh) * | 2021-06-18 | 2025-09-12 | 易灵思有限公司 | 现场可编程逻辑门阵列 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5880597A (en) * | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
| US6163168A (en) * | 1998-12-09 | 2000-12-19 | Vantis Corporation | Efficient interconnect network for use in FPGA device having variable grain architecture |
| US6670825B1 (en) * | 1998-11-18 | 2003-12-30 | Altera Corporation | Efficient arrangement of interconnection resources on programmable logic devices |
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| US7460529B2 (en) * | 2004-07-29 | 2008-12-02 | Advantage Logic, Inc. | Interconnection fabric using switching networks in hierarchy |
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| KR100833179B1 (ko) * | 2006-02-15 | 2008-05-28 | 삼성전자주식회사 | 클러스터드 전압 스케일링을 위한 레벨 컨버팅 플립플롭 및펄스 발생기 |
| US7705629B1 (en) * | 2008-12-03 | 2010-04-27 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
| US7714611B1 (en) * | 2008-12-03 | 2010-05-11 | Advantage Logic, Inc. | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
-
2004
- 2004-03-30 US US10/814,943 patent/US6975139B2/en not_active Expired - Lifetime
-
2005
- 2005-02-28 EP EP05724178A patent/EP1730841A4/en not_active Ceased
- 2005-02-28 CN CN200580010432XA patent/CN1938950B/zh not_active Expired - Fee Related
- 2005-02-28 KR KR1020067022720A patent/KR101116943B1/ko not_active Expired - Fee Related
- 2005-02-28 JP JP2007506180A patent/JP4588068B2/ja not_active Expired - Fee Related
- 2005-02-28 CN CN201110439666.3A patent/CN102571073B/zh not_active Expired - Fee Related
- 2005-02-28 WO PCT/US2005/006583 patent/WO2005104375A1/en not_active Ceased
- 2005-09-01 US US11/218,419 patent/US7256614B2/en not_active Expired - Lifetime
-
2007
- 2007-06-26 US US11/823,257 patent/US7417457B2/en not_active Expired - Lifetime
-
2008
- 2008-07-16 US US12/174,080 patent/US7557613B2/en not_active Expired - Lifetime
-
2009
- 2009-05-26 US US12/472,305 patent/US7768302B2/en not_active Expired - Fee Related
-
2010
- 2010-06-04 US US12/794,685 patent/US7863932B2/en not_active Expired - Fee Related
- 2010-11-29 US US12/955,738 patent/US7986163B2/en not_active Expired - Fee Related
-
2011
- 2011-06-21 US US13/165,668 patent/US8242807B2/en not_active Expired - Fee Related
-
2012
- 2012-07-17 US US13/551,011 patent/US8698519B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5880597A (en) * | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
| US6670825B1 (en) * | 1998-11-18 | 2003-12-30 | Altera Corporation | Efficient arrangement of interconnection resources on programmable logic devices |
| US6163168A (en) * | 1998-12-09 | 2000-12-19 | Vantis Corporation | Efficient interconnect network for use in FPGA device having variable grain architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| US20110089972A1 (en) | 2011-04-21 |
| US7986163B2 (en) | 2011-07-26 |
| KR20070024520A (ko) | 2007-03-02 |
| JP2007531461A (ja) | 2007-11-01 |
| JP4588068B2 (ja) | 2010-11-24 |
| US20120280712A1 (en) | 2012-11-08 |
| US20050218928A1 (en) | 2005-10-06 |
| US20070268041A1 (en) | 2007-11-22 |
| US20090273368A1 (en) | 2009-11-05 |
| US7863932B2 (en) | 2011-01-04 |
| WO2005104375A1 (en) | 2005-11-03 |
| US6975139B2 (en) | 2005-12-13 |
| US7557613B2 (en) | 2009-07-07 |
| CN1938950B (zh) | 2012-02-29 |
| US7417457B2 (en) | 2008-08-26 |
| US20060006906A1 (en) | 2006-01-12 |
| CN102571073B (zh) | 2015-07-08 |
| EP1730841A1 (en) | 2006-12-13 |
| US20100244895A1 (en) | 2010-09-30 |
| US8242807B2 (en) | 2012-08-14 |
| US20110248744A1 (en) | 2011-10-13 |
| CN1938950A (zh) | 2007-03-28 |
| EP1730841A4 (en) | 2007-08-29 |
| US7256614B2 (en) | 2007-08-14 |
| US20080272806A1 (en) | 2008-11-06 |
| CN102571073A (zh) | 2012-07-11 |
| US7768302B2 (en) | 2010-08-03 |
| US8698519B2 (en) | 2014-04-15 |
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