KR101107349B1 - 커맨드 데이터의 복제를 지원하는 고용량 메모리 서브시스템용 메모리 칩 - Google Patents
커맨드 데이터의 복제를 지원하는 고용량 메모리 서브시스템용 메모리 칩 Download PDFInfo
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- KR101107349B1 KR101107349B1 KR1020097016070A KR20097016070A KR101107349B1 KR 101107349 B1 KR101107349 B1 KR 101107349B1 KR 1020097016070 A KR1020097016070 A KR 1020097016070A KR 20097016070 A KR20097016070 A KR 20097016070A KR 101107349 B1 KR101107349 B1 KR 101107349B1
- Authority
- KR
- South Korea
- Prior art keywords
- data
- memory
- memory module
- chip
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/769,001 | 2007-06-27 | ||
| US11/769,001 US7822936B2 (en) | 2007-06-27 | 2007-06-27 | Memory chip for high capacity memory subsystem supporting replication of command data |
| PCT/EP2008/058082 WO2009000857A1 (en) | 2007-06-27 | 2008-06-25 | Memory chip for high capacity memory subsystem supporting replication of command data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20090115130A KR20090115130A (ko) | 2009-11-04 |
| KR101107349B1 true KR101107349B1 (ko) | 2012-01-19 |
Family
ID=39791330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020097016070A Active KR101107349B1 (ko) | 2007-06-27 | 2008-06-25 | 커맨드 데이터의 복제를 지원하는 고용량 메모리 서브시스템용 메모리 칩 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7822936B2 (https=) |
| EP (1) | EP2160687B1 (https=) |
| JP (1) | JP4824126B2 (https=) |
| KR (1) | KR101107349B1 (https=) |
| CN (1) | CN101681322B (https=) |
| AT (1) | ATE479947T1 (https=) |
| DE (1) | DE602008002436D1 (https=) |
| WO (1) | WO2009000857A1 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9123409B2 (en) | 2009-06-11 | 2015-09-01 | Micron Technology, Inc. | Memory device for a hierarchical memory architecture |
| US9117496B2 (en) | 2012-01-30 | 2015-08-25 | Rambus Inc. | Memory device comprising programmable command-and-address and/or data interfaces |
| US8788748B2 (en) | 2012-03-22 | 2014-07-22 | International Business Machines Corporation | Implementing memory interface with configurable bandwidth |
| CN103150006A (zh) * | 2013-03-25 | 2013-06-12 | 西安华芯半导体有限公司 | Dram存储器的省电方法 |
| US9324389B2 (en) * | 2013-05-29 | 2016-04-26 | Sandisk Technologies Inc. | High performance system topology for NAND memory systems |
| US9728526B2 (en) | 2013-05-29 | 2017-08-08 | Sandisk Technologies Llc | Packaging of high performance system topology for NAND memory systems |
| WO2014193592A2 (en) * | 2013-05-29 | 2014-12-04 | Sandisk Technologies Inc. | High performance system topology for nand memory systems |
| US9703702B2 (en) * | 2013-12-23 | 2017-07-11 | Sandisk Technologies Llc | Addressing auto address assignment and auto-routing in NAND memory network |
| CN104268121B (zh) * | 2014-09-23 | 2017-08-11 | 浪潮(北京)电子信息产业有限公司 | 超大规模芯片中访问寄存器的方法及系统 |
| TWI588658B (zh) * | 2015-10-20 | 2017-06-21 | 旺宏電子股份有限公司 | I/o匯流排共用記憶體系統 |
| US9841922B2 (en) | 2016-02-03 | 2017-12-12 | SK Hynix Inc. | Memory system includes a memory controller |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070058409A1 (en) * | 2005-09-15 | 2007-03-15 | Hermann Ruckerbauer | Semiconductor memory arrangement with branched control and address bus |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5893927A (en) | 1996-09-13 | 1999-04-13 | International Business Machines Corporation | Memory device having programmable device width, method of programming, and method of setting device width for memory device |
| US7356639B2 (en) | 2000-01-05 | 2008-04-08 | Rambus Inc. | Configurable width buffered module having a bypass circuit |
| US6502161B1 (en) * | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
| JP2002063791A (ja) | 2000-08-21 | 2002-02-28 | Mitsubishi Electric Corp | 半導体記憶装置およびメモリシステム |
| US6493250B2 (en) * | 2000-12-28 | 2002-12-10 | Intel Corporation | Multi-tier point-to-point buffered memory interface |
| US7085866B1 (en) | 2002-02-19 | 2006-08-01 | Hobson Richard F | Hierarchical bus structure and memory access protocol for multiprocessor systems |
| DE10318603B4 (de) * | 2003-04-24 | 2005-03-10 | Infineon Technologies Ag | Eingangsempfängerschaltung |
| US20040243769A1 (en) | 2003-05-30 | 2004-12-02 | Frame David W. | Tree based memory structure |
| US7120727B2 (en) * | 2003-06-19 | 2006-10-10 | Micron Technology, Inc. | Reconfigurable memory module and method |
| US7136958B2 (en) | 2003-08-28 | 2006-11-14 | Micron Technology, Inc. | Multiple processor system and method including multiple memory hub modules |
| JP4741226B2 (ja) * | 2003-12-25 | 2011-08-03 | 株式会社日立製作所 | 半導体メモリモジュール、およびメモリシステム |
| US7216196B2 (en) * | 2003-12-29 | 2007-05-08 | Micron Technology, Inc. | Memory hub and method for memory system performance monitoring |
| US7188219B2 (en) * | 2004-01-30 | 2007-03-06 | Micron Technology, Inc. | Buffer control system and method for a memory system having outstanding read and write request buffers |
| US7366864B2 (en) * | 2004-03-08 | 2008-04-29 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
| US7120723B2 (en) * | 2004-03-25 | 2006-10-10 | Micron Technology, Inc. | System and method for memory hub-based expansion bus |
| US20060036826A1 (en) | 2004-07-30 | 2006-02-16 | International Business Machines Corporation | System, method and storage medium for providing a bus speed multiplier |
| EP2383660B1 (en) | 2005-04-21 | 2013-06-26 | Violin Memory, Inc. | Interconnection system |
| US8200887B2 (en) | 2007-03-29 | 2012-06-12 | Violin Memory, Inc. | Memory management system and method |
| US20060245226A1 (en) | 2005-05-02 | 2006-11-02 | Inphi Corporation | Fully buffered DIMM architecture and protocol |
| US7397684B2 (en) | 2005-09-15 | 2008-07-08 | Infineon Technologies, Ag | Semiconductor memory array with serial control/address bus |
| US20070079057A1 (en) | 2005-09-30 | 2007-04-05 | Hermann Ruckerbauer | Semiconductor memory system and memory module |
| US7378868B2 (en) * | 2006-01-19 | 2008-05-27 | Altera Corporation | Modular I/O bank architecture |
| DE102006045113B3 (de) | 2006-09-25 | 2008-04-03 | Qimonda Ag | Speichermodul-System, Speichermodul, Buffer-Bauelement, Speichermodul-Platine, und Verfahren zum Betreiben eines Speichermoduls |
-
2007
- 2007-06-27 US US11/769,001 patent/US7822936B2/en active Active
-
2008
- 2008-06-25 CN CN2008800155062A patent/CN101681322B/zh active Active
- 2008-06-25 EP EP08761364A patent/EP2160687B1/en active Active
- 2008-06-25 DE DE602008002436T patent/DE602008002436D1/de active Active
- 2008-06-25 JP JP2010513903A patent/JP4824126B2/ja not_active Expired - Fee Related
- 2008-06-25 KR KR1020097016070A patent/KR101107349B1/ko active Active
- 2008-06-25 WO PCT/EP2008/058082 patent/WO2009000857A1/en not_active Ceased
- 2008-06-25 AT AT08761364T patent/ATE479947T1/de not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070058409A1 (en) * | 2005-09-15 | 2007-03-15 | Hermann Ruckerbauer | Semiconductor memory arrangement with branched control and address bus |
Also Published As
| Publication number | Publication date |
|---|---|
| DE602008002436D1 (de) | 2010-10-14 |
| US7822936B2 (en) | 2010-10-26 |
| JP4824126B2 (ja) | 2011-11-30 |
| WO2009000857A1 (en) | 2008-12-31 |
| US20090006772A1 (en) | 2009-01-01 |
| JP2010531501A (ja) | 2010-09-24 |
| EP2160687A1 (en) | 2010-03-10 |
| CN101681322A (zh) | 2010-03-24 |
| ATE479947T1 (de) | 2010-09-15 |
| EP2160687B1 (en) | 2010-09-01 |
| KR20090115130A (ko) | 2009-11-04 |
| CN101681322B (zh) | 2012-09-05 |
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