KR101102774B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

Disclosure of Invention The present invention provides a method of manufacturing a semiconductor device capable of securing threshold voltage characteristics required by each transistor through a single process in a power control semiconductor device having a plurality of transistors having different process elements from each other. According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming an active region having a structure in which a first deep well of a first conductive type and a second deep well of a second conductive type are bonded to a substrate; A first impurity region of a first conductivity type is formed in the first deep well of the substrate, and the first impurity region extends to the channel scheduled region of the substrate so that the first impurity region and the channel scheduled region overlap each other. Forming a; Forming a gate having a structure in which the first deep well and the second deep well are simultaneously crossed on the substrate, and a gate insulating film and a gate electrode are sequentially stacked; And forming a source region and a drain region of a second conductivity type in the first deep well on the gate side and the second deep well on the other side of the gate, respectively. In a semiconductor device having a structure in which a plurality of transistors having different process elements such as impurity doping concentration in an active region and a thickness of a gate insulating film are integrated on a single substrate, the threshold voltage characteristics required by each transistor are easily maintained while maintaining breakdown voltage characteristics. There is an effect that can be secured.

Impurity Region, Gate, Expansion, Overlap, Channel

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a manufacturing method of a power control semiconductor device.

The semiconductor device for power control has a structure in which a plurality of transistors having different process elements such as impurity doping concentration in the active region and thickness of the gate insulating film are integrated on one substrate according to required characteristics, and an extended drain (EDMOS) MOS) transistors are often used. In designing such a power control semiconductor device, it is well known that a threshold voltage (VT) characteristic must be secured while maintaining a breakdown voltage (BV) characteristic required by each transistor.

1 is a cross-sectional view showing a semiconductor device for power control according to the prior art. Here, a power control semiconductor device composed of EDMOS transistors having N channels is illustrated.

Referring to FIG. 1, a method of manufacturing a power control semiconductor device according to the related art is described. Referring to FIG. After the N type second deep wells 13A and 13B are formed, the device isolation layer 14 is formed to form the active regions 24A and 12B where the first deep wells 12A and 12B and the second deep wells 13A and 13B are joined to each other. 24B).

Subsequently, impurities are implanted into a portion of the substrate 11 on which the first deep wells 12A and 12B are formed to form P-type first impurity regions 15A and 15B, and the second deep wells 13A and 13B are formed. (11) An ion is implanted into a portion to form N-type second impurity regions 16A and 16B.

Next, a mask pattern for opening the channel region C is formed on the substrate 11, and an ion implantation process is performed on the mask pattern as an injection barrier, so that the threshold voltage adjusting layers 17A, 17B).

Next, gate insulating films 18A and 18B are formed on the substrate 11. At this time, the gate insulating films 18A and 18B form different thicknesses of the gate insulating films 18A and 18B formed in the first and second regions (T1? T2).

Next, after the gate conductive film is formed over the entire surface of the substrate 11, the gate conductive film and the gate insulating films 18A and 18B are sequentially etched to form the gate insulating films 18A and 18B and the gate electrodes in the first and second regions, respectively. 19A and 19B are sequentially stacked to form gates that simultaneously cross the first deep wells 12A and 12B and the second deep wells 13A and 13B.

Next, the P-type pickup regions 21A and 21B in the first impurity regions 15A and 15B, the N-type source regions 22A and 22B in the first deep well and the N-type drains in the second impurity regions 16A and 16B. The regions 23A and 23B are formed.

Since the power control semiconductor device formed through the above-described process typically has a large operating voltage, impurities in the first deep wells 12A and 12B and the second deep wells 13A and 13B are conventionally used to secure breakdown voltage characteristics. Low doping concentration. As such, when the impurity doping concentrations of the first deep wells 12A and 12B and the second deep wells 13A and 13B are lowered in order to ensure breakdown voltage characteristics, a threshold voltage of the transistor may decrease rapidly. In addition, as the thickness of the gate insulating films 18A and 18B decreases in the state where the impurity doping concentrations of the first and second deep wells 12A and 12B and the second deep wells 13A and 13B are formed low, the magnitude of the threshold voltage is further reduced. This happens.

In order to solve this problem, the prior art has no choice but to form the threshold voltage adjusting layers 17A and 17B in the channel region C of the substrate 11 through a mask process and an ion implantation process. For reference, the channel region C of the EDMOS transistor may be defined as a surface region of the substrate 11 in a region where the gate electrodes 19A and 19B and the first deep wells 12A and 12B overlap.

However, considering the impurity doping concentrations of the first and second deep wells 12A and 12B and 13A and 13B and the thicknesses of the gate insulating films 18A and 18B, the transistors formed in the respective regions may have different characteristics (for example, impurities). Has to be formed to have the threshold voltage adjusting layers 17A and 17B to have a conductivity type, an impurity type or an ion implantation amount, and thus a process step increases, and manufacturing cost and manufacturing time increase.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and in the power control semiconductor device in which a plurality of transistors having different process elements are integrated, the threshold voltage characteristics required by each transistor through one process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be secured.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device which can easily secure a threshold voltage characteristic while maintaining a breakdown voltage characteristic in a power control semiconductor device.

In accordance with an aspect of the present invention, a method of manufacturing a semiconductor device includes: forming an active region having a structure in which a first deep well of a first conductive type and a second deep well of a second conductive type are bonded to a substrate; A first impurity region of a first conductivity type is formed in the first deep well of the substrate, and the first impurity region extends to the channel scheduled region of the substrate so that the first impurity region and the channel scheduled region overlap each other. Forming a; Forming a gate having a structure in which the first deep well and the second deep well are simultaneously crossed on the substrate, and a gate insulating film and a gate electrode are sequentially stacked; And forming a source region and a drain region of a second conductivity type in the first deep well on the gate side and the second deep well on the other side of the gate, respectively.

The overlapping region may be formed within a range from the source region to an interface between the first deep well and the second deep well. The line width (or area) of the overlap region may gradually increase from the source region toward the drain region.

The impurity doping concentration of the first impurity region may be higher than the impurity doping concentration of the first deep well.

The method may further include forming a pickup region of a first conductivity type in the first impurity region to be spaced apart from the source region by a predetermined distance. The source region and the pickup region may be formed in the first impurity region.

The method may further include defining the active region on the substrate before forming the first impurity region, and forming an isolation layer to partially overlap the region where the gate is to be formed. The device isolation layer may be formed through a shallow trench isolation (STI) process.

The method may further include forming a second impurity region of a second conductivity type surrounding the drain region in the second deep well before forming the gate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming an active region having a structure in which a first deep well of a first conductive type and a second deep well of a second conductive type are bonded to a substrate. ; Forming a first impurity region of a first conductivity type in the first deep well so as to be spaced apart from the channel expected region of the substrate by a predetermined distance; Extending the first impurity region to a channel expected region of the substrate through heat treatment to form an overlapping region in which the first impurity region and the channel scheduled region overlap each other; Forming a gate having a structure in which the first deep well and the second deep well are simultaneously crossed on the substrate, and a gate insulating film and a gate electrode are sequentially stacked; And forming a source region and a drain region of a second conductivity type in the first deep well on the gate side and the second deep well on the other side of the gate, respectively.

The overlapping region may be formed within a range from the source region to an interface between the first deep well and the second deep well. The line width (or area) of the overlap region may be gradually increased from the source region to the drain direction.

The impurity doping concentration of the first impurity region in the overlap region may be formed to have a gradient. An impurity doping concentration of the first impurity region in the overlap region may be gradually decreased from the source region toward the drain region.

The impurity doping concentration of the first impurity region may be higher than the impurity doping concentration of the first deep well.

The method may further include forming a pickup region of a first conductivity type in the first impurity region to be spaced apart from the source region by a predetermined distance. The source region and the pickup region may be formed in the first impurity region.

The method may further include defining the active region on the substrate before forming the first impurity region, and forming an isolation layer to partially overlap the region where the gate is to be formed. The device isolation layer may be formed through an STI process.

The method may further include forming a second impurity region of a second conductivity type surrounding the drain region in the second deep well before forming the gate.

According to the present invention based on the above-described problem solving means, a semiconductor having a structure in which a plurality of transistors having different process elements such as impurity doping concentration of active region and thickness of gate insulating film are integrated on one substrate by forming an overlap region. While maintaining the breakdown voltage characteristics in the device, it is possible to easily obtain the threshold voltage characteristics required by each transistor.

In addition, in the present invention, by forming an overlap region, an ion implantation process may be performed for each transistor to form a threshold voltage characteristic required by each transistor through a single ion implantation process without forming a threshold voltage control layer. There is an effect that can reduce the manufacturing cost and manufacturing cost by simplifying the process staff of the semiconductor device through this.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

In the embodiments of the present invention described below, a power control semiconductor device having a structure in which a plurality of transistors having different process elements such as impurity doping concentration in an active region and a thickness of a gate insulating film are integrated on a single substrate is broken down. Provides a method of manufacturing a semiconductor device that can secure the threshold voltage (VT) characteristics while maintaining the voltage (Brakdown Voltage, BV), and can obtain the threshold voltage characteristics required by each transistor through a single process. do. To this end, the present invention extends the impurity region formed to surround the pickup region to the substrate under the gate electrode to form an overlap region in which the impurity region and the gate electrode overlap, thereby securing the threshold voltage characteristics of the semiconductor device, It is a technical idea to adjust the size of the line width (or area) of an area to secure each threshold voltage characteristic required by a plurality of transistors having different process elements at once.

In the following description, a case where the technical subject matter of the present invention is applied to an EDMOS transistor having N channels will be described. Therefore, in the following description, the first conductivity type is P type and the second conductivity type is N type. Of course, the technical gist of the present invention can be equally applied to an EDMOS transistor having a P channel, in which case the first conductive type is N type and the second conductive type is P type.

First, the technical principle implementation principle of the present invention described above with reference to FIGS. 2A and 2B will be described in detail.

2A and 2B illustrate a semiconductor device to which the technical subject matter of the present invention is applied. FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along the line X-X 'of FIG. 2A.

As shown in FIGS. 2A and 2B, the EDMOS transistor to which the technical subject matter of the present invention is applied includes a first deep well 32 having a first conductivity type and a second deep well 33 having a second conductivity type formed on a substrate 31. , An active region 34 defined by an isolation layer 42 formed on the substrate 31 and having a structure in which the first deep well 32 and the second deep well 33 are bonded to each other, and a first deep well on the substrate 31. 32 and the gate electrode 41 crossing the second deep well 33 at the same time, the gate insulating film 40 interposed between the substrate 31 and the gate electrode 41, the gate electrode 41 is aligned to one end The first conductive type source region 37 formed in the first deep well 32, the first conductive type pickup region 38 formed in the first deep well 32, and the first deep well spaced apart from the source region 37 by a predetermined distance. The first impurity region 39 and the gate electrode 41 of the first conductivity type, which are formed in the 32 and surround the pick-up region 38, and have a overlap region O partially overlapped with a portion of the gate electrode 41. ) From the other end The second conductive type drain region 35 formed in the second deep well 33 spaced apart from each other, and the second impurity region 36 of the second conductive type formed in the second deep well 33 and surrounding the drain region 35. ).

Here, the first impurity region 39 serves to improve the contact characteristics between the first deep well 32 and the pickup region 38 and to adjust the threshold voltage, which is larger than the first deep well 32. It may have an impurity doping concentration, and may have a lower impurity doping concentration than the pickup region 38. The second impurity region 36 acts as an extended drain region 35 to improve stability of the drain region 35 during operation, and has a higher impurity doping concentration than the second deep well 33. It may have a lower impurity doping concentration than the drain region 35. In addition, the device isolation layer 42 may be formed through a shallow trench isolation (STI) process, and the device isolation layer 42 between the gate electrode 41 and the drain region 35 may be partially disposed under the gate electrode 41. It may have a nested structure.

In general, the threshold voltage value of the transistor is proportional to the impurity doping concentration of the active region 34 and the thickness of the gate insulating layer 40. That is, when either the impurity doping concentration of the active region 34 or the thickness of the gate insulating film 40 decreases, the magnitude of the threshold voltage also decreases. In this case, since the impurity doping concentration of the active region 34 has a great influence on the breakdown voltage characteristic of the semiconductor device, it is not easy to adjust the impurity doping concentration of the active region 34 to secure the threshold voltage characteristic. When using the method of controlling the thickness of the gate insulating film 40 for each transistor in order to secure the threshold voltage characteristic, a plurality of deposition processes (or growth processes), mask processes, and etching processes are required. This may increase the productivity of the semiconductor device and reduce the film quality of the gate insulating film 40.

However, in the semiconductor device having the above-described structure, the first impurity region 39 extends (or expands) in the channel length direction (X-X 'direction) so that the first impurity region 39 and the gate electrode 41 overlap each other. By forming an overlapping overlapping region O to locally increase the impurity doping concentration of the channel region C, the impurity doping concentration of the active region 34 and the thickness of the gate insulating film 40 are not required. The threshold voltage characteristic of the semiconductor device can be easily ensured.

Specifically, since the first impurity region 39 has an impurity doping concentration in the active region 34, particularly, the impurity doping concentration is greater than that of the first deep well 32 having the same conductivity type as the first impurity region 39. The threshold voltage of the semiconductor device may be increased through the region O, and as the line width (or area) of the overlapping region O increases, the threshold voltage may be further increased.

Here, the overlapping region O is located in the channel region C, that is, the overlapping region O is located within the range from the source region 37 to the boundary surface where the first and second deep wells 32 and 33 are in contact with each other. It is preferable to form. In the case where the line width (or area) of the overlapping region O is increased, it is preferable to gradually increase the source region 37 toward the drain region 35 from the viewpoint.

In addition, the impurity doping concentration of the first impurity region 39 in the overlapping region O may have a constant value (see the first embodiment of the present invention) or may have a gradient (the second embodiment of the present invention). Reference). At this time, when the impurity doping concentration of the first impurity region 39 in the overlapping region O has a gradient, the first impurity region in the overlapping region O gradually increases from the source region 37 toward the drain region 35. It is more preferable to form such that the impurity doping concentration of 39) is reduced.

As described above, the semiconductor device to which the technical spirit of the present invention is applied is for power control in which a plurality of transistors having different process elements such as the doping concentration of the active region 34 and the thickness of the gate insulating layer 40 are integrated through the overlap region O. FIG. While maintaining the breakdown voltage characteristic in the semiconductor device, it is possible to secure the threshold voltage characteristic required by each transistor. In particular, the process to simplify the process of forming a threshold voltage control layer through the mask process and the ion implantation process to secure the threshold voltage characteristics, it is possible to reduce the manufacturing cost and manufacturing cost.

In addition, since the line width (or area) of the overlapped region O gradually increases from the source region 37 to the drain region 35 in accordance with the required threshold voltage characteristic, the threshold voltage is increased through the overlapped region O. As a result, degradation of the breakdown voltage characteristic can be prevented. In addition, when the impurity doping concentration of the first impurity region 39 in the overlap region O is formed to have a gradient, it is possible to prevent the breakdown voltage characteristic from being deteriorated more effectively.

Specifically, the impurity doping concentration of the channel region C adjacent to the drift region, that is, the active region 34 adjacent to the interface between the first and second deep wells 32 and 33 below the gate electrode 41 is determined. Since it can be kept low, the breakdown voltage characteristic can be prevented from being deteriorated even when the magnitude of the threshold voltage is increased through the overlap region (O). For reference, a drift region may be referred to as a drift region from an interface where the first deep well 32 and the second deep well 33 are in contact with each other under the gate electrode 41, that is, from the point where the channel region C ends to the drain region 35.

In addition, the doping concentration on the surface of the substrate 31 in the channel region C adjacent to the drift region can be relatively lower than the technique of forming the threshold voltage adjusting layer through the mask process and the ion implantation process to secure the threshold voltage characteristics. Since it is possible to improve the surface mobility (carrier) of the carrier (surface mobility), there is an advantage that can increase the operating current through this.

Hereinafter, embodiments of the present invention will be described in detail with respect to a manufacturing method of a semiconductor device to which the technical subject matter of the present invention is applied.

Example 1

 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 3A, impurities of the first conductivity type and the second conductivity type are ion implanted into each region of the substrate 51 having the first region and the second region, and the implanted impurities are implanted. A heat treatment process for activating is performed to form first deep wells 52A and 52B of the first conductivity type and second deep wells 53A and 53B of the second conductivity type.

Next, the active regions 54A and 54B having a structure in which the first deep wells 52A and 52B and the second deep wells 53A and 53B are bonded to the substrate 51 are defined, and partially overlap with the region where the gate is to be formed. The device isolation film 55 is formed as much as possible. In this case, the device isolation layer 55 may be formed by a shallow trench isolation (STI) process.

Next, the first conductive type and the second conductive type are ion-implanted into a predetermined region of the substrate 51, and a heat treatment is performed to activate the implanted impurities. The first impurity regions 57 and 58 of the type are formed, and the second impurity regions 56A and 56B of the second conductive type are formed in the second deep wells 53A and 53B. In this case, it is preferable that the impurity doping concentration of the first impurity regions 57 and 58 is larger than the impurity doping concentration of the first deep wells 52A and 52B. Further, the heat treatment for forming the first impurity regions 57 and 58 and the second impurity regions 56A and 56B rather than the heat treatment process for forming the first deep wells 52A and 52B and the second deep wells 53A and 53B. It is desirable to proceed the process at lower temperatures.

Here, the first impurity regions 57 and 58 are formed by ion implanting impurities of the first conductivity type into the first deep wells 52A and 52B in each region, and the first impurity regions 57 and 58 are formed as channel regions ( By extending to the region where C) is to be formed, overlap regions O1 and O2 overlapping the regions where the first impurity regions 57 and 58 and the channel region C are to be formed are formed. At this time, if the area where overlap regions O1 and O2 are formed in each region is adjusted according to the threshold voltage characteristic required by the semiconductor device to be formed in each region, the region is formed in each region through one ion implantation process and heat treatment process. The threshold voltage characteristic required by the semiconductor device to be obtained can be secured.

For example, in the first embodiment of the present invention, the impurity doping concentrations of the active regions 54A and 54B of the first region and the second region are the same, and the threshold required by the semiconductor device to be formed in the first region and the second region is required. The voltages are the same, but when the thickness of the gate insulating film formed in the first region is thicker than the thickness of the gate insulating film to be formed in the second region, the voltage is larger than the line width (or area) of the overlap region O1 formed in the first region. By forming a larger line width (or area) of the overlapping region O2 formed in the region, it is possible to secure all the threshold voltage characteristics required by the semiconductor devices to be formed in the first region and the second region.

As shown in FIG. 3B, the gate insulating films 59A and 59B are formed on the substrate 51, and the thickness T1 of the gate insulating film 59A formed on the substrate 51 of the first region is second. It is formed larger than the thickness T2 of the gate insulating film 59B formed on the substrate 51 in the region (T1> T2).

Next, after the gate conductive film is deposited on the entire surface of the substrate 51, the gate conductive film and the gate insulating films 59A and 59B are sequentially etched to sequentially etch the first and second deep wells 52A and 52B and 53A into the respective regions. And 53B at the same time, a gate having a structure in which the gate insulating films 59A and 59B and the gate electrode 60 are sequentially stacked is formed.

As shown in FIG. 3C, the source regions 62A and 62B are ion-implanted with impurities of the second conductivity type in the first deep wells 52A and 52B in the substrate 51 to be aligned at one end of the gate electrode 60. ), And ion-implanted impurities of the second conductive type into the second impurity regions 56A and 56B in the substrate 51 so as to be spaced a predetermined distance from the other end of the gate electrode 60 to drain regions 63A and 63B. ).

Next, the first conductive type pickup regions 61A and 61B are formed by ion implanting impurities of the first conductive type into the first impurity regions 57 and 58 so as to be spaced apart from the source regions 62A and 62B at predetermined intervals. .

Next, a heat treatment process for activating impurities injected into the pickup regions 61A and 61B, the source regions 62A and 62B and the drain regions 63A and 63B is performed.

As described above, in the method of manufacturing the semiconductor device according to the first embodiment of the present invention, the dopant concentration in the active regions 54A and 54B and the thickness of the gate insulating films 60A and 60B are formed by forming the overlap regions O1 and O2. In the power control semiconductor device having a structure in which a plurality of transistors having different process elements, such as the same, are integrated on one substrate, the threshold voltage characteristic required by each transistor can be easily secured while maintaining the breakdown voltage characteristic. In addition, it is possible to secure the threshold voltage characteristics required by each transistor through one ion implantation process without performing the ion implantation process for each transistor to form a threshold voltage control layer.

As described above, the method of manufacturing a semiconductor device according to the first embodiment of the present invention can take advantage of the operating characteristics mentioned in FIG. 2 and at the same time simplify the process steps of the semiconductor device. Can be reduced.

[Example 2]

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. For the convenience of description, the same reference numerals are used as in the first embodiment of the present invention.

As shown in FIG. 4A, impurities of the first conductivity type and the second conductivity type are ion implanted into each region of the substrate 51 having the first region and the second region, and the implanted impurities are implanted. A heat treatment process for activating is performed to form first deep wells 52A and 52B of the first conductivity type and second deep wells 53A and 53B of the second conductivity type.

Next, the active regions 54A and 54B having a structure in which the first deep wells 52A and 52B and the second deep wells 53A and 53B are bonded to the substrate 51 are defined, and partially overlap with the region where the gate is to be formed. The device isolation film 55 is formed as much as possible. In this case, the device isolation layer 55 may be formed by an STI process.

Next, the first impurity regions 57 and 58 of the first conductive type are formed in the first deep wells 52A and 52B by ion implanting impurities of the first conductive type and the second conductive type into the predetermined regions of the substrate 51. And second impurity regions 56A and 56B of the second conductivity type are formed in the second deep wells 53A and 53B. In this case, it is preferable that the impurity doping concentration of the first impurity regions 57 and 58 is larger than the impurity doping concentration of the first deep wells 52A and 52B.

Here, the first impurity regions 57 and 58 are formed by ion implanting impurities of the first conductivity type into the first deep wells 52A and 52B in each region, and the first impurity regions 57 and 58 are formed as channel regions ( C) may be formed so as to be spaced apart from the region to be formed at predetermined intervals S1 and S2 to secure all threshold voltage characteristics required by the semiconductor devices to be formed in the first and second regions.

For example, in the second embodiment of the present invention, the impurity doping concentrations of the active regions 54A and 54B of the first region and the second region are the same, and a threshold required by the semiconductor device to be formed in the first region and the second region is required. Although the voltages are the same, the first impurity region 57 and the channel region C formed in the first region are formed when the thickness of the gate insulation layer formed in the first region is thicker than the thickness of the gate insulation layer formed in the second region. By forming the gap S2 between the first impurity region 58 formed in the second region and the region where the channel region C is to be formed smaller than the interval S1 between the regions to be formed, the first region and All the threshold voltage characteristics required by the semiconductor device to be formed in the second region can be secured.

As shown in FIG. 4B, heat treatment is performed to activate impurities injected into the first impurity regions 57 and 58 and the second impurity regions 56A and 56B. At this time, the heat treatment is preferably performed at a lower temperature than the heat treatment process for forming the first deep well (52A, 52B) and the second deep well (53A, 53B). Hereinafter, the reference numerals of the first impurity regions 57 and 58 which have been heat-treated are changed to '57A' and '58A'.

Here, the overlapping regions O1 and O2 overlapping the regions where the first impurity regions 57A and 58A and the channel region C are to be formed by diffusion of impurities implanted into the first impurity regions 57A and 58A by the heat treatment process. ). At this time, since the first impurity regions 57A and 58A formed in each region are made of impurities having the same conductivity type, they have the same diffusion distance during the heat treatment process. Accordingly, the line widths (or areas) of the overlap regions O1 and O2 may be adjusted according to the intervals S1 and S2 in which the predetermined region of the channel region C and the first impurity regions 57A and 58A are spaced apart. It is possible to secure all the threshold voltage characteristics required by the semiconductor device to be formed in each region.

For example, in the second embodiment of the present invention, the impurity doping concentrations of the active regions 54A and 54B of the first region and the second region are the same, and a threshold required by the semiconductor device to be formed in the first region and the second region is required. Although the voltages are the same, the first impurity region 57 and the channel region C formed in the first region are formed when the thickness of the gate insulation layer formed in the first region is thicker than the thickness of the gate insulation layer formed in the second region. The spacing S1 between the first impurity region 58 formed in the second region and the region where the channel region C is to be formed is smaller than the spacing S1 between the regions to be formed. Since the diffusion distances of the first impurity regions 57A and 58A are the same, the line width (or area) of the overlap region O2 formed in the second region is larger than the line width (or area) of the overlap region O1 formed in the first region. By making the larger, the semiconductor device to be formed in the first region and the second region is required. It is possible to ensure all of the threshold voltage characteristics.

In addition, since the impurity doping concentrations of the first impurity regions 57A and 58A in the overlapping regions O1 and O2 have a gradient as the overlap regions O1 and O2 are formed through diffusion during heat treatment, the above-mentioned FIG. As described above, deterioration of the breakdown voltage characteristic can be prevented more effectively than the first embodiment of the present invention by forming the overlap regions O1 and O2.

In FIG. 4B, for convenience of description, the first impurity regions 57A and 58A are diffused only in the channel region C in the heat treatment process described above. That is, although not shown in the drawings, the first impurity regions 57A and 57B and the second impurity regions 56A and 56B may be diffused both in the horizontal and vertical directions during the above-described heat treatment process.

As shown in FIG. 4C, gate insulating films 59A and 59B are formed on the substrate 51, and the thickness T1 of the gate insulating film 59A formed on the substrate 51 of the first region is changed to the second thickness. It is formed larger than the thickness T2 of the gate insulating film 59B formed on the substrate 51 in the region (T1> T2).

Next, after the gate conductive film is deposited on the entire surface of the substrate 51, the gate conductive film and the gate insulating films 59A and 59B are sequentially etched to sequentially etch the first and second deep wells 52A and 52B and 53A into the respective regions. And 53B at the same time, a gate having a structure in which the gate insulating films 59A and 59B and the gate electrode 60 are sequentially stacked is formed.

As shown in FIG. 4D, the source regions 62A and 62B are ion-implanted with impurities of the second conductivity type in the first deep wells 52A and 52B in the substrate 51 so as to be aligned at one end of the gate electrode 60. ), And ion-implanted impurities of the second conductive type into the second impurity regions 56A and 56B in the substrate 51 so as to be spaced a predetermined distance from the other end of the gate electrode 60 to drain regions 63A and 63B. ).

Next, the first conductive type pickup regions 61A and 61B are formed by ion implanting impurities of the first conductive type into the first impurity regions 57A and 58A so as to be spaced apart from the source regions 62A and 62B at predetermined intervals. .

Next, a heat treatment process for activating impurities injected into the pickup regions 61A and 61B, the source regions 62A and 62B and the drain regions 63A and 63B is performed.

As described above, in the method of manufacturing the semiconductor device according to the second embodiment of the present invention, the dopant concentration in the active regions 54A and 54B and the thickness of the gate insulating films 60A and 60B are formed by forming the overlap regions O1 and O2. In the power control semiconductor device having a structure in which a plurality of transistors having different process elements, such as the same, are integrated on one substrate, the threshold voltage characteristic required by each transistor can be easily secured while maintaining the breakdown voltage characteristic. In addition, it is possible to secure the threshold voltage characteristics required by each transistor through a single ion implantation process without forming a threshold voltage control layer by performing an ion implantation process for each transistor.

As described above, the method of manufacturing a semiconductor device according to the second embodiment of the present invention can take advantage of the operating characteristics mentioned above with reference to FIG. 2 and can simplify the process steps of the semiconductor device. Can be reduced.

In addition, since the impurity doping concentrations of the first impurity regions 57A and 58A in the overlap regions O1 and O2 are formed to have a gradient, the breakdown voltage characteristic can be secured more effectively than the first embodiment of the present invention.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a semiconductor device for power control according to the prior art.

2A and 2B illustrate a semiconductor device to which the technical subject matter of the present invention is applied.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31, 51: substrate 32, 52A, 52B: first deep well

33, 53A, 53B: second deep well 34, 54A, 54B: active region

35 drain region 36, 56A, 56B: second impurity region

37, 62A, 62B: source area 38, 61A, 61B: pickup area

40, 59A, 59B: gate insulating film 41, 60: gate electrode

42, 55: device isolation layers 39, 57, 57A, 58, 58A: first impurity region

Claims (20)

Forming an active region having a structure in which a first deep well of a first conductive type and a second deep well of a second conductive type are bonded to a substrate; A first impurity region of a first conductivity type is formed in the first deep well of the substrate, and the first impurity region extends to the channel scheduled region of the substrate so that the first impurity region and the channel scheduled region overlap each other. Forming a; Forming a gate having a structure in which the first deep well and the second deep well are simultaneously crossed on the substrate, and a gate insulating film and a gate electrode are sequentially stacked; And Forming a source region and a drain region of a second conductivity type in the first deep well on the gate side and the second deep well on the other side of the gate, respectively; Semiconductor device manufacturing method comprising a. The method of claim 1, And the overlapping region is located within a range from the source region to an interface between the first deep well and the second deep well. The method of claim 1, And a line width (or area) of the overlap region is increased from the source region toward the drain region. The method of claim 1, The impurity doping concentration of the first impurity region is higher than the impurity doping concentration of the first deep well. The method of claim 1, And forming a pickup region of a first conductivity type in the first impurity region to be spaced apart from the source region by a predetermined distance. The method of claim 5, And the source region and the pickup region are formed in the first impurity region. The method of claim 1, Before forming the first impurity region Defining the active region on the substrate, and forming an isolation layer to partially overlap the region where the gate is to be formed. The method of claim 7, wherein The device isolation film is a semiconductor device manufacturing method formed through a shallow trench isolation (STI) process. The method of claim 1, Before forming the gate And forming a second impurity region of a second conductivity type surrounding the drain region in the second deep well. Forming an active region having a structure in which a first deep well of a first conductive type and a second deep well of a second conductive type are bonded to a substrate; Forming a first impurity region of a first conductivity type in the first deep well so as to be spaced apart from the channel expected region of the substrate by a predetermined distance; Extending the first impurity region to a channel scheduled region of the substrate through heat treatment to form an overlapping region in which the first impurity region and the channel scheduled region overlap each other; Forming a gate having a structure in which the first deep well and the second deep well are simultaneously crossed on the substrate, and a gate insulating film and a gate electrode are sequentially stacked; And Forming a source region and a drain region of a second conductivity type in the first deep well on the gate side and the second deep well on the other side of the gate, respectively; Semiconductor device manufacturing method comprising a. The method of claim 10, And the overlapping region is located within a range from the source region to an interface between the first deep well and the second deep well. The method of claim 10, And a line width (or area) of the overlap region is increased in the drain direction from the source region. The method of claim 10, The impurity doping concentration of the first impurity region in the overlap region has a gradient. The method of claim 13, The impurity doping concentration of the first impurity region in the overlapping region decreases from the source region toward the drain region. The method of claim 10, The impurity doping concentration of the first impurity region is higher than the impurity doping concentration of the first deep well. The method of claim 10, And forming a pickup region of a first conductivity type in the first impurity region to be spaced apart from the source region by a predetermined distance. The method of claim 16, And the source region and the pickup region are formed in the first impurity region. The method of claim 10, Before forming the first impurity region Defining the active region on the substrate, and forming an isolation layer to partially overlap the region where the gate is to be formed. The method of claim 18, The device isolation film is formed by an STI process. The method of claim 10, Before forming the gate And forming a second impurity region of a second conductivity type surrounding the drain region in the second deep well.

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