KR101097168B1 - Method for forming semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a semiconductor device, and the present invention relates to a problem in that a process of forming an alignment key mask (Align Key Mask) is complicated and has a high defect rate in forming a MIM capacitor on the first metal wiring. In order to solve the problem of damage to the lower metal wiring in the etching of the MIM capacitor, after forming the first metal wiring, a barrier insulating film is formed and the upper electrode layer is formed to be thin enough to be transparent, thereby forming the MIM capacitor of the semiconductor device. It is a method of forming a semiconductor device that can simplify the process and improve the characteristics of the semiconductor device.

Description

Method of forming a semiconductor device {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view of a MIM capacitor used for Al metal wiring according to the prior art.

2 is a cross-sectional view of a MIM capacitor used for Cu metal wiring according to the prior art.

3A to 3G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, wherein in forming an MIM capacitor on an upper portion of a first metal wire, an alignment key mask process step is complicated and a defect rate is high, resulting in a low yield and a MIM capacitor. In order to solve the problem of damage to the lower metal interconnection in the etching step, the present invention relates to a method of forming a semiconductor device, after forming the first metal interconnection to form a barrier insulating film and to form the upper electrode layer thin enough to be transparent.

Among the semiconductor devices, capacitors used in highly integrated semiconductor devices include polysilicon to polysilicon, polysilicon to silicon, metal to silicon, and metal to metal silicon. Various capacitor structures of to Polysilicon and metal to metal have been used. Among these capacitor structures, metal to metal or metal to dielectric / metal insulator metal (MIM) structures have a low series resistance, which makes a capacitor having high storage capacity and thermal stability. And because of the low VCC advantage is widely used as the structure of the current capacitor.

The MIM capacitor is generally located between the metal wires. However, the MIM capacitor has a problem in that the formation process step is very complicated, resulting in a high defect rate and a low yield of semiconductor devices.

1 is a cross-sectional view of a MIM capacitor used in the Al metal wiring according to the prior art.

Referring to FIG. 1, a metal barrier layer 20 is formed on an Al first metal wire 10, and then a MIM capacitor is formed on the first metal wire 10. At this time, since deep vias are already formed in the Al metal wiring structure, an alignment key mask process is not additionally required. However, as the line width of the metal wiring decreases, there is a change from Al metal wiring to Cu metal wiring due to the problem of embedding the metal layer or increasing the resistance.

2 is a cross-sectional view of a MIM capacitor used for Cu metal wiring according to the prior art.

Referring to FIG. 2, the lower electrode layer 30 and the dielectric layer (not shown) are formed on the first metal wiring 10 and the interlayer dielectric (ILD) insulating layer 15 formed by using a damascene process. 40 and the upper electrode layer 50 are sequentially deposited. In this case, the upper and lower electrode layers 30 and 50 are deposited by PVD, and the dielectric layer 40 is deposited by CVD. The upper electrode layer 50 and the lower electrode layer 20 may use TaN or TiN, and the dielectric layer As the 40, the use of nitride, oxide, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₅ ) is used. desirable.

Next, the etch stop film 60 is formed on the MIM capacitor, and then the IMD insulating film 70 is formed.

Next, a damascene pattern is formed on the IMD insulating film 70 and the second metal wiring 90 is formed.

At this time, when the first metal wiring 20 is exposed, in the etching process of patterning the MIM capacitor or the wet cleaning of the semiconductor substrate in each subsequent process step, the first metal wiring is seriously oxidized to short-circuit or disconnection. Fatal problems such as these can occur. Therefore, there exists a problem that the reliability of a semiconductor element falls.

In addition, when the MIM capacitor is formed using an opaque material such as TaN as the lower electrode layer, the overlay key or the align key may not be visible when the MIM capacitor is formed later. Therefore, in order to form the deep alignment key and the overlay key before depositing the lower electrode layer, the key etching process must be performed simultaneously with the etching process of the oxide film 35.                         

As described above, during the MIM capacitor formation process, a process step of forming an overlay key and an alignment key is further required, and the production process step becomes complicated. Therefore, not only the possibility of defects increases, but also in the region in which the MIM capacitor is formed, there is a problem in that a step occurs very severely compared to other regions, thereby reducing the process margin in the subsequent second metal wiring forming step.

The present invention is to solve the above problems, and after forming the first metal wiring to form a barrier insulating film and the upper electrode layer to be thin enough to be transparent, to simplify the process of forming the MIM capacitor of the semiconductor device and characteristics of the semiconductor device It is an object of the present invention to provide a method for forming a semiconductor device capable of improving the efficiency of the semiconductor device.

The present invention is to achieve the above object,

Forming a barrier insulating film on the ILD insulating film provided with the first metal wiring;

Etching a predetermined portion of the barrier insulating film to expose a predetermined region of the MIM capacitor;

Depositing a metal barrier layer filling the exposed region to a height of the barrier insulating layer to form a lower electrode layer; and

And forming a dielectric layer and a transparent upper electrode layer over the metal barrier layer.                     

Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, the barrier insulating layer 120 is formed on the ILD insulating layer 100 provided with the first metal wire 110. In this case, the barrier insulating film 120 is preferably formed to have a thickness of 100 ~ 1000 하여 using silicon carbide (SiC) or silicon nitride (SiN), the barrier insulating film 120 is formed by the first metal wiring 110 It serves to prevent damage by the etching process for subsequent MIM capacitor formation.

Referring to FIG. 3B, a predetermined portion of the barrier insulating layer 120 is etched to expose a region of the MIM capacitor predetermined region. In this case, it is preferable to expose the narrow region so that the subsequent MIM capacitor lower electrode region is included in the region of the first metal wiring 110.

Referring to FIG. 3C, the metal barrier layer 125 filling the exposed region is formed to the height of the barrier insulating layer 120. In this case, the metal barrier layer 125 may be a tungsten layer or a tungsten nitride layer formed using a CVD method, or may be any one selected from CoWP, CoMoP, CoWB, and CoNiP layers formed using an electroless plating method. In this case, the metal barrier layer 125 is preferably formed to a thickness of 100 ~ 1000Å, serves as a lower electrode layer of the MIM capacitor connected to the first metal wiring 110.

Referring to FIG. 3D, the dielectric layer 130 forming the MIM capacitor and the transparent upper electrode layer 140 are formed on the metal barrier layer 125 and the barrier insulating layer 120. In this case, the dielectric layer 130 is formed to have a thickness of 100 ~ 1000Å using any one selected from silicon nitride film (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ) and tantalum oxide (Ta ₂ O ₅ ). desirable.
In addition, the upper electrode layer 140 may be a tantalum layer or tantalum nitride formed by PVD, CVD or ALD method, or may be a tungsten layer or tungsten nitride layer formed by CVD method, and may be electroless plating. It may be any one selected from the CoWP, CoMoP, CoWB and CoNiP layer formed by using. At this time, the upper electrode layer 140 is preferably formed to a thickness of 10 ~ 50Å. By forming the upper electrode layer 140 in this manner, the alignment key forming process for the subsequent MIM capacitor patterning process can be omitted.

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Next, in consideration of the subsequent second metal wiring forming process, it is more preferable to further form the etch stop layer 150 on the upper electrode layer 140 and then proceed with the MIM capacitor patterning process.

Referring to FIG. 3E, the etch stop layer 150, the upper electrode layer 140, the dielectric layer 130, and the metal barrier layer 125 are sequentially etched using a MIM capacitor mask to form a MIM capacitor.

Referring to FIG. 3F, the IMD insulating layer 170 is formed on the barrier insulating layer 120, and the damascene pattern for metal wiring is formed by etching the IMD insulating layer 170. In this case, the IMD insulating film 170 is preferably formed using SiO ₂ or OSG (organosilica glass), and after the damascene pattern for metal wiring is formed, a cleaning process using an H ₂ plasma method is performed.

Referring to FIG. 3G, the diffusion barrier layer 180 and the metal seed layer (not shown) are formed on the damascene pattern to form the second metal wire 190. At this time, the diffusion barrier 180 is formed to a thickness of 10 ~ 300Å, the metal seed layer is formed to a thickness of 50 ~ 1500Å by using PVD or CVD method, the process of embedding the second metal wiring 190 is electroless It is preferable to carry out by using the plating method, the electrolytic plating method, the PVD or the CVD method.

As described above, the present invention simplifies the process of forming a MIM capacitor of a semiconductor device by using a metal barrier layer as a lower electrode layer and forming an upper electrode layer so as to be transparent after forming the first metal wiring, and thus yields a semiconductor device. And it provides an effect that can improve the characteristics.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (15)

Forming a barrier insulating film on the ILD insulating film provided with the first metal wiring; Etching a predetermined portion of the barrier insulating film to expose a region of the MIM capacitor; Depositing a metal barrier layer filling the exposed region to a height of the barrier insulating layer to form a lower electrode layer; And Forming a dielectric layer and a transparent upper electrode layer over the metal barrier layer. The method of claim 1, The barrier insulating film is formed using a silicon carbide (SiC) or silicon nitride (SiN) to a thickness of 100 ~ 1000Å, the method of forming a semiconductor device. The method of claim 1, The metal barrier layer is a tungsten layer or tungsten nitride layer formed by the CVD method. The method of claim 1, The dielectric layer is formed of a silicon nitride film (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ) and tantalum oxide (Ta ₂ O ₅ ), using a semiconductor, characterized in that formed in a thickness of 100 ~ 1000Å Formation method of the device. The method of claim 1, And the upper electrode layer is a tantalum layer or tantalum nitride formed by PVD, CVD or ALD. The method of claim 1, Forming an etch stop layer on the MIM capacitor; Forming an IMD insulating film on the barrier insulating film; Etching the IMD insulating layer pattern to form a damascene pattern for metal wiring; And And forming a diffusion barrier layer and a metal seed layer on the damascene pattern, and then forming a second metal wiring. The method of claim 6, The IMD insulating film is a method of forming a semiconductor device, characterized in that formed using SiO ₂ or OSG. The method of claim 6, And forming a damascene pattern for the metal wiring, and then performing a cleaning process using an H ₂ plasma method. The method of claim 6, The diffusion barrier film is a method of forming a semiconductor device, characterized in that formed in a thickness of 10 ~ 300Å. The method of claim 6, The metal seed layer is formed to a thickness of 50 ~ 1500Å by using a PVD or CVD method, and the process of embedding the second metal wiring is performed using an electroless plating method, an electrolytic plating method, PVD or CVD method. A method of forming a semiconductor device. The method of claim 1, The metal barrier layer is a method of forming a semiconductor device, characterized in that any one selected from CoWP, CoMoP, CoWB and CoNiP layer formed by an electroless plating method. The method of claim 1, And the upper electrode layer is a tungsten layer or tungsten nitride layer formed by a CVD method. The method of claim 1, wherein the upper electrode layer is any one selected from CoWP, CoMoP, CoWB, and CoNiP layers formed by an electroless plating method. 12. The method of claim 3 or 11, wherein the metal barrier layer is formed to a thickness of 100 to 1000 GPa. The method of forming a semiconductor device according to any one of claims 5, 12, and 13, wherein the upper electrode layer is formed to a thickness of 10 to 50 microseconds.

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