KR101094943B1 - Address Generating Circuit for Test Mode of Semiconductor Memory Apparatus - Google Patents

Abstract

Output of an external address signal in response to a normal mode mode signal, an auto refresh signal, and a test mode signal in response to a first mode determination unit for determining an operation mode of the semiconductor memory device, an output signal of the first mode determination unit, and an external address signal A second mode determination unit determining an operation mode of the semiconductor memory device in response to a first address generator determining whether or not, an auto refresh signal and a test mode signal, an output signal and an internal address signal of the second mode determination unit An address generation circuit including a second address generation unit for determining whether to output an address signal and an output unit for outputting one of the output signals of the first address generation unit and the second address generation unit as an address selection signal is provided.

Auto refresh, test

Description

Address Generating Circuit for Test Mode of Semiconductor Memory Apparatus

The present invention relates to a semiconductor device, and more particularly, to an address generating circuit for a test mode of a semiconductor memory device.

The semiconductor memory device performs an auto refresh operation at regular intervals to maintain data stored in the memory cell. The auto refresh period (refresh to active / refresh time; tRFC) is specified in a standard specification of a semiconductor memory device, and is a time required until a valid command can be input after an auto refresh operation.

During the auto refresh operation, the semiconductor memory device operates by dividing the active section (tRAS) and the precharge section (tRP), and tRAS means the time required for activating the bit line sense amplifier and transitioning to a stable state. The time taken to deactivate the sense amplifier and transition to the standby state as in the initial stage.

To ensure that the semiconductor memory device operates with the appropriate tRFC, tests should be performed prior to product release. In such a test mode, another auto refresh command or an active command is applied after the auto refresh command to determine whether the semiconductor memory device is malfunctioning to determine an appropriate auto refresh period. That is, if another command is input while the refresh is being performed by the auto refresh command, the newly input command will be ignored. If another command is input after the refresh operation is completed, the operation according to the newly input command will be performed. Accordingly, it is possible to check whether the specified auto refresh period is satisfied by varying the time to input another auto refresh command or an active command during the auto refresh operation period.

However, if another command is applied during the tRAS section of the auto refresh operation section, the corresponding command is ignored. However, if another command is applied in the tRP section, the corresponding command may not be ignored. In order to measure the correct auto refresh interval (tRFC), it is necessary to measure tRAS plus tRP. However, the above-mentioned problem situation prevents accurate measurement of tRP.

As a method for accurately measuring the precharge period in a semiconductor memory device, there is a method of confirming whether the sense amplifier accurately senses data of the word lines by continuously precharging adjacent word lines having data of opposite phases. For example, WL1 is selected while pre-charging by enabling WL0 connected to the memory cell having the data of the first logic level. The memory cell connected to WL1 stores data of a second logic level in phase opposite to the memory cell connected to WL0. In this case, when WL0 is not fully precharged, that is, when tRP is not satisfied, the sense amplifier does not transition to the initial state. If WL1 is precharged in this state, the sense amplifier does not sense the correct value.

However, in the auto refresh mode, since the word lines are enabled in any order to reduce the current, the above precharge interval measuring method cannot be applied.

1 is a diagram for describing an address generation circuit in a general test mode.

As shown in the drawing, a general address generation circuit includes a first address generator 10 that outputs a first address signal in response to an external address ADD_EX in a normal active mode ACT_NM, and an internal address in an auto refresh mode RFS. The address selection signal ADD includes one of a second address generator 12 that outputs a second address signal in response to (ADD_IN), and one of output signals of the first address generator 10 and the second address generator 12. It includes an output unit 14 for outputting.

In FIG. 1, the second address generator 12 does not operate in the normal active mode ACT_NM, and the output unit outputs the external address ADD_EX as the address selection signal ADD. In contrast, in the auto refresh mode RFS, the first address generator 10 does not operate, and the output unit 14 outputs the internal address ADD_IN as the address selection signal ADD.

That is, in the auto refresh mode (RFS), since the word line is enabled by the internal address ADD_IN generated by the internal address counter, an accurate precharge period cannot be measured, and as a result, a mass produced semiconductor memory device is required. It is difficult to check whether the tRFC is satisfied.

SUMMARY OF THE INVENTION The present invention has a technical problem to provide an address generation circuit for a test mode of a semiconductor memory device capable of accurately measuring the auto refresh interval.

Another object of the present invention is to provide an address generation circuit for a test mode of a semiconductor memory device capable of sequentially enabling a word line in an auto refresh test mode of a semiconductor memory device.

The address generation circuit according to an embodiment of the present invention for achieving the above-described technical problem is a first mode determination unit for determining an operation mode of a semiconductor memory device in response to a normal active mode signal, an auto refresh mode signal and a test mode signal. ; A first address generator determining whether to output the external address signal in response to an output signal and an external address signal of the first mode discriminator; A second mode determiner configured to determine an operation mode of the semiconductor memory device in response to the auto refresh mode signal and the test mode signal; A second address generator determining whether to output the internal address signal in response to an output signal and an internal address signal of the second mode discriminator; And an output unit configured to output one of an output signal of the first address generator and the second address generator as an address selection signal.

According to the present invention, in the auto refresh test mode, the word lines are sequentially enabled to measure the precharge period. Therefore, the auto refresh section including the active section and the precharge section can be accurately determined.

As a result, it is possible to improve the operational reliability of the semiconductor memory device, and to provide a semiconductor memory device suitable for the auto refresh period defined in the standard.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2 is a block diagram of an address generation circuit for a test mode of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 2, the address generation circuit 100 according to an exemplary embodiment of the present invention may respond to the semiconductor memory in response to the normal active mode signal ACT_NM, the auto refresh mode signal RFS, and the test mode signal TM. A first mode determining unit 110 that determines a mode of the device, an output signal of the first mode determining unit 110, and an external address signal ADD_EX, in response to determining whether to output the external address signal ADD_EX. The second mode determiner 130 and the second mode determiner 130 that determine the mode of the semiconductor memory device in response to the first address generator 120, the auto refresh mode signal RFS, and the test mode signal TM. The second address generator 140 and the first address generator 120 and the second address generator 140 that determine whether to output the internal address signal ADD_IN in response to the output signal and the internal address signal ADD_IN. One of the output signals And an output unit 150 outputting the dress selection signal ADD.

More specifically, the first mode determination unit 110 is in the test mode of the auto refresh operation, that is, the auto refresh mode signal RFS and the test mode signal TM are enabled and the normal active mode signal ACT_NM is displayed. When enabled, the first address generator 120 is driven. Also, in the normal active mode, that is, when the normal active mode signal ACT_NM is enabled and the auto refresh mode signal RFS and the test mode signal TM are disabled, the first address generator 120 To be driven. Accordingly, the first address generator 120 outputs the external address ADD_EX.

The second mode determiner 130 deactivates the second address generator 140 when the test mode of the auto refresh operation, that is, when the auto refresh mode signal RFS and the test mode signal TM are enabled, outputs the deactivated second address generator 140. The external address ADD_EX is output from the unit 150 as the address selection signal ADD.

That is, the address generation circuit shown in Fig. 2 outputs the external address ADD_EX as the address selection signal ADD in the test mode of the auto refresh operation. In addition, the external address ADD_EX is output as the address selection signal ADD even in the normal active mode.

In the auto refresh mode, since the test mode signal TM and the normal active mode signal ACT_NM are disabled, the first address generator 120 is inactivated and the internal address output from the second address generator 140 is disabled. (ADD_IN) is output as the address selection signal ADD.

As a result, in the test mode for measuring the auto refresh operation section, the word lines may be sequentially enabled by the external address ADD_EX, and thus, the precharge section included in the refresh section may be accurately measured.

3 is an example of the address generation circuit diagram shown in FIG. 2.

First, the first mode determination unit 110 determines whether the first mode determination unit 112 determines whether the test mode is the auto refresh operation, and a signal for driving the first address generation unit in the normal active mode or the test mode of the auto refresh operation. It includes a second determination unit 114 for outputting.

The first determination unit 112 may be configured as logic elements ND11 and IV11 that receive the auto refresh mode signal RF and the test mode signal TM and output a high level signal when the input signals are both high level. Can be. In addition, the second determination unit 114 receives the output signal of the first determination unit 112 and the normal active mode signal ACT_NM and outputs a high level signal as the first output signal when the input signal is both low level. The logic device NR11 and the logic device IV12 for inverting the output signal of the logic device NR11 and outputting the second output signal may be included. That is, the logic device IV12 outputs a high level signal if any one of the input signals of the second discriminator 114 is at a high level.

Meanwhile, the first address generator 120 includes first to fourth switching elements connected in series between the power supply voltage terminal VDD and the ground terminal VSS. In the first switching device P11, a source terminal is connected to a power supply voltage terminal and an external address ADD_EX is input to the gate terminal. In the second switching device P12, a source terminal is connected to the drain terminal of the first switching element P11, a drain terminal is connected to the output terminal of the first address generator 120, and a second determination unit ( The first output signal of 114, that is, the output signal of logic element NR11, is input.

In the third switching device N11, a drain terminal is connected to an output terminal of the first address generator 120, and a second output signal of the second determination unit 114, that is, an output signal of the logic device IV12 is connected to the gate terminal. Is entered. In addition, the fourth switching element N12 has a drain terminal connected to a source terminal of the third switching element N11, a source terminal connected to a ground terminal VSS, and an external address signal ADD_EX input to the gate terminal. .

When the output signal of the logic device NR11 is at a low level, that is, the first address generator 120 may enter the test mode or the normal active mode of the auto refresh mode by the first mode determination unit 110. In operation, the external address signal ADD_EX is output to the output terminal. On the other hand, when the output signal of the logic element NR11 is at a high level, that is, when the semiconductor memory device is not in either the test mode or the normal active mode of the auto refresh mode, for example, the semiconductor memory device is in the auto refresh mode. In the case of operation in which the external address signal ADD_EX is not output.

Next, the second mode determiner 130 outputs the first output signal having a low level when the input signal is both high level using the inverted signal of the test mode signal TM and the auto refresh mode signal RFS as input signals. And a logic element IV14 for inverting an output signal of the logic element ND12 and the logic element ND12 and outputting the second signal as a second output signal. That is, the logic device IV14 outputs a high level signal when both the inverted signal of the test mode signal TM and the auto refresh mode signal RFS are at the high level.

Meanwhile, the second address generator 140 includes fifth to eighth switching elements connected in series between the power supply voltage terminal VDD and the ground terminal VSS. The fifth switching element P13 has a source terminal connected to a power supply voltage terminal and receives an internal address ADD_IN through a gate terminal. The sixth switching device P14 has a source terminal connected to the drain terminal of the fifth switching element P13, a drain terminal connected to the output terminal of the second address generator 140, and a second mode determination unit ( The first output signal of 130, that is, the output signal of logic element ND12, is input.

In the seventh switching device N13, a drain terminal is connected to an output terminal of the second address generator 140, and a second output signal of the second mode determination unit 130, that is, an output signal of the logic element IV14, is connected to the gate terminal. Is input. In addition, the eighth switching element N14 has a drain terminal connected to a source terminal of the seventh switching element N13, a source terminal connected to a ground terminal VSS, and an internal address signal ADD_IN being input to the gate terminal. .

The second address generator 140 may generate an internal address signal only when the output signal of the logic device ND12 is at a low level, that is, when the semiconductor memory device operates in the auto refresh mode by the second mode determination unit 130. (ADD_IN) is output and the internal address signal ADD_IN is not output when the test mode of the auto refresh mode, that is, when the output signal of the logic element ND12 is at a high level.

The output unit 150 may be configured as a latch circuit commonly connected to the output terminals of the first address generator 120 and the second address generator 140, and the first and second mode determination units 110,. An address signal determined according to the output signal of 130 is output as the address selection signal ADD.

Reference numerals IV13, IV15 and IV16 denote logic elements for inverting the input signal.

By such an address generation circuit, the precharge period can be measured by sequentially enabling the word lines in accordance with the external address in the test mode of the auto refresh operation.

The auto refresh section (tRFC) consists of an active section (tRAS) and a precharge section (tRP). When a new command is input in the pre-autonomous section (tRP), the auto precharge section is accurately measured because the new command is processed. I could not. In the present invention, the precharge period can be measured by checking whether the precharge is performed while the word line is sequentially enabled in the precharge period in the auto precharge mode, and as a result, it is possible to confirm whether the auto refresh period satisfies the specification.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a diagram for explaining an address generation circuit in a general test mode;

2 is a block diagram of an address generation circuit for a test mode of a semiconductor memory device according to an embodiment of the present invention;

3 is an example of the address generation circuit diagram shown in FIG. 2.

Description of the Related Art [0002]

100: address generation circuit 110: first mode discrimination unit

120: first address generator 130: second mode determination unit

140: second address generator 150: output unit

Claims (11)

A first mode determination unit configured to determine whether an operation mode of the semiconductor memory device is a test mode of an auto refresh operation or a normal active mode in response to a normal active mode signal, an auto refresh mode signal, and a test mode signal; A first address generator determining whether to output the external address signal in response to an output signal and an external address signal of the first mode discriminator; A second mode determination unit configured to determine whether an operation mode of the semiconductor memory device is an auto refresh mode or a test mode of an auto refresh operation in response to the auto refresh mode signal and the test mode signal; A second address generator determining whether to output the internal address signal in response to an output signal and an internal address signal of the second mode discriminator; And When the external address signal is output from the first address generator, the external address is output as an address selection signal, and when the internal address signal is output from the second address generator, the internal address is an address selection signal. An output unit for outputting to a; Address generation circuit for the test mode of the semiconductor memory device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The first mode determination unit may drive the first address generator to output the external address from the first address generator when the operation mode of the semiconductor memory device is a test mode of the auto refresh operation. An address generation circuit for a test mode of a semiconductor memory device. Claim 3 was abandoned when the setup registration fee was paid. And the first mode discriminator is configured to output the external address from the first address generator when the operation mode of the semiconductor memory device is a normal active mode. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, And the second mode determination unit deactivates the second address generator when the operation mode of the semiconductor memory device is the test mode of the auto refresh operation. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The second mode determination unit generates the address for the test mode of the semiconductor memory device, wherein the internal address is output from the second address generator when the operation mode of the semiconductor memory device is the auto refresh mode. Circuit. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The first mode determination unit may include: a first determination unit configured to determine whether an operation mode of the semiconductor memory device is a test mode of the auto refresh operation; And Address generation circuit for the test mode of the semiconductor memory device comprising a. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The first determination unit may include a first logic element configured to receive the auto refresh mode signal and the test mode signal and output a high level signal when the input signal is at a high level. Address generation circuitry. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The second determination unit may include: a second logic element configured to receive an output signal of the first determination unit and the normal active mode signal and output a high level signal as a first output signal when the input signal is both low level; And A third logic element inverting the output signal of the second logic element and outputting the second output signal as a second output signal; Address generation circuit for the test mode of the semiconductor memory device comprising a. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, The first address generator may include: a first switching device to which a source terminal of a first switching device is connected to a power supply voltage terminal, and the external address signal is applied to a gate terminal of the first switching device; The source terminal of the second switching device is connected to the drain terminal of the first switching device, the drain terminal of the second switching device is connected to the output terminal of the first address generator, and the gate terminal of the second switching device is the The second switching element to which an output signal of the second logic element is applied; A third switching element having a drain end of a third switching element connected to an output end of the first address generator, and an output signal of the third logic element applied to a gate end of the third switching element; And A drain terminal of the fourth switching device is connected to the source terminal of the third switching device, a source terminal of the fourth switching device is connected to the ground terminal, and the external address signal is applied to the gate terminal of the fourth switching device. The fourth switching element; Address generation circuit for the test mode of the semiconductor memory device comprising a. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The second mode determination unit may include: a fourth logic element configured to output a first output signal having a low level when the input signal is a high level by using the inverted signal of the test mode signal and the auto refresh mode signal as input signals; And A fifth logic element inverting the output signal of the fourth logic element and outputting the second output signal as a second output signal; Address generation circuit for the test mode of the semiconductor memory device comprising a. Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, The second address generator may include: a fifth switching device to which a source terminal of a fifth switching device is connected to a power voltage terminal, and an internal address signal is applied to a gate terminal of the fifth switching device; A source terminal of the sixth switching device is connected to a drain terminal of the fifth switching device, and a drain terminal of the sixth switching device is connected to an output terminal of the second address generator, and the gate terminal of the sixth switching device is the first terminal. The sixth switching element to which an output signal of a fourth logic element is applied; The seventh switching device to which a drain terminal of a seventh switching device is connected to an output terminal of the second address generator, and an output signal of the fifth logic device is applied to a gate terminal of the seventh switching device; And The drain terminal of the eighth switching device is connected to the source terminal of the seventh switching device, the source terminal of the eighth switching device is connected to the ground terminal, and the internal address signal is applied to the gate terminal of the eighth switching device. The eighth switching device; Address generation circuit for the test mode of the semiconductor memory device comprising a.

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