KR101087391B1 - Method for manufacturing cmos image sensor - Google Patents

Abstract

The present invention fundamentally prevents inter-pixel interference due to dopant implantation in the active region without a separate tuning process in the isolation ion implantation process for securing the thickness of the initial pad nitride film to form the channel stop region, and before the CMP process. In order to provide a method for manufacturing a CMOS image sensor that can ensure uniformity without performing a photo process and an etching process to be performed further, the present invention comprises the steps of depositing a pad oxide film and a pad nitride film on a substrate; Forming a trench by etching the pad nitride film, the pad oxide film, and the substrate, forming a channel stop region at an inner wall portion and a bottom surface of the trench, and forming an insulating layer for an isolation layer so that the trench is buried. Depositing a film having a high selectivity between the insulating film for device isolation and the pad nitride film; Selectively polishing the insulating film for device isolation by performing a planarization process using a thin film, and planarizing the pad nitride film and the insulation film for the device isolation film by performing an entire surface etching process, and removing the pad nitride film to remove the device isolation film. It provides a method of manufacturing a CMOS image sensor comprising the step of forming a.

CMOS image sensor, channel stop region, HDP oxide, isolation ion implantation, etch back

Description

Manufacturing Method of CMOS Image Sensor {METHOD FOR MANUFACTURING CMOS IMAGE SENSOR}

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

2 is a cross-sectional view illustrating a photodiode and a transfer transistor among unit pixels of a general CMOS image sensor.

3A to 3G are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to the prior art.

4A to 4F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 110: substrate 11, 111: pad oxide film

12, 112: pad nitride film 12a: pad nitride film pattern

13: photoresist pattern 16, 113: trench

18, 116: channel stop region 19, 117: HDP oxide film

19a and 117a: device isolation layer 114: month oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of fabricating an isolation layer of a complementary metal-oxide-semiconductor (CMOS) image sensor.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used. The image sensor is arranged on the upper part of the light sensing unit for generating and accumulating photocharges from the outside to implement a color image. Such color filter arrays (CFAs) are red (R), green (G) and blue (B), or yellow, magenta, and cyan. It consists of a branch collar. Typically, three colors of red (R), green (G), and blue (B) are frequently used in the color filter array of the CMOS image sensor.

Such an image sensor is a semiconductor device that converts an optical image into an electrical signal. As described above, a CCD and a CMOS image sensor have been developed and widely commercialized. A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other. CMOS image sensors, on the other hand, use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make MOS transistors as many as the number of pixels. It is a device employing the method.

However, CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask processes, complicated process, and difficult to implement one chip because signal processing circuit cannot be implemented in CCD chip. Recently, researches on the development of CMOS image sensors using sub-micron CMOS manufacturing techniques have been enthusiastically conducted to overcome the disadvantages of the CCD.

The CMOS image sensor forms an image by forming a photo diode and a MOS transistor in a unit pixel and sequentially detects a signal in a switching method. Since the CMOS manufacturing technology is used, the power consumption is low and the number of masks is approximately. The process is very simple compared to CCD process that requires 30 to 40 masks, and it is possible to make various signal processing circuits and one chip.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor. Here, as an example, a unit pixel of a CMOS image sensor having a 4-T (transistor) structure is illustrated.

As shown in FIG. 1, a CMOS image sensor includes one photo diode (PD) and four MOS transistors. The four MOS transistors include a transfer transistor Tx, a reset transistor Rx, a drive transistor MD, and a selector transistor Sx. A load transistor is formed outside the unit pixel to read an output signal. Unexplained reference 'Cfd' indicates the capacitance of the floating diffusion.

A cross-sectional view of the unit pixel of such a CMOS image sensor is shown in FIG. In FIG. 2, only the photodiode and the transfer transistor Tx are shown for convenience of description.

As shown in FIG. 2, the CMOS image sensor includes an isolation layer 19a, a gate electrode 22, an n ⁻ doped region 23 and a p ⁰ doped region 25 constituting a photodiode. In addition, an n-type channel stop region 18 is formed under the device isolation layer 19a by performing an isolation ion implantation process to prevent cross talk between unit pixels.

Hereinafter, a method of forming the device isolation layer 19a including the n-channel stop region 18 of the CMOS image sensor according to the related art will be described with reference to FIGS. 3A to 3G.

First, as shown in FIG. 3A, the pad oxide film 11 and the pad nitride film 12 are sequentially formed on the semiconductor substrate 10.

Subsequently, as illustrated in FIG. 3B, after forming the photoresist pattern 13 by performing a photo process, the pad nitride layer exposed by performing the etching process 14 using the photoresist pattern 13 as an etching mask ( Etch 12). As a result, the pad nitride film pattern 12a is formed.

3C, after removing the photoresist pattern 13 through a strip process, an etching process 15 using the pad nitride layer pattern 112a as a hard mask is performed to bring the substrate 10 to a target depth. Etch it. As a result, a trench 16 is formed.

Next, as shown in FIG. 3D, the isolation ion implantation process 17 for the n-channel stop region is performed to form the n-channel stop region 18 on the substrate 10 on the inner side of the trench 16.

Subsequently, as shown in FIG. 3E, a high density plasma (HDP) oxide film 19 is deposited so that the trench 16 is buried.

Subsequently, a photo process and an etching process are performed to selectively etch portions having a relatively high level after deposition of the HDP oxide layer 19 to form an HDP oxide layer 19 having a relatively uniform level.

As such, the reason for performing the photo process and the etching process is that a step occurs between the cell array region and / or a logic region where a logic element for driving the cell is formed after the HDP oxide film 19 is deposited. This is because it is difficult to ensure uniformity when the subsequent CMP (Chemical Mechanical Polishing) process is performed in the present state.

Next, as shown in FIG. 3F, the CMP process 20 is performed to planarize the HDP oxide film 19. As a result, the HDP oxide film 19 is planarized and isolated inside the trench 16.

Subsequently, as illustrated in FIG. 3G, the etching process 21 using the etching selectivity between the oxide film and the nitride film is performed to selectively remove the pad nitride film pattern 12a. As a result, the device isolation film 19a is formed.

As described above, the isolation ion implantation process for forming the n-channel stop region 18 in the conventional CMOS image sensor manufacturing method is performed using the pad nitride film pattern 12a as an ion implantation mask. As a result, the dopant is not implanted into the active region in the isolation ion implantation process, and is implanted only into the inner wall and the bottom of the trench 16 to prevent the leakage current flow between the pixels.

For example, in the isolation ion implantation process, when the thickness of the pad nitride layer pattern 12a is low, dopants may be implanted in the active region, thereby causing channeling to affect device operation characteristics. That is, when the thickness of the pad nitride layer pattern 12a remaining after the formation of the trench 16 is low, the ion implantation energy should be tuned and lowered during the isolation ion implantation process, which may cause cross-talk problems. Can be. Therefore, it is necessary to control the thickness of the pad nitride film pattern 12a to a predetermined thickness or more.

On the other hand, when the thickness of the pad nitride layer pattern 12a remaining after the CMP process 20 is thick as shown in FIG. 3F, the device isolation layer 19a is thickly profiled in FIG. 3G, thereby floating gate of the subsequent gate electrode. The polysilicon film and the nitride film are not removed from the device isolation layer 19a by the step during the etching process to define the shape and the etching process to form the lightly doped drain (LDD) spacer on both sidewalls of the gate electrode. The problem of deterioration may occur. Therefore, it is necessary to control the thickness of the pad nitride film pattern 12a remaining after the CMP process 20 to be low.

Accordingly, the present invention has been made to solve the above problems of the prior art, has the following object.

First, the present invention can fundamentally prevent the inter-pixel interference due to the dopant implantation of the active region without a separate tuning process in the isolation ion implantation process to secure the thickness of the initial pad nitride film to form the channel stop region. It is an object of the present invention to provide a method for manufacturing a CMOS image sensor.

In addition, another object of the present invention is to provide a method of manufacturing a CMOS image sensor that can ensure uniformity without performing a photo process and an etching process that are additionally performed before the CMP process.

In addition, another object of the present invention is to provide a method for manufacturing a CMOS image sensor that can control the thickness of the device isolation film to a target thickness to stabilize the subsequent process.

According to an aspect of the present invention, there is provided a method of forming a trench by depositing a pad oxide film and a pad nitride film on a substrate, etching the pad nitride film, the pad oxide film, and the substrate to form a trench, and forming the trench. Forming a channel stop region at an inner wall portion and a bottom surface of the insulating layer; depositing an insulating film for device isolation to fill the trench; and using a slurry having a high selectivity between the insulating film for device isolation and the pad nitride film. Performing a planarization process to selectively polish the insulating film for the device isolation layer, performing a front surface etching process to planarize the pad nitride film and the device isolation film, and removing the pad nitride film to form the device isolation film It provides a method for manufacturing a CMOS image sensor comprising the steps.

In addition, during the planarization process, the insulating film for the device isolation layer is excessively polished to be lower than the height of the pad nitride film so that the pad nitride film protrudes.

Preferably, the planarization process is performed by a chemical mechanical polishing (CMP) process.

In addition, during the entire surface etching process, the pad nitride layer and the insulation layer for the device isolation layer are etched and planarized.

Preferably, the front etch process is performed by an etch back or blanket process.

Preferably, the insulating film for the device isolation film is an HDP (High Density Plasma) oxide film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4A to 4F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention. 4A to 4F, only the device isolation layer forming process including the channel stop region is illustrated for convenience of description.

First, as shown in FIG. 4A, the pad oxide film 111 and the pad nitride film 112 are sequentially formed on the semiconductor substrate 110. In this case, the substrate 110 has a structure in which a P + region and a P- epi layer are stacked. In addition, the pad nitride film 112 is formed to a thickness of about 1600 to 1800 kPa, preferably 1700 kPa.

Next, a trench trench isolation (STI) process is performed to form the trench 113 in the substrate 110.

Subsequently, a dry or wet oxidation process is performed on the inner surface of the trench 113 to form a wall oxide layer 114. The wall oxide film 114 compensates the inner surface of the trench 113 that is damaged during the etching process for forming the trench 113, and rounds the bottom and upper corner portions of the trench 113. It is formed to prevent the problem of deterioration of operating characteristics such as convenience of process progress and leakage current.

Subsequently, as illustrated in FIG. 4B, an isolation ion implantation process 115 is performed to form channel stop regions 116 on the inner and bottom surfaces of the trench 113. In this case, the wall oxide layer 114 functions as a screen oxide layer to minimize damage to the substrate 110.

Subsequently, as shown in FIG. 4C, an HDP oxide film 117 having excellent embedding characteristics is deposited as an insulating film for device isolation so that voids do not occur in the trench 113.

Next, as shown in FIG. 4D, the planarization process 118 is performed to selectively planarize the HDP oxide film 117. At this time, the planarization process 118 is performed by a CMP process. Here, the CMP process selectively polishes the HDP oxide film 117 using a slurry having a high selectivity ratio between the nitride film and the oxide film. That is, the HDP oxide film 117 is excessively polished as in the same figure using a slurry having a higher polishing rate for the oxide film than for the nitride film. As a result, the HDP oxide film 117 is profiled to have a lower thickness than the pad nitride film 12.

For example, the CMP process is performed as shown in Table 1 below.

Low Selectivity Slurry (LSS) CMP High Selectivity Slurry (HSS) CMP Slurry HS1100H (slurry)
HS-T8005-HX (slurry) HS-T8102GP (additive) Pad IC1400K-GRV IC1400K-GRV Disk Diamond Diamond Time 25 minutes + 25 minutes 50 minutes Retaining ring pressure 6.0 psi 6.0 psi Membrane pressure (membrane)
pressure) 4.0psi 4.0psi Inner tube pressure 5.0psi 5.0psi Platen speed 93 rpm 93 rpm Head speed 87 rpm 87 rpm Slurry flow rate 170ml / min 200ml / min

Subsequently, as illustrated in FIG. 4E, the front surface etching process 119 such as an etch back or a blanket is performed to etch the pad nitride layer 112 and the HDP oxide layer 117. At this time, the target during the front etching process 119 is set within the range of 300 ~ 1100Å, such a target is set based on the HDP oxide film 117 etching target.

For example, the front etching process 119 is carried out using 60CF ₄ / 40CHF ₃ / 15OOAr for about 45 "(min) at a pressure of 1000-1500mTorr, a source power of 400-450Ws, and a temperature of room temperature -50 ° C. In this case, the process time may be appropriately changed according to the active residual film after the STI CMP process.

Subsequently, as shown in FIG. 4F, the pad nitride film 112 is removed by performing a wet etching process 120 using phosphoric acid (H ₃ P 0 ₄ ). As a result, the device isolation film 117a having the same profile as in the same drawing is formed.

As described above, in the method of manufacturing the CMOS image sensor according to the preferred embodiment of the present invention, as shown in FIG. 4D, the CMP process 118 is selectively performed by using a slurry having a high selectivity between the nitride film and the oxide film. After polishing 117, the pad nitride film 112 is etched by performing an entire surface etching process 119, such as an etch back or a blanket, as shown in FIG. 4E, thereby securing uniformity. As such, the process can be simplified without the need for a separate photo process and etching process before the CMP process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, in isolation ion implantation process to secure the thickness of the initial pad nitride layer to prevent the inter-pixel interference due to dopant implantation in the active region without additional tuning process, thereby improving device characteristics You can.

Second, after polishing the HDP oxide film selectively through the CMP process, the entire surface etching process such as etch back is performed to etch the pad nitride layer to control the thickness of the device isolation layer to a target thickness, so that a separate photo process is performed before the CMP process as in the prior art. Uniformity can be ensured without performing an etching process, and the isolation characteristics and the process of the device can be simplified.

Third, by controlling the thickness of the device isolation layer through a front surface etching process such as an etch back, it is possible to stabilize the subsequent process, that is, the etching process of the gate electrode and the LDD etching process.

As a result, it is possible to improve the operating characteristics of the CMOS image sensor to increase the yield.

Claims (6)

Depositing a pad oxide film and a pad nitride film on the substrate; Etching the pad nitride film, the pad oxide film, and the substrate to form a trench; Forming a channel stop region in the inner wall portion and the bottom surface of the trench; Depositing an insulating film for an isolation layer to fill the trench; Performing a planarization process using a slurry having a high selectivity ratio between the insulating film for device isolation and the pad nitride film to selectively polish the insulating film for device isolation; Planarizing the pad nitride layer and the isolation layer for the device isolation layer by performing an entire surface etching process; And Removing the pad nitride layer to form an isolation layer Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, And the insulating film for the device isolation layer is excessively polished during the planarization process so as to be lower than the height of the pad nitride film so that the pad nitride film protrudes. The method of claim 2, And the planarization step is a CMP process. The method according to any one of claims 1 to 3, The front surface etching process is a method of manufacturing a CMOS image sensor to planarize by etching the pad nitride film and the insulating film for the device isolation film. The method of claim 4, wherein The front surface etching process is a manufacturing method of the CMOS image sensor to be carried out by the etch back or blanket process. The method of claim 4, wherein And the insulating film for device isolation film is an HDP oxide film.

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