KR101077539B1 - Network on chip and network on chip systems - Google Patents

Abstract

The present invention relates to a network on chip of the present invention.

The network on chip according to the present invention comprises: a plurality of local switch routers for dividing a plurality of IPs into a plurality of clusters having a predetermined number of IPs, and connecting the IPs configured in the plurality of clusters in a star topology structure; One or more upper switch routers that connect local switch routers in a star topology; a plurality of local switch routers and one or more upper switch routers form a vertical hierarchy, and ring routers between switch routers that form the same hierarchy. Characterized in that connected to the structure.

According to the present invention, the average hopping latency required for data communication between IPs can be reduced, and the overall data bandwidth can be increased as compared with the existing hierarchical star topology. In addition, the number of cycles and packet buffering required for data movement can be reduced, thereby minimizing execution time and energy consumption required for data communication.

Network-on-Chip, topology, ring topology, hierarchical star

Description

NETWORK ON CHIP AND NETWORK ON CHIP SYSTEMS

The present invention relates to a network on chip and a network on chip system. More specifically, the present invention relates to a network on chip and a network on chip system for connecting each IP in a multi-core processor including a plurality of IPs.

As the process of semiconductor integrated technology evolves, the circuit line width of the transistor is reduced and the performance is improved. On the other hand, the delay of the global wire connecting the transistor is relatively reduced, and the interconnection problem is now emerging. In addition, with the development of the process, the number of IP (intellecture properties) to be integrated in one chip increases, and the existing bus-based system that interconnects these via one common medium is a data communication band of multiple IPs. bandwidth) It does not meet the requirements.

To solve this interconnection problem, instead of connecting multiple IPs to a single bus to send data directly, the data is converted into packets and passed through several local switch routers. Network on chip (transport on chip) technology that transmits the spotlight. Currently, network-on-chip technology is widely used as an interconnection technology in multi-core systems in which a large number of IPs are integrated, and is gradually replacing the existing bus technology.

1A is a diagram illustrating a mesh topology structure in a conventional network on chip topology.

The mesh topology shown in FIG. 1A is the most frequently used topology in a multi-core processor. As a mesh, neighboring IPs and switch routers are connected in a grid form to provide a wide data bandwith. However, in the mesh topology, N x N IPs need N x N switch routers to connect all of them, which leads to high implementation costs, and the hopping latency between each IP is at least 1 to maximum. 2 x N is variable and has a long disadvantage.

1B is a diagram illustrating a hierarchical star topology in a conventional network on chip topology.

The hierarchical star topology shown in FIG. 1B is similar to the tree topology structure, and has a structure in which N by N IPs are preferentially connected to each other in a star topology structure, and then the switch routers are connected in a star structure. In this case, N + 1 switch routers are required, and the hopping latency is exponentially reduced to 3 ((number of layers x 2)-1). Therefore, the hierarchical star topology structure can implement an efficient connection network at a low cost, but has a disadvantage in that the total data bandwidth is small.

It is an object of the present invention to provide a network-on-chip composed of a new combined topology that can efficiently implement a network using less resources in data communication between IPs in a multi-core processor having a plurality of IPs. .

It is also an object of the present invention to provide a network on chip system employing a combined topology.

The network on chip according to the present invention comprises: a plurality of local switch routers for dividing a plurality of IPs into a plurality of clusters having a predetermined number of IPs, and connecting the IPs configured in the plurality of clusters in a star topology structure; One or more upper switch routers that connect local switch routers in a star topology; a plurality of local switch routers and one or more upper switch routers form a vertical hierarchy, and ring routers between switch routers that form the same hierarchy. Characterized in that connected to the structure.

When increasing the number of IP inside the multi-core processor, it includes a top-level switch router that connects the upper switch routers in a star topology structure,

When there are a plurality of top switch routers, it is preferable that the top switch routers are connected in a ring topology structure.

Some of the plurality of IPs,

It is desirable to connect directly to some of the switch routers of the upper layer of the plurality of local switch routers.

The network-on-chip system according to the present invention divides a plurality of processing units and a plurality of processing units into a plurality of clusters having a predetermined number of processing units, and connects the processing units configured in the plurality of clusters, respectively, in a star topology structure. A plurality of local network switches, one or more system network switches connecting the plurality of local network switches in a star topology structure, connected to the system network switches, and to a plurality of processing units through the system network switches and the plurality of local network switches. A control processor which downloads a program and controls the operation of the system network switch and the plurality of local network switches, and is connected to the system network switch, and predetermined through a system network switch and the plurality of local network switches. It includes a task scheduler for scheduling a task for a program of the plurality of processing units, a plurality of local network switches and a system network switch in a vertical layer structure, the network switches of the same layer are connected in a ring topology structure It is characterized by.

It is preferable to further include an external memory interface connected between the system network switch and the external memory and transferring data intermediate processing results of the plurality of processing units to the external memory.

The network-on-chip system according to the present invention divides 16 processing units, 16 processing units into four clusters, and four local network switches that connect the processing units configured in the four clusters in a star topology structure. The system network switch connects four local network switches in a star topology structure, is connected to the system network switch, and downloads image processing programs to 16 processing units through the system network switch and four local network switches. A control processor that controls the operation of the switch and four local network switches, and connected to the system network switch, and through the system network switch and four local network switches, tasks for the image processing program to Including a task scheduler for scheduling, between the four local network switch and the system network switch to form a vertical hierarchical structure, between the network switches forming the same layer is characterized in that connected in a ring topology structure.

It is further preferred to further comprise two external memory interfaces, each connected between the system network switch and the external memory, for respectively conveying data intermediate processing results of the sixteen processing units to the external memory.

According to the present invention, the average hopping latency required for data communication between IPs can be reduced as compared with the existing layer star topology, and the overall data bandwidth can be increased.

In addition, the number of cycles and packet buffering required for data movement can be reduced, thereby minimizing execution time and energy consumption required for data communication.

Hereinafter, a network on chip and a network on chip system according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a network on chip according to an embodiment of the present invention will be described in detail.

[Network on chip]

2 is a diagram illustrating a network on chip having a structure in which a hierarchical star topology and a ring topology are combined according to an embodiment of the present invention.

Referring to FIG. 2, a network on chip according to the present invention includes a plurality of IPs, a plurality of local switch routers SW1, and a higher switch router SW2, and a hierarchical star topology and a ring topology It is characterized by a combined connection structure.

The plurality of local switch routers SW1 divide the plurality of IPs into a plurality of clusters 20a, 20b, 20c, and 20d having a predetermined number of IPs, and each of the plurality of local switches routers SW1 into divided clusters 20a, 20b, 20c, and 20d. The configured IPs may be connected in a star topology structure. Here, the star topology structure may refer to a form in which a network between IPs is constructed by connecting IPs in a cluster around an arbitrary local switch router SW1.

The upper switch router SW2 may again connect a plurality of local switch routers SW1 in a star topology structure.

In addition, switch routers forming the same layer may be connected in a ring topology structure. Here, the same layer may be regarded as one of the layers formed by the local switch routers SW1 connecting the IPs configured in a cluster unit in a star topology structure. In addition, when there is more than one upper switch router (SW2), the layer formed by the upper switch router (SW2) connecting the local switch routers (SW1) in a star topology structure can be seen as one of them. In this case, the layers formed by the upper switch routers SW2 become upper layers of the layers formed by the local switch routers SW1, and the plurality of local switch routers SW1 and the upper switch routers SW2 are vertically hierarchical structures. In this case, the star network structure is connected to the hierarchical star topology, and the switch routers that form the same layer are connected to the ring topology to form a ring network structure.

FIG. 3 is a diagram illustrating a combined topology structure in which the star topology and the ring topology illustrated in FIG. 2 are expanded when the number of IPs is 64 in a multi-core processor.

As shown in FIG. 3, when the number of IPs is increased in the multi-core processor, the uppermost switch router SW3 connecting the upper switch routers SW2 in a star topology structure may be included. In this case, when there are a plurality of top switch routers SW3, the top switch routers SW3 are connected in a ring topology structure, and the layers formed by the top switch routers SW3 are a layer formed by the top switch routers SW2 and local. It becomes a higher layer to the layer formed by the switch routers SW1. Accordingly, in the network on chip topology according to the present invention, when the number of IPs is increased, the network on chip can be expanded by increasing the number of layers by applying a combined structure of a layer star topology and a ring topology.

Meanwhile, the plurality of IPs may be a combination of IPs that are the same or not the same. In addition, some of the plurality of IPs may be directly connected to a part of a switch router (upper switch router SW2 or top switch router SW3) that is a higher layer of the plurality of local switch routers SW1 as necessary. In addition, the network-on-chip topology structure according to the present invention may be either a symmetric topology or an asymmetric topology, as shown in FIGS. 2 and 3.

The network on chip topology according to the present invention takes a connection structure combining a vertical layer star topology structure and a horizontal ring topology structure for the same layer in network connection between a plurality of IPs. Thus, in data communication between a plurality of IPs, it is possible to reduce hopping latency, to distribute data movement from each IP to a higher level switch router, and to increase the total data bandwith, The problem of the existing mesh topology and hierarchical star topology structure can be improved.

Table 1 below is a table comparing N × N IPs with implementation cost, hopping latency, and bandwiths for each of mesh, layer star, and combined topology.

Referring to Table 1, in the case of the layer star and ring coupling topology, fewer switch routers are used compared to the existing mesh topology, thereby reducing the implementation cost. In addition, the layer star and ring coupling topology can further reduce the hopping latency of the existing layer star topology. In addition, it is possible to provide a wider band withs than the data bands with the existing hierarchical star topology.

Therefore, the hierarchical star and ring coupling topology according to the present invention can solve the implementation cost problem of the existing mesh topology. In addition, it is possible to not only increase the data band with the existing hierarchical star topology structure, but also reduce the hopping latency.

Next, a network on chip system according to an embodiment of the present invention will be described in detail.

[Network on chip system]

The network on chip system according to an embodiment of the present invention is an embodiment to which the above-described network on chip topology is applied and will be described in detail with reference to an image processing system as a specific example.

4A is a diagram illustrating the overall configuration of a network on a chip system according to an embodiment of the present invention.

Referring to FIG. 4A, a network chip system according to the present invention includes a plurality of processing units PU1 to PU16, a plurality of local network switches 410a, 410b, 410c, and 410d, a system network switch 420, and a control processor 430. ), A task scheduler 440 and external memory interfaces 450a and 450b.

More specifically, in the network on a chip system for image processing according to an embodiment of the present invention, 16 process units (PU1 to PU16), four 7x7 local network switches (410a, 410b, 410c, 410d), one 8x8 system The network switch 420 may include two external memory interfaces 450a and 450b.

Here, sixteen process units PU1 through PU16 are divided into four clusters through four 7x7 local network switches 410a, 410b, 410c, and 410d, and four 7x7 local network switches between process units configured in each cluster. Through each of the star topology can be connected. The four 7x7 local network switches 410a, 410b, 410c, and 410d may be connected in a star topology structure through the 8x8 system network switch 420. Accordingly, the four local network switches 410a, 410b, 410c, and 410d and the system network switch 420 may be connected in a vertical hierarchical star topology. In addition, the network switches of the same layer are connected in a ring topology structure. In FIG. 4A, four local network switches 410a, 410b, 410c, and 410d are illustrated in a structure connected in a ring topology with one same layer. However, when more processing units are added and expanded in a network on chip system, The local network switch and the system network switch may be added, and the added system network switches form one same layer, and the system network switches forming the same layer may be connected to each other in a ring topology structure. In addition, if necessary, a higher system network switch for connecting the added system network switch in a star topology structure may be added. In this manner, the network on chip system may be extended.

The control processor 430, the task scheduler 440, and the two external memory interfaces 450a and 450b may be directly connected to the 8 × 8 system network switch 420.

The control processor 430 may download a program for image processing to the processing units PU1 to PU2 through the local network switches 410a, 410b, 410c, and 410d and the system network switch 420. In addition, the control processor 430 may control operations of the local network switches 410a, 410b, 410c, and 410d and the system network switch 420.

The task scheduler 440 may schedule a task for a predetermined image area with each processing unit PU1 to PU2 along with the program download through the control processor 430.

In the external memory interfaces 450a and 450b, data to be processed by each processing unit PU1 to PU2 is loaded from an external memory (not shown), and an intermediate result of data processed through each processing unit PU1 to PU2 is external. It may be connected between the external memory and the 8x8 system network switch 420 so as to be stored in the memory.

FIG. 4B is a diagram illustrating an operation sequence of the network on chip system shown in FIG. 4A.

First, as shown in FIG. 4B, the control processor 430 programs a program to the processing units PU1 to PU2 through the plurality of local network switches 410a, 410b, 410c, and 410d and the system network switch 420. Will be downloaded. At this time, the task scheduler 440 schedules a task for the image area to each of the processing units PU1 to PU2.

Thereafter, the processing units PU1 to PU2 load image data from an external memory (not shown) through the external memory interface 450 to perform predetermined data processing. In this process, frequent data communication is performed between the processing units PU1 to PU2, and data intermediate processing results, which are not solved by the system internal memory during the image processing, are output through the external memory interface 450. Will be saved as).

In the network on a chip system according to an embodiment of the present invention, 16 processing units PU1 to PU2 are star layered through four local network switches 410a, 410b, 410c, and 410d and a system network switch 420. The topologies are connected and four local network switches 410a, 410b, 410c, and 410d are connected in a ring topology. In addition, in order to connect each of the local network switches 410a, 410b, 410c, and 410d with a ring network, two ports were added to each of the local network switches 410a, 410b, 410c, and 410d to be changed to a 7x7 switch. The ring network facilitates data movement between 16 local network switches 410a, 410b, 410c, and 410d, thereby reducing the data movement load to the system network.

More specifically, when moving data packets between processing units adjacent to each other, the conventional hierarchical star topology has to go through three switches, but only two switches in the network on chip system applying the combined topology according to the present invention. This assumes that the same number of processing units has a lower average hopping latency than the hierarchical star topology in data movement between processing units.

In addition, when the network-on-chip system according to the present invention operates at 400MHz, the ring network can provide a total of 25.6 GB / s (4 x 4 x 0.4 GHz x 4B) data band Weeds, which is a conventional layer star 89.6 GB / s (4 x 10 x 0.4 GHz x 4B + 1 x 16 x 0.4 GHz x 4B) of the topology is about 30% of the bandwidth.

Table 2 below is a table showing the combined topology effect in the network on a chip system according to an embodiment of the present invention compared with the existing hierarchical star topology structure.

In order to measure the gain of a network-on-chip system employing the combined topology according to the present invention, when processing one image frame in an image processing application where data communication between processing units occupies about 30% of the total data movement, the combined topology The number of cycles and the number of buffers of data packets were measured for the system to which the system is applied and the system to which the hierarchical star topology is applied. As a result, the combined topology according to the present invention has gained about 19% in cycle count by reducing the number of switch hops required for data communication between processing units. In addition, since the data packets pass through fewer switches, the number of packet buffer rungs in the switch can be reduced by about 21%. Since most of the energy in the network on chip is consumed by packet buffering in the switch carrying the data packet, it is possible to reduce the overall energy consumption of the network on chip system by reducing the number of buffering.

As described above, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features.

Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive, and the scope of the present invention is indicated by the following claims rather than the above description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1A illustrates a mesh topology structure in a conventional network on chip topology.

1B illustrates a hierarchical star topology structure in a conventional network on chip topology.

2 is a diagram illustrating a structure in which a hierarchical star topology and a ring topology are combined according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a combined topology structure in which the star topology and the ring topology shown in FIG. 2 are expanded when the number of IPs is 64 in a multi-core processor; FIG.

4A is a diagram illustrating a configuration of a network on chip system for image processing according to an embodiment of the present invention.

FIG. 4B is a view showing an operation sequence of the network on chip system shown in FIG. 4A.

Claims (7)

In the multi-core processor including a plurality of IP (Intellecture Property) relates to a network on a chip that connects between each IP, A plurality of local switch routers for dividing the plurality of IPs into a plurality of clusters having a predetermined number of IPs, and connecting the IPs respectively configured in the plurality of clusters in a star topology structure; And One or more upper switch routers connecting the plurality of local switch routers in a star topology structure; And the plurality of local switch routers and the at least one upper switch router form a vertical hierarchical structure, and switch routers forming the same layer are connected in a ring topology structure. The method of claim 1, When increasing the number of IP in the multi-core processor, and includes a top switch router for connecting the upper switch routers in a star topology structure, When there are a plurality of top switch routers, the top switch routers, characterized in that connected in a ring topology structure, network on chip. The method of claim 1, Some of the plurality of IPs, And directly connect with a portion of a switch router of a higher layer of the plurality of local switch routers. A plurality of processing units; A plurality of local network switches for dividing the plurality of processing units into a plurality of clusters having a predetermined number of processing units, and connecting the processing units respectively configured in the plurality of clusters in a star topology structure; One or more system network switches connecting the plurality of local network switches in a star topology structure; Connected to the system network switch, downloading a predetermined program to the plurality of processing units through the system network switch and the plurality of local network switches, and controlling the operation of the system network switch and the plurality of local network switches. Control processor; And A task scheduler coupled to the system network switch, the task scheduler scheduling the task for the predetermined program to the plurality of processing units via the system network switch and the plurality of local network switches; And the plurality of local network switches and the system network switch form a vertical hierarchical structure, and network switches of the same layer are connected in a ring topology structure. 5. The method of claim 4, And an external memory interface coupled between the system network switch and an external memory, the external memory interface transferring data intermediate processing results of the plurality of processing units to the external memory. 16 processing units; Four local network switches that divide the sixteen processing units into four clusters and connect between the processing units configured in the four clusters in a star topology structure; A system network switch connecting the four local network switches in a star topology structure; Is connected to the system network switch, downloads an image processing program to the sixteen processing units through the system network switch and the four local network switches, and controls the operation of the system network switch and the four local network switches. Control processor; And A task scheduler coupled to the system network switch, the task scheduler scheduling the task for the image processing program to the sixteen processing units via the system network switch and the four local network switches; And the four local network switches and the system network switch form a vertical hierarchical structure, and network switches of the same layer are connected in a ring topology structure. The method of claim 6, And two external memory interfaces, each connected between the system network switch and an external memory, for transferring data intermediate processing results of the sixteen processing units to the external memory, respectively.

Images