KR101068642B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device capable of alleviating a Passing Gate Effect and a method of manufacturing the same. The semiconductor device of the present invention provides a separation of the device on a substrate having a device isolation region and an active region. A gate crossing the region and the active region at the same time, and an interference barrier layer disposed between the device isolation region and the gate, and according to the present invention, an interference barrier layer between the gate passing through the device isolation region and the device isolation region. By forming a to increase the physical distance between the main gate and the passing gate, there is an effect that can mitigate the passing gate effect.

Ion implantation, oxygen, passing gate, interference prevention film

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same that can alleviate a Passing Gate Effect.

Recently, as semiconductor devices are highly integrated, channel lengths of gates decrease, which causes threshold voltages to decrease and refresh characteristics to deteriorate. In order to solve this problem, a recess gate (RG) structure for increasing a channel length by recessing a substrate to a predetermined depth is introduced and applied.

FIG. 1A is a plan view illustrating a semiconductor device according to the related art, and FIG. 1B is a cross-sectional view taken along the line X-X ′ of FIG. 1A.

1A and 1B, a gate 18 simultaneously crossing the device isolation layer 12 and the active region 13 is formed on a substrate 11 on which the active region 13 is defined as the device isolation layer 12. Formed. The gate 18 has a structure in which the gate insulating film 15, the gate electrode 16, and the gate hard mask film 17 are sequentially stacked. A recess pattern 14 is formed in the substrate 11 under the gate 18 of the active region 13. Here, the gate 18 passing through the active region 13 is called a main gate, and the gate 18 passing through the device isolation layer 12 is called a passing gate.

However, in the above-described prior art, as the semiconductor device is highly integrated, the physical distance between the main gate and the passing gate is gradually decreasing. As a result, there is a problem that a so-called Passing Gate Effect occurs due to a change in the threshold voltage of the main gate and a parasitic capacitance between the main gate and the passing gate due to the bias applied to the passing gate. (See 'X' in FIG. 1A).

In addition, in the above-described conventional technique, a portion of the device isolation layer 12 is also etched during the etching process for forming the recess pattern 14 in the active region 13, resulting in loss. In this case, the loss of the device isolation layer 12 is typically etched to 1/3 to 1/2 of the recess pattern 14. The loss of the device isolation layer 12 has a problem in that the physical distance between the main gate and the passing gate is further reduced to deepen the passing gate effect (see 'X' in FIG. 1B).

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can alleviate the passing gate effect.

According to an aspect of the present invention, there is provided a semiconductor device including a gate that simultaneously crosses an element isolation region and an active region on a substrate having an element isolation region and an active region, and the device isolation region and the gate. Interference prevention film interposed between is included. In this case, the interference prevention layer may be locally disposed only between the gate and the device isolation region in contact with both edges of the active region.

The gate may include a gate insulating film formed on the substrate; The gate electrode may include a gate electrode including a silicon layer on the gate insulating layer and a gate hard mask layer formed on the gate electrode. Here, the interference prevention film may be an oxide film, and more specifically, the silicon film may be an oxidized silicon oxide film.

The display device may further include a recess pattern formed in the active region under the gate.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a gate conductive film on a substrate having an isolation region and an active region; Forming an interference prevention layer by partially oxidizing the gate conductive layer formed on the device isolation region; Selectively etching the gate conductive layer to form a gate electrode including the interference preventing layer and simultaneously crossing the device isolation region and the active region.

The forming of the anti-interference layer may include forming an ion implantation mask exposing the gate conductive layer on the device isolation region; The ion implantation mask may include ion implanting oxygen (O ₂ ) into the gate conductive layer using an ion implantation barrier and performing a heat treatment.

The gate conductive layer may include a silicon layer, and the interference prevention layer may include a silicon oxide layer.

The method may further include forming a recess pattern by selectively etching the substrate before forming the gate conductive layer.

The present invention based on the above-described problem solving means can form an interference barrier between the gate passing through the device isolation region and the device isolation region to increase the physical distance between the main gate and the passing gate, thereby alleviating the passing gate effect. It has an effect.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention described below provides a semiconductor device and a method for manufacturing the same, which can alleviate a passing gate effect between a main gate passing through an active region and a passing gate passing through an isolation region. do. To this end, the present invention is to increase the physical distance between the main gate and the passing gate by forming an interference barrier between the gate (that is, the passing gate) passing through the device isolation region and the device isolation region.

2 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 2, the semiconductor device of the present invention includes a gate 109 simultaneously crossing the device isolation region and the active region 103 on the substrate 101 including the device isolation region and the active region 103. An interference prevention film 110 interposed between the device isolation region and the gate 109. In this case, the device isolation region refers to an area of the substrate 101 on which the device isolation layer 102 is formed.

The interference prevention layer 110 increases the physical distance between the main gate passing through the active region 103 and the passing gate passing through the device isolation layer 102 to mitigate the passing gate effect therebetween. The anti-interference film 110 may be formed of an oxide film.

The anti-interference film 110 may be formed between the device isolation film 102 and the gate 109 or may be locally formed only between the device isolation film 102 and the gate 109 in contact with both edges of the active region 103.

The gate 109 may have a structure in which the gate insulating layer 105, the first gate electrode 106, the second gate electrode 107, and the gate hard mask layer 108 are stacked.

The gate insulating layer 105 may be an oxide layer, for example, a silicon oxide layer (SiO ₂ ).

The first gate electrode 106 is preferably formed of a material having excellent interface characteristics with the gate insulating film 105. Therefore, the first gate electrode 106 may be a silicon film. As the silicon film, a polysilicon film (poly-Si) or a silicon germanium film (SiGe) may be used. Here, the anti-interference film 110 may be a material constituting the first gate electrode 106, that is, a silicon oxide film (SiO ₂ ) formed by oxidizing a silicon film.

In order to reduce the resistance of the gate 109, the second gate electrode 107 may be formed of a material having a lower specific resistance than that of the first gate electrode 106. Accordingly, the second gate electrode 107 may be a metallic film. Tungsten film W, titanium nitride film TiN, tungsten silicide WSi, or the like may be used as the metallic film.

The gate hard mask film 108 serves to protect the first and second gate electrodes 106 and 107 between processes, and any one or these selected from the group consisting of an oxide film, a nitride film, and an oxynitride layer are laminated. It can be formed into a laminated film.

In addition, the semiconductor device of the present invention may further include a recess pattern 104 formed in the substrate 101 under the gate 109. The recess pattern 104 may have a shape of any one of a rectangle, a polygon, and a bulb type. In this case, the bulb type means a recess pattern having a structure wider than an upper portion thereof.

As described above, according to the present invention, by providing the anti-interference layer 110, the physical distance between the main gate and the passing gate can be increased to alleviate the passing gate effect therebetween.

3A through 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, after forming a trench (not shown) for device isolation in the substrate 21, an isolation material 22 is formed by filling an insulating material in the trench. The device isolation film may be formed of an oxide film. The oxide film may be formed of a high density plasma oxide (HDP) film, a spin on dielectric film (SOD), or a laminated film in which these layers are stacked. Typically, an area of the substrate 21 on which the device isolation film 22 is formed is referred to as an 'device isolation region', and an area of the substrate 21 on which the device isolation film 22 is not formed is called an active region 23.

Next, after forming a hard mask pattern (not shown) for forming the recess pattern 24 on the substrate 21, the substrate 21 is etched using the hard mask pattern as an etch barrier. The set pattern 24 is formed. In this case, the recess pattern 24 may be selectively formed only in the active region 23 of the substrate 21.

An etching process for forming the recess pattern 24 may be performed using a dry etch method. In this case, when the recess pattern 24 is to be formed only in the active region 23 of the substrate 21, an etching gas having a faster etching rate with respect to the substrate 21 than an etching rate with respect to the device isolation layer 22 is used. Can be carried out.

Here, the hard mask pattern for forming the recess pattern 24 uses a line pattern that simultaneously crosses the device isolation layer 22 and the active region 23 in order to reduce process difficulty. Accordingly, the groove 25 is formed in the device isolation layer 22 while the device isolation layer 22 is partially etched during the etching process for forming the recess pattern 24. In this case, the depth of the groove 25 has a level 1/3 to 1/2 of the depth of the recess pattern 24.

The recess pattern 24 may be formed in a polygonal or bulb type in addition to the quadrangle shown in the drawing. In this case, the bulb type means a recess pattern having a structure wider than an upper portion thereof.

Next, a gate insulating film 26 is formed on the surface of the substrate 21 including the recess pattern 24. The gate insulating film 26 may be formed of an oxide film, and a silicon oxide film (SiO ₂ ) may be used as the oxide film. The silicon oxide film may be formed using thermal oxidation, dry oxidation, or wet oxidation.

Next, the recess pattern 24 is buried in the upper portion of the substrate 21, and a first gate conductive layer 27 is formed to partially cover the upper surface of the substrate 21. Preferably, the first gate conductive film 27 is formed of a gate insulating film 26, for example, a silicon film having excellent interfacial properties with the silicon oxide film. As the silicon film, a polysilicon film (poly-Si), a silicon germanium film (SiGe), or the like can be used.

As shown in FIG. 3B, a portion of the first gate conductive layer 27 is selectively oxidized to form an interference prevention layer 27A. The interference prevention film 27A increases the physical distance between the main gate and the passing gate to mitigate the passing gate effect therebetween.

Hereinafter, a method of selectively oxidizing a part of the first gate conductive film 27 to form the interference prevention film 27A will be described in detail.

First, an ion implantation mask 28 for forming the interference preventing film 27A is formed on the first gate conductive film 27. In this case, the ion implantation mask 28 may be formed using a photoresist.

Here, the ion implantation mask 28 may be formed to cover the first gate conductive layer 27 on the active region 23 and to expose the first gate conductive layer 27 on the device isolation layer 22. have. In this case, the ion implantation mask 28 may be formed using a device isolation mask for device isolation. Therefore, the manufacturing cost of the semiconductor device can be reduced because a separate mask is not manufactured. In addition, the ion implantation mask 28 may be formed to partially expose the first gate conductive layer 27 on the device isolation layer in contact with both edges of the active region 23.

Next, oxygen (O ₂ ) is ion implanted into the first gate conductive film 27 using the ion implantation mask 28 as an injection barrier. In the ion implantation process, the ion implantation depth R _p is a target in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ , targeting a contact surface where the device isolation film 22 and the first gate conductive film 27 contact each other. You can proceed with the amount. In this case, the ion implantation depth R _p is more preferably directed to a contact surface where the lower surface of the groove 25 of the device isolation layer 22 and the first gate conductive layer 27 contact each other.

Next, heat treatment is performed to activate the injected oxygen ions. The heat treatment may be carried out using a furnace heat treatment method or a rapid heat treatment method (RTP).

As a result, a portion of the first gate conductive layer 27 formed on the device isolation layer 22 may be selectively oxidized to form the interference prevention layer 27A. Accordingly, the interference prevention film 27A may be formed of an oxide film, in particular, a silicon oxide film (SiO ₂ ) in which a silicon film is oxidized.

In addition, since the ion implantation depth R _p advances to the contact surface where the lower surface of the groove 25 of the device isolation film 22 and the first gate conductive film 27 contact with each other, the groove 25 of the device isolation film 22. The interference prevention layer 27A may be formed by oxidizing the first gate conductive layer 27 embedded in the second gate conductive layer 27, thereby increasing the physical distance between the main gate and the passing gate more effectively.

As a result, the present invention can alleviate the passing gate effect between the main gate and the passing gate by forming the interference prevention film 27A.

As shown in FIG. 3C, the second gate conductive layer 28 and the gate hard mask layer 30 are sequentially formed on the first gate conductive layer 27. The second gate conductive film 28 is preferably formed of a material having a lower resistivity than the first gate conductive film 27, for example, a metallic film. Tungsten film W, titanium nitride film TiN, tungsten silicide WSi, or the like may be used as the metallic film. The gate hard mask layer 30 serves as a hard mask and protects the gate electrode during an etching process for forming a subsequent gate. The gate hard mask film 30 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which they are stacked.

to the next. After the photoresist pattern (not shown) is formed on the gate hard mask layer 30, the gate hard mask layer 30, the second gate conductive layer 28, and the first gate conductive layer are formed using the photoresist pattern as an etch barrier. A gate 31 is formed by sequentially etching the 27 and the gate insulating layer 26. Hereinafter, the reference numeral of the etched gate hard mask layer 30 is changed to '30A' and the reference numeral of the etched gate insulating layer 26 is changed to '26A'.

Through the above-described process, the device isolation film 22 and the active region 23 are simultaneously crossed, and the gate insulating film 26A, the first gate electrode 31, the second gate electrode 29A and the gate hard mask film ( The gate 31 having a structure in which 30A) is sequentially stacked may be formed. In this case, the gate 31 passing through the device isolation layer 22 may include an interference prevention layer 27A under the first gate electrode 31.

As described above, according to the present invention, by forming the interference prevention layer 27A, the physical distance between the main gate passing through the active region 23 and the passing gate passing through the device isolation layer 22 can be increased to alleviate the passing gate effect.

Next, although not shown in the drawing, impurity ion implantation is performed to form a junction region, that is, a source and a drain region, on the substrate 21 of the active region 23 on both sides of the gate 31 using the gate 31 as an ion implantation barrier. do. In this case, P-type impurities (eg, phosphorus (P), arsenic (As)) or N-type impurities (eg, boron (B)) may be used as the impurities.

Next, a heat treatment for activating the implanted impurities is performed. The heat treatment may be a furnace heat treatment method or a metal heat treatment method.

Meanwhile, after the oxygen ion implantation for forming the interference prevention film 27A is performed, the interference prevention film 27A is activated by activating the implanted oxygen ions during the heat treatment to activate the impurities injected into the junction region without performing the heat treatment process. It may be formed. In this case, it is possible to reduce the thermal burden on the semiconductor device for heat treatment and to simplify the manufacturing process of the semiconductor device.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A is a plan view showing a semiconductor device according to the prior art.

FIG. 1B is a cross-sectional view taken along the line X-X 'of FIG. 1A; FIG.

2 is a sectional view showing a semiconductor device according to the first embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

101, 21: substrate 102, 22: device isolation film

103, 12: active region 104, 24: recess pattern

109, 31: gate 110, 27A: interference prevention film

Claims (16)

delete delete delete delete delete delete delete Forming a gate conductive film on a substrate having a device isolation region and an active region; Forming an interference prevention layer by partially oxidizing the gate conductive layer formed on the device isolation region; And Selectively etching the gate conductive layer to form a gate electrode including the anti-interference layer and simultaneously crossing the device isolation region and the active region Semiconductor device manufacturing method comprising a. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, Forming the interference prevention film, Forming an ion implantation mask exposing the gate conductive layer on the device isolation region; Ion implanting oxygen (O ₂ ) into the gate conductive layer using the ion implantation mask as an ion implantation barrier; And Step of performing heat treatment Semiconductor device manufacturing method comprising a. Claim 10 was abandoned upon payment of a setup registration fee. 10. The method of claim 9, And the ion implantation mask partially exposes a gate conductive layer on the device isolation region in contact with both edges of the active region. Claim 11 was abandoned upon payment of a setup registration fee. 10. The method of claim 9, The ion implantation depth R _p at the ion implantation targets a contact surface between the device isolation region and the gate conductive layer. Claim 12 was abandoned upon payment of a registration fee. 10. The method of claim 9, The ion implantation method is a semiconductor device manufacturing method performed by the dose amount (atoms / cm ³ ) in the range of 1 × 10 ¹⁵ ~ 1 × 10 ¹⁷ . Claim 13 was abandoned upon payment of a registration fee. The method of claim 8, And the gate conductive film comprises a silicon film. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, Claim 15 was abandoned upon payment of a registration fee. The method of claim 8, Before forming the gate conductive film, Selectively etching the substrate to form a recess pattern. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 15, The recess pattern includes any one selected from the group consisting of a rectangle, a polygon, and a bulb shape.

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