KR101067223B1 - Package substrate - Google Patents

Abstract

The present invention discloses a package substrate. The package substrate includes a core layer; A first inner layer circuit layer disposed on the core layer; A first inner layer insulating layer disposed on the first inner layer circuit layer; A first outer layer circuit layer disposed on the first inner layer insulating layer and having a first outer layer pad; A second inner layer circuit layer disposed below the core layer; A second inner layer insulating layer disposed below the second inner layer circuit layer and having a thickness different from that of the first inner layer insulating layer; And a second outer layer circuit layer disposed under the second inner layer insulating layer and having a second outer layer pad.

Package, insulation layer, circuit layer, thickness, thermal expansion, bending

Description

Package substrate

The present invention relates to a package substrate, and more particularly, to a package substrate having an inner insulating layer or an inner circuit layer having different thicknesses on upper and lower portions thereof.

Recently, as electronic products become smaller and lighter, semiconductor device components provided therein also tend to be smaller and thinner. In order to cope with such a technology trend, interest in the technology of a semiconductor package for mounting a semiconductor device on a package substrate is increasing.

The semiconductor package may include a package substrate, a semiconductor chip mounted on an upper surface of the package substrate, a molding member encapsulating the semiconductor chip, and a lower surface of the package substrate and electrically connected to the semiconductor chip and an external circuit unit such as a main board substrate. It may include a solder ball to.

The package substrate may include a circuit layer and an insulating layer that are sequentially stacked. At this time, the upper circuit layer centered around the core layer of the package substrate has a complicated circuit pattern structure compared to the lower circuit layer. Accordingly, since the upper circuit layer has a smaller amount of Cu remaining in the circuit layer than the lower circuit layer, the upper insulating layer has a larger filling amount of the insulating resin forming the insulating layer than the lower insulating layer.

Here, the insulating resin is a thermoplastic resin, when exposed to heat, the upper and lower insulating layers may shrink due to the polymerization reaction.

In this case, the upper and lower insulating layers have different filling amounts due to the pattern difference between the upper and lower circuit layers, and thus have different shrinkage rates due to heat in a heating process, for example, a soldering process or a molding process. That is, since the upper insulating layer has a larger filling amount of the insulating resin than the lower insulating layer, the upper insulating layer has a larger shrinkage than the lower insulating layer. As a result, the package substrate may cause deformation such as warping.

The warpage problem of the package substrate may cause a bonding defect between the semiconductor chip and the package substrate or a bonding defect between the package substrate and the main board substrate, which may not only lower the reliability of the package but also lower the mass productivity.

Accordingly, the present invention has been made to solve a problem that may occur in a conventional package substrate, and an object thereof is to provide a package substrate having an inner insulating layer or an inner circuit layer having different thicknesses on the upper and lower portions thereof. .

It is an object of the present invention to provide a package substrate. The package substrate includes a core layer; A first inner layer circuit layer disposed on the core layer; A first inner layer insulating layer disposed on the first inner layer circuit layer; A first outer layer circuit layer disposed on the first inner layer insulating layer and having a first outer layer pad; A second inner layer circuit layer disposed below the core layer; A second inner layer insulating layer disposed below the second inner layer circuit layer and having a thickness different from that of the first inner layer insulating layer; And a second outer layer circuit layer disposed under the second inner layer insulating layer and having a second outer layer pad.

Here, the second inner layer insulating layer may have a larger thickness than the first inner layer insulating layer.

The first inner layer insulating layer may include one insulating layer, and the second inner layer insulating layer may include at least two or more multilayer insulating layers stacked.

In addition, at least two insulating layers of the multilayer insulating layer may be made of a material having a different thermal expansion coefficient.

In addition, at least one of the first and second inner layer insulating layers may have a bending pattern.

In addition, the first and second inner layer insulating layer may include a bending preventing filling structure filled in the through-hole formed in at least one.

In addition, the anti-bending filling structure may have a coefficient of thermal expansion different from that of the first and second inner layer insulating layers.

In addition, the first pad may be electrically connected to the semiconductor chip, and the second pad may be electrically connected to the motherboard.

Another object of the present invention is to provide a package substrate. The package substrate includes a core layer; A first inner layer circuit layer disposed on the core layer; A first inner layer insulating layer disposed on the first inner layer circuit layer; A first outer layer circuit layer disposed on the first inner layer insulating layer and having a first outer layer pad; A second inner circuit layer disposed below the core layer and having a thickness different from that of the first inner circuit layer; A second inner layer insulating layer disposed below the second inner layer circuit layer; And a second outer layer circuit layer disposed under the second inner layer insulating layer and having a second outer layer pad.

Here, the second inner circuit layer may have a smaller thickness than the first inner circuit layer.

In addition, the first and second inner layer insulating layers may have the same thickness.

In addition, the first pad may be electrically connected to the semiconductor chip, and the second pad may be electrically connected to the motherboard.

Since the package substrate of the present invention includes an inner insulation layer or an inner circuit layer having different thicknesses on the upper and lower portions thereof, it is possible to prevent the occurrence of warpage of the package substrate due to the difference in shrinkage of the upper and lower inner insulation layers. .

In addition, the reliability and mass productivity of a package manufactured using the package substrate of the present invention can be further improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of the package substrate. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view of a package substrate according to a first embodiment of the present invention.

Referring to FIG. 1, a package substrate according to an exemplary embodiment of the present invention may include a core layer 100, a first inner layer circuit layers 121 and 122, a first inner layer insulating layers 111 and 112, and a first outer layer circuit layer ( 123, the second inner circuit layers 141 and 142, the second inner insulating layers 131 and 132, and the second outer circuit layers 143.

The first inner layer circuit layers 121 and 122, the first inner layer insulating layers 111 and 112, and the first outer layer circuit layer 123 may be disposed on the core layer 100 with respect to the core layer 100. have. Here, the first inner layer circuit layers 121 and 122 and the first inner layer insulating layers 111 and 112 may be formed in alternating layers, but for convenience of description, the first inner layer circuit layers 121 and 122 and the first inner layer circuit layers 121 and 122 may be formed. The inner insulation layers 111 and 112 are illustrated as two layers, respectively, but are not limited thereto.

The first outer circuit layer 123 may include a first pad 123a electrically connected to the semiconductor chip. Here, the first pad 123a and the semiconductor chip may be electrically connected to each other using solder balls or wires.

Meanwhile, the second inner layer circuit layers 141 and 142, the second inner layer insulating layers 131 and 132, and the second outer layer circuit layer 143 are disposed below the core layer 100 with respect to the core layer 100. Can be. Here, the second inner layer circuit layers 141 and 142 and the second inner layer insulating layers 131 and 132 may be formed in multiple layers, but for convenience of description, the second inner layer circuit layers 141 and 142 and the second inner layer insulating layers may be formed. Reference numerals 131 and 132 are illustrated in two layers, respectively, but are not limited thereto.

The second outer layer circuit layer 143 may include a second pad 143a to be electrically connected to an external circuit unit, for example, a motherboard. In this case, the second pad 143a and the main board may be electrically connected to each other by solder balls.

The first and second inner layer circuit layers 121. 122, 141, and 142 of the multilayer may be electrically connected to each other by vias 130 formed in the first and second inner layer insulating layers 111, 112, 131, and 132, respectively. Can be. Here, the via 130 may include a conductive paste filled in the via hole penetrating through the first and second inner layer insulating layers 111, 112, 131, and 132.

In addition, a solder resist pattern 150 exposing the first and second pads 123a and 143a may be further disposed on the first outer circuit layer 123 and the second outer circuit layer 143, respectively.

In addition, the core layer 100 includes a hole 102 penetrating the body, and the first and second inner layer circuit layers 121. 122, 141, and 142 may be electrically connected to each other through the hole 102. All.

In addition, the inside of the hole 102 may be filled with a conductive or insulating filler 101.

The first and second inner circuit layers 121. 122, 141, and 142 will be described in more detail. The first inner circuit layers 121 and 122 and the second inner circuit layers 141 and 142 have different pattern structures. As described above, the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 have different amounts of filling of different insulating resins. For example, since the first inner circuit layers 121 and 122 have a complicated circuit pattern compared to the second inner circuit layers 141 and 142, the first inner circuit layers 121 and 122 may be formed of the second inner circuit layer ( 141, 142 may have a smaller amount of Cu.

Therefore, when the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 have the same thickness, the first inner layer insulating layers 111 and 112 have the second inner layer insulating layers 131 and 131. Compared with 132, the amount of filling of the insulating resin can be relatively high, so that the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 have different shrinkage rates, that is, different coefficients of thermal expansion. Have. That is, the package substrate has the first and second inner layer insulating layers 111, 112, 131, and 132 disposed on the bottom and the bottom of the core layer 100, respectively, and have different shrinkage rates due to heat. It may cause deformation.

In order to solve this problem, the first and second inner layer insulating layers 111, 112, 131, and 132 may be formed to have different thicknesses. For example, when the first inner layer insulating layers 111 and 112 have a larger amount of insulating resin than the second inner layer insulating layers 131 and 132, the thickness d2 of the second inner layer insulating layers 131 and 132 may be It may be larger than the thickness d1 of the first inner layer insulating layers 111 and 112. That is, between the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 by controlling the thickness between the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132. The filling amount of insulating resin can be adjusted. As a result, the difference in the filling amount of the insulating resin between the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 can be reduced, so that the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers are reduced. The deflection of the package substrate can be prevented by the difference in the coefficient of thermal expansion between (131, 132). Here, the thicknesses of the first and second inner layer insulating layers 111, 112, 131, and 132 may be variously changed according to the design pattern structure of the first and second inner layer circuit layers 121. 122, 141, and 142. There will be.

The first and second inner layer insulating layers 111, 112, 131, and 132 may be formed by coating insulating resins or laminating prepregs including insulating resins impregnated with glass fibers. Here, examples of the material of the insulating resin may be bismaleimide (BT) resin, poly propylene glycol (PPG), epoxy resin, or the like. In addition, the first and second inner layer insulating layers 111, 112, 131, and 132 may further include an inorganic filler such as silicon oxide particles. In this case, the thicknesses of the first and second inner layer insulating layers 111, 112, 131, and 132 may be the thickness of the prepreg or the insulating resin for forming the first and second inner layer insulating layers 111, 112, 131, and 132. It can be controlled by adjusting the coating thickness of.

As another method for controlling the thicknesses of the first and second inner layer insulating layers 111, 112, 131, and 132, the thickness of the first and second inner layer insulating layers 111, 112, 131, and 132 may be equal to the thickness of the insulating layer. The number of stacks can be adjusted. For example, the first inner layer insulating layers 111 and 112 may include a single insulating layer, and the second inner layer insulating layers 131 and 132 may include a multilayer insulating layer stacked in at least two layers. .

Here, the multilayer insulating layers may be formed of the same material. However, when the first and second inner layer insulating layers 111, 112, 131, and 132 do not improve the warpage problem of the package substrate only by adjusting the thickness, the multilayer insulating layers are formed of different materials having different thermal expansion coefficients. Accordingly, the difference in thermal expansion coefficient between the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 can be reduced. For example, when the multilayer insulating layer is formed of an insulating layer of two layers, one layer may be formed of an epoxy resin, and the other layer may be formed of an epoxy resin containing an inorganic filler capable of reducing the coefficient of thermal expansion. Here, examples of the inorganic filler may be silicon oxide particles.

Therefore, as in the embodiment of the present invention, the thickness of the inner layer insulating layers disposed on the upper and lower portions of the core layer may be differently formed, thereby reducing the difference in thermal expansion coefficient between the inner layer insulating layers disposed on the upper and lower portions, respectively. Therefore, the warpage failure of the package substrate, which may occur in a soldering process or a molding process requiring heat, can be prevented.

2 is a cross-sectional view of a package substrate according to a second embodiment of the present invention.

Here, the second embodiment of the present invention has the same configuration as the first embodiment described above except for a certain pattern. Therefore, the second embodiment of the present invention will be omitted for the convenience of description, and the same configuration will be given the same reference numerals.

2, a package substrate according to an embodiment of the present invention may include a core layer 100, first inner circuit layers 121 and 122 disposed on the core layer 100, and a first inner circuit layer 121. 122) The first inner layer insulating layers 111 and 112 disposed on the upper portion, the first outer layer circuit layers 123 and the core disposed on the first inner layer insulating layers 111 and 112 and having the first pad 123a. The second inner layer circuit layers 141 and 142 disposed below the layer 100, the second inner layer insulating layers 131 and 132 disposed below the second inner layer circuit layers 141 and 142, and the second inner layer insulating layer ( It may include a second outer layer circuit layer 143 disposed under the 131, 132 and having a second pad (143a).

Here, the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers may have different thicknesses. For example, when the first inner layer circuit layers 121 and 122 have a complicated circuit pattern compared to the second inner layer circuit layers 141 and 142, the first and second inner layer insulating layers 111, 112, 131, and 132 are provided. In order to reduce the difference in thermal expansion coefficient therebetween, the second inner layer insulating layers 131 and 132 may have a thicker thickness than the first inner layer insulating layers 111 and 112.

The first inner layer insulating layers 111 and 112 may have the bend pattern 133. For example, as illustrated in the drawing, the bending pattern 133 may have a form of dimples unlike the unevenness or the drawing. As a result, when the first inner layer insulating layers 111 and 112 shrink by heating, the shrinking direction and the contracting force may be dispersed, thereby reducing the shrinkage of the first inner layer insulating layers 111 and 112.

In addition, the first inner layer circuit layers 121 and 122 may not be formed in the bending patterns 133 of the first inner layer insulating layers 111 and 112 so as to easily form the first inner layer circuit layers 121 and 122. It may be formed in a non-region, but the embodiment is not limited to this.

In the exemplary embodiment of the present invention, although the first inner layer insulating layers 111 and 112 include the bending patterns 133, the present invention is not limited thereto, and the predetermined patterns include the first and second inner layer circuit layers 121. It may be formed on at least one of the first and second inner layer insulating layers (111, 112, 131, 132) according to the design of the 122, 141, 142.

Therefore, as in the embodiment of the present invention, by forming a pattern that can reduce the shrinkage in the inner layer insulating layer, it is possible to more effectively improve the bending failure of the package substrate.

3 is a cross-sectional view of a package substrate according to a third embodiment of the present invention.

Here, in the third embodiment of the present invention has the same configuration as the first embodiment described above except for the warpage-proof filling structure. Therefore, the third embodiment of the present invention will be omitted for the sake of convenience of description, the same configuration will be given the same reference numerals.

Referring to FIG. 3, a package substrate according to an exemplary embodiment of the present invention may include a core layer 100, first inner circuit layers 121 and 122 disposed on the core layer 100, and a first inner circuit layer 121. 122) The first inner layer insulating layers 111 and 112 disposed on the upper portion, the first outer layer circuit layers 123 and the core disposed on the first inner layer insulating layers 111 and 112 and having the first pad 123a. The second inner layer circuit layers 141 and 142 disposed below the layer 100, the second inner layer insulating layers 131 and 132 disposed below the second inner layer circuit layers 141 and 142, and the second inner layer insulating layer ( It may include a second outer layer circuit layer 143 disposed under the 131, 132 and having a second pad (143a).

Here, the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers may have different thicknesses. For example, when the first inner layer circuit layers 121 and 122 have a complicated circuit pattern compared to the second inner layer circuit layers 141 and 142, the first and second inner layer insulating layers 111, 112, 131, and 132 are provided. In order to reduce the difference in thermal expansion coefficient therebetween, the second inner layer insulating layers 131 and 132 may have a thicker thickness than the first inner layer insulating layers 111 and 112.

The second inner layer insulating layers 131 and 132 may include a through hole 134 formed therein, and an anti-bending filling structure 135 may be disposed in the inner layer of the through hole 134. The anti-bending filling structure 135 may be formed of a material having a thermal expansion coefficient different from that of the first and second inner layer insulating layers 111, 112, 131, and 132. As a result, the anti-bending filling structure 135 may control the shrinkage ratio of the first and second inner layer insulating layers 111, 112, 131, and 132.

For example, when the first inner layer insulating layers 111 and 112 are greatly contracted compared to the second inner layer insulating layers 131 and 132, the anti-bending filling structure 135 may have the second inner layer insulating layers 131 and 132. Can be formed on. At this time, the anti-bending filling structure 135 is made of a material having a coefficient of thermal expansion larger than the insulating resin forming the second inner layer insulating layers (131, 132), thereby improving the shrinkage of the second inner layer insulating layers (131, 132) By having the same shrinkage as that of the first inner layer insulating layer, warpage of the package substrate can be prevented.

In the exemplary embodiment of the present invention, the bending preventing filling structure 135 is described and illustrated as being formed on the second inner insulation layers 131 and 132, but is not limited thereto. For example, the anti-bending filling structure 135 may be formed on the first inner insulation layers 111 and 112. At this time, the anti-bending filling structure 135 is made of a material having a coefficient of thermal expansion smaller than the insulating resin forming the first inner layer insulating layers (111, 112), thereby reducing the shrinkage of the first inner layer insulating layers (111, 112) By having the same shrinkage as those of the second inner layer insulating layers 131 and 132, warpage of the package substrate can be prevented. Alternatively, the anti-bending filling structure 135 may be provided on the first and second inner layer insulating layers 111, 112, 131, and 132, respectively. That is, the bending prevention filling structure 135 may be changed in material and position according to the design pattern structure of the first and second inner circuit layers 121. 122, 141, and 142.

The anti-bending filling structure 135 may be formed of a material having excellent heat or physical strength in order not to reduce durability of the first inner layer insulating layers 111 and 112 or the second inner layer insulating layers 131 and 132. For example, examples of the material used as the anti-bending filling structure 135 may be ceramic, ceramic, and metal powder.

Therefore, as in the embodiment of the present invention, by forming the anti-bending filling structure on at least one of the first and second inner layer insulating layer, it is possible to more efficiently improve the bending failure of the package substrate.

4 is a cross-sectional view of a package substrate according to a fourth embodiment of the present invention.

Here, the fourth embodiment of the present invention has the same configuration as the first embodiment described above except for the inner circuit layer and the inner insulation layer. Therefore, the fourth embodiment of the present invention will be omitted for convenience of description, and the same configuration will be given the same reference numerals.

Referring to FIG. 4, a package substrate according to an exemplary embodiment of the present invention may include a core layer 100, first inner circuit layers 121 and 122 disposed on the core layer 100, and a first inner circuit layer 121. 122) The first inner layer insulating layers 111 and 112 disposed on the upper portion, the first outer layer circuit layers 123 and the core disposed on the first inner layer insulating layers 111 and 112 and having the first pad 123a. The second inner layer circuit layers 141 and 142 disposed below the layer 100, the second inner layer insulating layers 131 and 132 disposed below the second inner layer circuit layers 141 and 142, and the second inner layer insulating layer ( It may include a second outer layer circuit layer 143 disposed under the 131, 132 and having a second pad (143a).

Here, the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132 may have the same thickness. In this case, the first inner layer circuit layers 121 and 122 and the second inner layer circuit layers 141 and 142 may have different thicknesses. For example, when the first inner layer circuit layers 121 and 122 have a complicated circuit pattern compared to the second inner layer circuit layers 141 and 142, the first inner layer circuit layers 121 and 122 and the second inner layer circuit layer ( 141 and 142 may have a thickness d4 of the second outer layer circuit layer 143 smaller than a thickness d3 of the first inner layer circuit layers 121 and 122 in order to reduce the difference in the amount of Cu remaining in the circuit layer. Can be. Accordingly, it is possible to reduce the difference in filling amount of the insulating resin between the first inner layer insulating layers 111 and 112 and the second inner layer insulating layers 131 and 132, thereby preventing warpage of the package substrate.

Therefore, as in the embodiment of the present invention, the thickness of the inner circuit layers disposed on the upper and lower portions based on the core layer may be controlled to prevent warpage of the package substrate.

Hereinafter, the effect of the package substrate according to the embodiment of the present invention will be described in more detail with reference to FIGS. 5 and 6.

Here, the package substrate to be compared includes four first inner layer circuit layers disposed on the core layer, one outer layer circuit layer, and four first inner layer insulating layers, and four layers disposed under the core layer. It was manufactured to include the second inner layer circuit layer of, the outer layer circuit layer of one layer and the second inner layer insulating layer of four layers. At this time, the first and second inner layer circuit layers had the same thickness and formed of Cu. In addition, the first and second inner layer insulating layers were formed of an epoxy resin containing silicon oxide. At this time, the first and second inner layer insulating layers were formed to have the same thickness, that is, a thickness of 30 mm.

On the other hand, the package substrate to be implemented is formed to have the same configuration as the package substrate to be compared except for the thickness of the second inner layer insulating layer. At this time, the thickness of the second inner layer insulating layer was formed to be 33mm.

5 is a graph comparing the amount of change in the degree of warpage of the package substrate according to the temperature change between the target and the target.

As shown in FIG. 5, the warpage change amount ΔH of the package substrate 210 to be compared was 73 μm, and the warpage degree change amount ΔH of the package substrate 220 to be implemented was 26 μm. That is, the generation of warpage of the package substrate can be reduced by controlling the thicknesses of the first and second inner layer insulating layers.

6 is a graph comparing the amount of change in the degree of warpage of the package according to the temperature change between the target and the target.

As shown in FIG. 6, after the semiconductor chip and the main board substrate were mounted on the package substrate of the implementation target and the comparison target, the variation in the degree of warpage (ΔH) of the package was compared. At this time, the warpage degree change amount ΔH of the package 310 to be compared was 474 μm, and the warpage degree change amount ΔH of the package 320 to be implemented was 308 μm. That is, the warpage of the package can be reduced by controlling the thicknesses of the first and second inner layer insulating layers.

Therefore, as in the embodiment of the present invention, the control of the thickness of the inner insulating layers disposed on the upper and lower portions can reduce the occurrence of warpage of the package substrate by heating such as a soldering process or a molding process, thereby ensuring the reliability of the package. Mass production was improved.

1 is a cross-sectional view of a package substrate according to a first embodiment of the present invention.

2 is a cross-sectional view of a package substrate according to a second embodiment of the present invention.

3 is a cross-sectional view of a package substrate according to a third embodiment of the present invention.

4 is a cross-sectional view of a package substrate according to a fourth embodiment of the present invention.

5 is a graph comparing the amount of change in the degree of warpage of the package substrate according to the temperature change between the target and the target.

6 is a graph comparing the amount of change in the degree of warpage of the package according to the temperature change between the target and the target.

<Explanation of symbols for the main parts of the drawings>

100: core layer

111, 112: first inner layer insulating layer

121, 122: first inner layer circuit layer

131 and 132: second inner layer insulating layer

141, 142: second inner layer circuit layer

123: first outer circuit layer

143: second outer circuit layer

150: solder resist pattern

133: bending pattern

135: warpage-filled structure

Claims (12)

Core layer; A first inner layer circuit layer disposed on the core layer; A first inner layer insulating layer disposed on the first inner layer circuit layer; A first outer layer circuit layer disposed on the first inner layer insulating layer and having a first pad; A second inner layer circuit layer disposed below the core layer; A second inner layer insulating layer disposed below the second inner layer circuit layer and having a thickness different from that of the first inner layer insulating layer; And A second outer circuit layer disposed below the second inner insulation layer and having a second pad; Including; At least one of the first and second inner layer insulating layers has a bent pattern. The method of claim 1, The second inner layer insulating layer has a larger thickness than the first inner layer insulating layer. The method of claim 1, The first inner layer insulating layer includes a single insulating layer, and the second inner layer insulating layer includes at least two or more multilayer insulating layers stacked. The method of claim 3, wherein At least two insulating layers of the multilayer insulating layer are made of a material having a different coefficient of thermal expansion. delete The method of claim 1. A package substrate comprising a bending prevention filling structure filled in the through-hole formed in at least one of the first and second inner layer insulating layer. The method of claim 6, The bending preventing filling structure is formed of a material having a thermal expansion coefficient different from that of the first and second inner layer insulating layers. The method of claim 1, The first pad is electrically connected to the semiconductor chip, and the second pad is electrically connected to the main board substrate. Core layer; A first inner layer circuit layer disposed on the core layer; A first inner layer insulating layer disposed on the first inner layer circuit layer; A first outer layer circuit layer disposed on the first inner layer insulating layer and having a first pad; A second inner circuit layer disposed below the core layer and having a thickness different from that of the first inner circuit layer; A second inner layer insulating layer disposed below the second inner layer circuit layer; And A second outer circuit layer disposed below the second inner insulation layer and having a second pad; Including; At least one of the first and second inner layer insulating layers has a bent pattern. The method of claim 9, The second inner circuit layer has a smaller thickness than the first inner circuit layer. The method of claim 9, The first and second inner layer insulating layers have the same thickness as each other. The method of claim 9, The first pad is electrically connected to the semiconductor chip, and the second pad is electrically connected to the main board substrate.

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