KR101064219B1 - Pram with vertical channel, pram array using the same and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PRAM device, a PRAM array, and a method of manufacturing the same, wherein the semiconductor substrate is etched to form trenches, and sidewall gates are formed on sidewalls of the trench to have a vertical channel structure. By minimizing the area, high integration is possible, and the lower electrode, the phase change material layer, and the upper electrode are sequentially stacked and filled between sidewall gates formed on both side walls of the trench, so that the phase change material layer is easily aligned to a desired thickness by self alignment. There is an effect that can be formed.

Description

A PRAM element having a vertical channel structure, a PRAM array using the same, and a method of manufacturing the same {PRAM WITH VERTICAL CHANNEL, PRAM ARRAY USING THE SAME AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, a memory array, and a method of manufacturing the same, and more particularly, to a phase-change random access memory (PRAM) device having a vertical channel structure, a PRAM array using the same, and a method of manufacturing the same.

With the development of removable media and multimedia devices, the demand for high capacity low power memory devices has exploded in recent decades. For nonvolatile memories that can store data without external periodic signals, flash memory using conductive floating gates has led the entire nonvolatile memory market.

However, due to the reliability problem at the small scale of flash memory, researches on memory having different operating principles have been conducted by academics and industry. In other words, MRAMs using magnetic materials, PRAMs using phase change materials, RRAMs using resistive changes, and various memories replacing conventional floating gate flash memories have been developed for commercialization. Among them, PRAM using a phase conversion material has a spotlight as a next-generation nonvolatile memory because of its simple cell structure and relatively fast read / write operation compared to other nonvolatile memories.

Basically, the PRAM has a structure similar to that of the 1T (transistor) 1C (capacitor) structure of the DRAM, as shown in FIG. However, the information storage area is different from a chalcogenide material such as Ge ₂ Sb ₂ Te ₅ (GST), that is, a phase change material (PCM).

The operation principle of the PRAM is that the phase change material has a crystalline state or an amorphous state under predetermined conditions, and the difference in resistance depends on each state. For example, as shown in FIG. 2, after a current is applied to the GST material through a switching element for a predetermined time, heat is supplied to the vicinity of the melting point (Tm: about 610 ° C.) of the GST material for a short time (t1: 1 to 10 ns). When rapidly cooled for 1 ns, the GST material becomes an amorphous state with high resistance (L1, data '1' stored as a reset state or a program state), while near the crystallization temperature (Tc: about 450 ° C.) of the GST material. After a long time (t2: 30-50 ns) of heat is slowly cooled, the GST material becomes a crystalline state with a relatively low resistance (data '0' is stored as a set state or an erased state). Therefore, in the read operation, the data '1' or '0' is sensed using the voltage difference according to the current flowing through the GST material which is the phase change material.

In this case, a switching element for selecting a specific cell is used in the process of storing and reading data. Although PRAM using a silicon diode as a switching element has been introduced, when a large number of cells are integrated in an array form, power consumption due to the reverse leakage current of the diode becomes a problem. Should be used.

However, in the conventional PRAM, a switching element is formed between the ground and the bit line in order to apply a current to the phase change material layer, as shown in FIG. 3, in a planar type on a substrate. come.

In addition, due to the characteristics of the phase change material, it is easy to switch from the amorphous state (program state), which is a relatively large resistance, to the crystalline state (ease state), but the reverse is difficult, so that the temperature of the phase change material near the melting point of the phase change material is increased. In the conventional PRAM, as shown in FIG. 3, the lower electrodes 5a and 5b in contact with the phase change material layer have a relatively long length and a small cross-sectional area as compared with the upper electrodes 7a and 7b. Excitation has to be configured, and accordingly, there is a problem that it is difficult to deposit a phase change material layer by self alignment as well as an increase in complexity of the process.

In FIG. 3, reference numerals 7a and 7b may be used as contact lines to the common source / drain 3 formed on the semiconductor substrate 1 using reference numerals 9a as the upper electrode and reference numeral 9 as the common ground line. On the contrary, reference numeral 9 may serve as a bit line, and reference numerals 7a and 7b may operate as respective ground lines. Both sides of the common source / drain 3 are connected to the first source / drain 2a and the second source / drain 2b through a horizontal channel of each switching element controlled by each word line 4a and 4b. Subsequently, each of the phase change material layers is electrically connected to each of the lower electrodes 5a and 5b formed of a conductive plug on the interlayer insulating film 8. The phase change material layer of the left cell of FIG. 3 shows a state of a crystalline state (ease state 6a), and the phase change material layer of the right cell of FIG. 3 shows a part of an amorphous state (program state, 6b) is shown.

Accordingly, an object of the present invention is to provide a highly integrated PRAM device and a PRAM array using the same by minimizing the area consumed by the switching device by vertically implementing a channel of the switching device for supplying current to the phase change material layer. .

Another object of the present invention is to provide a method of manufacturing a PRAM array, which can easily form a phase change material layer by self alignment using a sidewall process.

In order to achieve the above object, the PRAM device according to the present invention comprises a switching element electrically connected to the first line, a lower electrode electrically connected to one terminal of the switching element, and a phase change material layer formed on the lower electrode; And a top electrode formed on the phase change material layer and electrically connected to a second line, wherein the switching element is formed on a portion of a trench bottom and a sidewall of the trench formed by etching a semiconductor substrate. And a sidewall gate formed with a gate insulating film interposed therebetween, wherein the trench is formed by stacking the bottom electrode, the phase change material layer, and the top electrode from a bottom with a separation insulating film interposed therebetween on the sidewall gate. ,

Two switching elements each having a vertical channel on both sidewalls of the semiconductor substrate; And a storage node formed by stacking the lower electrode, the phase change material layer, and the upper electrode in order from the bottom of the trench with a separation insulating layer interposed therebetween on the two switching elements.

In addition, the PRAM array according to the present invention includes two or more trenches formed by etching a predetermined distance from the semiconductor substrate; Two sidewall gates spaced apart from each other with a gate insulating film on a bottom and both sidewalls of each trench; A plurality of source / drain regions formed of an impurity doping layer on an upper portion of the semiconductor substrate and on a bottom of the trench positioned on both sidewall gates; And storage nodes stacked and filled from the bottom in the order of the lower electrode, the phase change material layer, and the upper electrode with the isolation insulating layer interposed therebetween on each of the trenches.

In addition, a method of manufacturing a PRAM array according to the present invention may include: a first step of etching a semiconductor substrate to form two or more trenches having a predetermined width and depth spaced apart from each other by a predetermined distance; Forming a gate insulating film on the substrate on which the trenches are formed; Depositing gate material over the substrate and etching anisotropically to form sidewall gates on both sidewalls of each trench; A fourth step of forming a separation insulating film on each sidewall gate through a thermal oxidation process; A fifth step of forming a source / drain on the substrate and the bottom of each trench through an ion implantation process; A sixth step of removing the gate insulating film exposed to both sides of each sidewall gate through an insulating film etching process; And a seventh step of sequentially filling and filling the lower electrode, the phase change material layer, and the upper electrode from the bottom of each trench exposed by the insulating film etching process to form a plurality of storage nodes.

Etching the semiconductor substrate to form two or more trenches having a predetermined width and depth spaced apart from each other by a predetermined distance; Forming a gate insulating film on the substrate on which the trenches are formed; Depositing gate material over the substrate and etching anisotropically to form sidewall gates on both sidewalls of each trench; Forming a source / drain on an upper portion of the substrate and a bottom of each trench through an ion implantation process; A fifth step of forming a separation insulating film on each sidewall gate through a thermal oxidation process; A sixth step of removing the gate insulating film exposed to both sides of each sidewall gate through an insulating film etching process; And a seventh step of sequentially filling and filling the lower electrode, the phase change material layer, and the upper electrode from the bottom of each trench exposed by the insulating film etching process to form a plurality of storage nodes.

The PRAM device and the PRAM array according to the present invention form a trench by etching a semiconductor substrate, and form a sidewall gate on the sidewall of the trench to have a vertical channel structure, thereby minimizing the area consumed by the switching element, thereby enabling high integration. Of course, unlike the prior art there is an effect that does not need to be bound by the shape of the lower electrode. In addition, compared with the method of using a diode device as a switching device, it is not affected by the integration limit due to diode reverse current.

In the PRAM array manufacturing method according to the present invention, the upper sidewall gate is formed with a thick oxide film during the thermal oxidation process, and the lower electrode, the phase change material layer, and the upper electrode are sequentially disposed between sidewall gates formed on both side walls of the trench. By sequentially filling and filling, the phase change material layer can be easily formed to a desired thickness by self alignment.

1 is an equivalent circuit diagram of a PRAM element.
FIG. 2 is a graph illustrating a crystal state according to a temperature and a time at which a phase change material layer of a PRAM device is heated.
3 is a cross-sectional view illustrating an example of a conventional PRAM device and an array structure.
4 is a cross-sectional view illustrating an example of a PRAM device and an array structure according to the present invention.
5 to 13 are cross-sectional views illustrating an example of a method of manufacturing a PRAM device and an array according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. 4 to 13, some components are exaggerated, and unnecessary parts are omitted to emphasize the structural features of the embodiments according to the present invention. In particular, Figures 4 to 13 are cross-sectional views seen from one side, it should be understood that the view seen from the other side can be a structure in which the PRAM device and the array are operated utilizing the features of the present invention.

Embodiment of PRAM Device Structure

First, a PRAM device according to the present invention basically includes a switching element electrically connected to a first line, a lower electrode electrically connected to one terminal of the switching element, and a phase change formed on the lower electrode as shown in FIG. 1. In the PRAM device including a material layer and an upper electrode formed on the phase change material layer and electrically connected to a second line, the switching device is controlled by a word line, as shown in FIG. 4. ) And a sidewall gate (32a, 32b, 32c or 32d) formed with a portion of the trench bottom formed by etching) and the gate insulating film 22 on one sidewall of the trench, thereby having a vertical channel. do.

Here, first and second source / drain regions (eg, 52b and 54a) are formed on the upper side of the semiconductor substrate and the trench bottom positioned on both sidewall gates as impurity doping layers, respectively, and the first source / drain regions ( 52b is electrically connected to the first line (not shown) through the conductive plug 84, and the second source / drain region 54a is electrically connected to the lower electrode 62a.

In the trench, the lower electrode (eg, 62a), the phase change material layer (eg, 70a), and the bottom electrode are disposed from the bottom of the sidewall gate 32a, 32b, 32c, or 32d with the isolation insulating film 40 therebetween. The upper electrodes (eg, 84a) are stacked and filled in order.

In FIG. 4, two sidewall gates are formed in each trench (32a and 32b, 32c and 32d), and the lower electrodes 62a and 62b / the phase change material layers 70a and 70b and the upper electrode (between the two sidewall gates). 84a and 84b), and filling the trenches is illustrated, but a PRAM device controlled by one sidewall gate formed on one sidewall of the trench may be implemented.

The first and second lines may be bit lines and ground lines, respectively, as shown in FIG. 1, but may be interchanged with each other.

As described above, the gate of the switching element for supplying current to the phase change material layers 70a and 70b is formed as a sidewall gate, so that the vertical channel structure is minimized, thereby minimizing the area consumed by the switching element.

In addition, since the phase change can be directly converted to heat generated in the phase change material layer, there is no need to be limited to the shape of the lower electrode. That is, in the conventional PRAM device as shown in FIG. 3, since the lower electrodes 5a and 5b need to supply heat sufficient to change the state of the phase change material layer 6a (especially when changing from the crystalline state to the amorphous state), In order for the lower electrodes 5a and 5b to have a predetermined resistance, there have been limitations in that they have a certain length and have a small cross-sectional area.

4 is a cross-sectional view of a PRAM device structure according to the present embodiment, in contrast to FIG. 3 showing a conventional PRAM device, and includes storage nodes 62a, 70a, and 84a (62b) including a phase change material layer for each trench. , 70b and 84b, and two switching elements having vertical channels on both sidewalls of the trench are connected in parallel to each storage node.

Each of the switching elements includes an impurity doped layer 52b formed on the substrate between trenches as a first source / drain region, an impurity doped layer 54a and 54b formed in a semiconductor at the bottom of the trench as a second source / drain region, The semiconductor pillar 12 between trenches is set to each channel area. Here, the semiconductor pillar 12 is not shown in the drawing, but refers to the semiconductor substrate 10 is etched in a columnar shape so as to form the respective trenches and to be filled with an insulating film pillar to define the channel region of each switching element.

The impurity doping layer 52b formed on the substrate is connected to the bit line or the ground line through the conductive plug 84 of the interlayer insulating film 90, and the upper electrodes 84a and 84b of each storage node are interlayer insulating films ( It is connected to the ground line or the bit line through the conductive plugs 82a and 82b of 90, and the sidewall gates 32a, 32b, 32c, and 32d of each switching element are connected to each word line.

Therefore, in the PRAM device according to the present exemplary embodiment, the lower electrodes 62a and 62b are formed from the bottom of the trench with the isolation insulating film 40 interposed between the two sidewall gates 32a, 32b, 32c and 32d for each trench. Since the structure has storage nodes stacked in the order of the phase change material layers 70a and 70b and the upper electrodes 84a and 84b, the thickness of the phase change material layers 70a and 70b may be increased depending on the trench depth. Therefore, it is possible to convert the phase into its own heat.

In FIG. 4, the left cell shows a state in which the phase change material layer is in a crystalline state (ease state, 70a), and the right cell shows a state in which the phase change material layer is converted to an amorphous state (program state, 70b).

Embodiment of PRAM Array

Next, an embodiment of a PRAM array using a PRAM element according to the embodiment of the above-described PRAM element structure will be described.

Basically, as illustrated in FIGS. 4 to 13, two or more trenches 11 formed by etching and being spaced apart from the semiconductor substrate 10 by a predetermined distance; Two sidewall gates (32a, 32b) (32c, 32d) formed with a gate insulating film (22) on the bottom and both sidewalls and spaced apart from each other in each trench; A plurality of source / drain regions formed as an impurity doping layer on upper portions of the semiconductor substrates 52a, 52b, and 52c and on the trench bottoms 54a and 54b, respectively located on both sidewall gates; And the lower electrodes 62a and 62b, the phase change material layers 70a and 70b, and the upper electrodes 84a and 84b from the bottom of each trench, with the isolation insulating film 40 interposed therebetween on each sidewall gate. And consists of filled storage nodes.

 The source / drain regions 52a, 52b, and 52c formed on the semiconductor substrate may be electrically connected to respective bit lines (not shown) through the conductive plugs 84 of the interlayer insulating layer 90, respectively. The source / drain regions 54a and 54b formed at the bottom of the trench are electrically connected to the lower electrodes 62a and 62b of each storage node, and the upper electrodes 84a and 84b of each storage node are interlayer insulating films ( 90 is electrically connected to a ground line (not shown) through conductive plugs 82a and 82b, and the sidewall gates 32a, 32b, 32c, and 32d are electrically connected to respective word lines (not shown). do.

Of course, the source / drain regions 52a, 52b, and 52c formed on the semiconductor substrate may be electrically connected to a ground line instead of a bit line. In this case, the upper electrodes 84a and 84b of each storage node may be ground lines. Instead it is electrically connected to the bitline.

[Example of Manufacturing Method of PRAM Array]

A method of manufacturing a PRAM array according to an embodiment of the PRAM array will be described with reference to FIGS. 5 to 13.

First, as shown in FIG. 5, the semiconductor substrate 10 is etched to form two or more trenches 11 having a predetermined width and depth spaced apart from each other by a predetermined distance (first step). Here, the width of the trench 11 is determined by the width of the sidewall gate and storage node to be formed later, the depth of the trench 11 may be determined by the vertical channel length and the thickness of the phase change material layer.

Of course, the semiconductor substrate 10 is etched in a direction perpendicular to the direction of the trench 11 to define an active region of a switching element to be formed later before the first step, thereby forming a field trench and filling an insulating layer. In this step, it is preferable that the insulating film filled in the field trenches can be removed together when the trench 11 is formed. In this case, reference numeral 12 in FIG. 5 has a semiconductor pillar shape.

Next, as shown in FIG. 6, a gate insulating film 20 is formed on the substrate on which the trenches 11 are formed (second step). Here, the gate insulating film 20 may be formed of an oxide film through a conventional thermal oxide film process.

Subsequently, as shown in FIG. 7, the gate material 30 is deposited on the entire surface of the substrate, and as shown in FIG. 8, anisotropic etching is performed to form sidewall gates 32a and 32b on both sidewalls of each of the trenches 11. (Third step). Here, the gate material 30 may be a silicon-based material doped with impurities as usual, and sidewalls formed on both sidewalls of each of the trenches 11 by adjusting etching conditions of the gate material 30. The height, width and inclination of the gates 32a and 32b may be adjusted.

Thereafter, as shown in FIG. 9, a separation insulating layer 40 is formed on the sidewall gates 32a and 32b through a thermal oxidation process (fourth step). At this time, by using a thicker oxide film formed on the sidewall gate than other portions, it is possible to remove the gate insulating film exposed outside each sidewall gate 32a, 32b.

Next, as shown in FIG. 10, the source / drains 52a, 52b, and 54 are formed on the top of the substrate and the bottom of each trench through an ion implantation process (Fifth Step).

However, it is preferable that the ion implantation process in this step is performed immediately after the third step, that is, immediately after forming the sidewall gates 32a and 32b by changing the order of the processes. In this way, the conductivity of the sidewall gates 32a and 32b formed of a silicon-based material may be increased along with the formation of the source / drain 52a, 52b and 54 by impurity ion implantation, and then the isolation insulating layer 40 is formed in the fourth step. In the thermal oxidation process for diffusing and annealing the ion implanted in the previous step is effective.

Thereafter, as shown in FIG. 11, the gate insulating layer 20 exposed to both sidewall gates is removed through an insulating layer etching process (sixth step). At this time, as described above, the oxide insulating film is formed thicker on the sidewall gate in the above-described process, so that even if the gate insulating film 20 exposed to both sides of the sidewall gate is removed by the insulating film etching process of this step, the isolation insulating film ( 40) remains.

Next, as shown in FIG. 12, a plurality of storage nodes are sequentially stacked from the bottom of each of the trenches exposed by the insulating film etching process in order from the bottom electrode 62, the phase change material layer 70, and the top electrode 64. Form them (step 7).

The lower electrode 62, the phase change material layer 70, and the upper electrode 64 may be formed of a known material.

In addition, the phase change material layer 70 can be easily formed by self-alignment because the phase change material layer 70 fills between sidewall gates 32a, 32b, 32c, and 32d on both sides, and the thickness thereof also controls process conditions. Can be implemented to have any size you want.

Thereafter, as shown in FIG. 13, an interlayer insulating film 90 is deposited on the entire surface of the substrate, and a plurality of layers for electrical connection with the source / drains 52a and 52b formed on the substrate and the upper electrodes 64 of the respective storage nodes are formed. Forming two contact holes; And forming conductive plugs 82a, 82b, and 84 in each of the contact holes, thereby manufacturing a PRAM array.

Other processes may follow a conventional memory array fabrication process, and further description thereof will be omitted.

10: semiconductor substrate 22: gate insulating film
32a, 32b, 32c, 32d: sidewall gate 40: isolation insulating film
52b: first source / drain 54a, 54b: second source / drain
62a and 62b: lower electrode 70a and 70b: phase change material layer
82a, 82b, 84: conductive plug 84a, 84b: upper electrode
90: interlayer insulating film

Claims (10)

A switching element electrically connected to a first line, a lower electrode electrically connected to one terminal of the switching element, a phase change material layer formed on the lower electrode, and formed on the phase change material layer, In a PRAM device comprising an electrically connected upper electrode,
The switching element has a portion of a trench bottom formed by etching a semiconductor substrate and a sidewall gate formed on one sidewall of the trench with a gate insulating film interposed therebetween,
And forming a trench in the trench in the trench, the lower electrode, the phase change material layer, and the upper electrode stacked from a bottom to an isolation insulating layer on the sidewall gate.
A switching element electrically connected to a first line, a lower electrode electrically connected to one terminal of the switching element, a phase change material layer formed on the lower electrode, and formed on the phase change material layer, In a PRAM device comprising an electrically connected upper electrode,
The switching element has a portion of a trench bottom formed by etching a semiconductor substrate and a sidewall gate formed on one sidewall of the trench with a gate insulating film interposed therebetween,
First and second source / drain regions are formed on the semiconductor substrate and the trench bottom positioned at both sides of the sidewall gate, respectively, as an impurity doping layer.
The first source / drain region is electrically connected to the first line,
And the second source / drain region is electrically connected to the lower electrode.
The method of claim 2,
And forming a trench in the trench in the trench, the lower electrode, the phase change material layer, and the upper electrode stacked from a bottom to an isolation insulating layer on the sidewall gate.
Two switching elements each having a vertical channel on both sidewalls of the semiconductor substrate; And
And a storage node formed by stacking the lower electrode, the phase change material layer, and the upper electrode in order from the bottom of the trench with a separation insulating layer interposed therebetween on the two switching devices.
Two or more trenches spaced apart from the semiconductor substrate by a predetermined distance and etched;
Two sidewall gates spaced apart from each other with a gate insulating film on a bottom and both sidewalls of each trench;
A plurality of source / drain regions formed of an impurity doping layer on an upper portion of the semiconductor substrate and on a bottom of the trench positioned on both sidewall gates; And
And each of the trenches comprises storage nodes stacked and filled from the bottom in order from the bottom to the bottom electrode, the phase change material layer, and the top electrode with a separation insulating layer on each sidewall gate.
The method of claim 5, wherein
Source / drain regions formed on the semiconductor substrate are electrically connected to each bit line,
Source / drain regions formed at the bottom of each trench are electrically connected to the lower electrode of each storage node,
The upper electrode of each storage node is electrically connected to a ground line,
Each sidewall gate is electrically connected to a respective wordline.
The method of claim 5, wherein
Source / drain regions formed on the semiconductor substrate are electrically connected to a ground line,
Source / drain regions formed at the bottom of each trench are electrically connected to the lower electrode of each storage node,
The upper electrode of each storage node is electrically connected to each bit line,
Each sidewall gate is electrically connected to a respective wordline.
Etching the semiconductor substrate to form two or more trenches having a predetermined width and depth spaced apart from each other by a predetermined distance;
Forming a gate insulating film on the substrate on which the trenches are formed;
Depositing gate material over the substrate and etching anisotropically to form sidewall gates on both sidewalls of each trench;
A fourth step of forming a separation insulating film on each sidewall gate through a thermal oxidation process;
A fifth step of forming a source / drain on the substrate and the bottom of each trench through an ion implantation process;
A sixth step of removing the gate insulating film exposed to both sides of each sidewall gate through an insulating film etching process; And
And a seventh step of sequentially filling and filling the lower electrode, the phase change material layer, and the upper electrode in order from the bottom of each trench exposed by the insulating film etching process to form a plurality of storage nodes. .
Etching the semiconductor substrate to form two or more trenches having a predetermined width and depth spaced apart from each other by a predetermined distance;
Forming a gate insulating film on the substrate on which the trenches are formed;
Depositing gate material over the substrate and etching anisotropically to form sidewall gates on both sidewalls of each trench;
Forming a source / drain on an upper portion of the substrate and a bottom of each trench through an ion implantation process;
A fifth step of forming a separation insulating film on each sidewall gate through a thermal oxidation process;
A sixth step of removing the gate insulating film exposed to both sides of each sidewall gate through an insulating film etching process; And
And a seventh step of sequentially filling and filling the lower electrode, the phase change material layer, and the upper electrode in order from the bottom of each trench exposed by the insulating film etching process to form a plurality of storage nodes. .
The method according to claim 8 or 9,
Depositing an interlayer insulating film on the entire surface of the substrate, and forming a plurality of contact holes for electrical connection with a source / drain formed on the substrate and an upper electrode of each storage node; And
And forming a conductive plug in each of the contact holes.

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