KR101049877B1 - LDMOS transistors and methods of manufacturing the same - Google Patents

LDMOS transistors and methods of manufacturing the same Download PDF

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Publication number
KR101049877B1
KR101049877B1 KR1020080100202A KR20080100202A KR101049877B1 KR 101049877 B1 KR101049877 B1 KR 101049877B1 KR 1020080100202 A KR1020080100202 A KR 1020080100202A KR 20080100202 A KR20080100202 A KR 20080100202A KR 101049877 B1 KR101049877 B1 KR 101049877B1
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South Korea
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region
type
extended drain
drain region
body region
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KR1020080100202A
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Korean (ko)
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KR20100041159A (en
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강찬희
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

 The present invention discloses an LDMOS transistor and a method of manufacturing the same. The LDMOS transistor includes a first type drift region, a second type body region formed in the first type drift region, and a first type extended drain spaced a predetermined distance from the second type body region in the first type drift region. A region, a source region formed in the second type body region, a drain region formed in the first type extended drain region, and a P well region formed on both sides of the extended drain region. Therefore, it has the effect of raising the breakdown voltage and lowering the on resistance.

LDMOS, Breakdown Voltage, On-Resistance

Description

LMDMOS transistor and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an LDMOS transistor and a method of manufacturing the same.

Ideally, the power semiconductor device is preferably a device capable of operating at a high voltage close to the theoretical breakdown voltage of the semiconductor.

Accordingly, when an external system using high voltage is controlled by an integrated circuit, the integrated circuit needs an element for high voltage control therein, and such an element requires a structure having a high breakdown voltage. do.

That is, in the drain or source of the transistor to which the high voltage is integrated, the punch-through voltage between the drain and the source and the semiconductor substrate and the breakdown voltage between the drain and the source and the well or the substrate should be greater than the high voltage. .

Among high voltage semiconductor devices, LDMOS (lateral diffused MOS), which is a high voltage MOS, has a structure suitable for high voltage because the channel region and the drain electrode are separated by a drift region and controlled by the gate electrode.

1 is a cross-sectional view showing an example of the structure of a conventional LDMOS transistor.

As shown in FIG. 1, the LDMOS transistor has a LOCOS 130 in the drift region to mitigate the electric field concentrated at the gate edge to improve the drain-source breakdown voltage BVdss. ).

While the LOCOS 130 is effective in terms of improving breakdown voltage (BVdss), the current flow path is bypassed to the lower part of the LOCOS 130, which is disadvantageous in terms of the resistance Rdson between the drain-source and the non-LOCOS applied LDMOS.

In addition, there is a disadvantage in that the electric field density increases intensively under the gate electrode.

However, when the drift concentration is increased to improve the resistance Rdson, the breakdown voltage BVdss is relatively decreased. That is, the breakdown voltage BVdss and the resistance Rdson show a trade-off.

Therefore, there is a constraint to improve only the resistance Rdson while maintaining the breakdown voltage BVdss level.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an LDMOS transistor having a high breakdown voltage and a low on-resistance, and a method of manufacturing the same.

The LDMOS transistor of the present invention for achieving the above object is constant with the first type drift region, the second type body region formed in the first type drift region, and the second type body region in the first type drift region. A first type extended drain region spaced apart from each other, a source region formed in the second type body region, a drain region formed in the first type extended drain region, and a P well region formed on both sides of the extended drain region. It is characterized by including.

 According to another aspect of the present invention, there is provided a method of manufacturing an LDMOS transistor, including forming a first type drift region on a semiconductor substrate, forming a second type body region in the first type drift region, and Forming a first type extended drain region spaced a predetermined distance from the second type body region in a first type drift region, forming a P-well region on both sides of the extended drain region, and And implanting an impurity into the type body region to form a source region, and implanting an impurity into the first type extended drain region to form a drain region.

The LDMOS transistor and its manufacturing method according to the present invention have the effect of increasing the breakdown voltage and lowering the on-resistance by forming the tilt ion implantation P well region and the extended drain region.

Hereinafter, an embodiment of an LDMOS transistor according to the present invention will be described with reference to the accompanying drawings.

2 shows a cross-sectional view of an LDMOS transistor of the present invention.

As shown in FIG. 2, a high concentration of N + layer in the P-type epitaxial layer 200 to prevent punch-through between the P-body region 260 and the P-type epitaxial layer 200 ( 220 is formed.

An N-drift region 240 and a P-body region 260 are formed on the N + layer 220 to form an active region.

A low concentration P well region 290 is formed to mitigate the electric field concentrated on both sides of the extended drain region 280 in the N-drift region 240, and the drain region 285 is formed in the extended drain region 280. ) Is formed.

A source region 265 is formed in the P-body region 260, and a P + type source contact region (not shown) is formed adjacent to the source region 265.

The channel region is the surface of the P-body region 260 between the source region 265 and the N-drift region 240.

The LOCOS 300 is formed on the N-drift region 240, and the gate insulating layer 320 is formed on the substrate surface except for the LOCOS 300.

The gate electrode 340 is formed on the LOCOS 300 between the P-body region 260 and the drain region 280.

Here, the P-body region 260 forms a P well region by implanting impurity ions, and the extended drain region 280 is formed by implanting an N well region deeper than conventionally, thereby draining from the source region 265. Prevents longer current paths to region 285.

Hereinafter, an embodiment of a method of manufacturing an LDMOS transistor according to the present invention will be described with reference to the accompanying drawings.

3A to 3E are cross-sectional views illustrating a manufacturing process of the LDMOS transistor of the present invention.

As shown in FIG. 3A, a high concentration N + layer 220 is formed on the P-type epitaxial layer 200, and an N-drift region 240 is formed on the N + layer 220.

As shown in FIG. 3B, a P well region is formed by implanting impurity ions into the N-drift region 240 to form a P-body region 260.

As shown in FIG. 3C, the LOCOS 300 is formed on the upper surface of the N-drift region 240 at a predetermined distance from the P-body region 260.

delete

As shown in FIG. 3D, an N well region is formed in the N-drift region 240 at a predetermined distance from the P-body region 260 to form an extended drain region 280. Although not shown, P-well regions 290 are formed on both sides of the extended drain region 280 for the purpose of relaxing the electric field by tilting ion implantation using a mask.

As shown in FIG. 3E, the source region 265 is formed by implanting impurities into the P-body region 260, and the N + type drain region 285 is formed by implanting impurity ions into the extended drain region. . The gate electrode 340 is formed on the semiconductor substrate through the gate insulating layer 320.

As described above, the present invention forms a P well region by tilt ion implantation using an N-well mask, thereby alleviating electric field distribution concentrated under the gate electrode, and forming an N well region to form an extended drain region. In addition, the on-resistance can be lowered by dispersing the current flow path without increasing the length of the drift region.

1 is a cross-sectional view of a general LDMOS transistor.

2 is a cross-sectional view of an LDMOS transistor of the present invention.

3A-3E are process cross-sectional views for manufacturing the LDMOS transistor of the present invention.

Claims (5)

First type drift region 240; A second type body region 260 formed in the first type drift region 240; A first type extended drain region 280 spaced apart from the second type body region 260 by a predetermined distance in the first type drift region 240; A source region 265 formed in the second type body region 260; A drain region 285 formed in the first type extended drain region 280; And P well regions 290 formed on both sides of the extended drain region 280; LDMOS transistor comprising a. The method of claim 1, And the second type body region (260) and the first type extended drain region (280) have the same depth, so that a current path is formed therebetween. Forming a first type drift region 240 on the semiconductor substrate; Forming a second type body region (260) in the first type drift region (240); Forming a first type extended drain region 280 spaced apart from the second type body region 260 in the first type drift region 240 by a predetermined distance; Forming P-well regions 290 on both sides of the extended drain region 280; Implanting impurities into the second type body region 260 to form a source region 265; And Implanting impurities into the first type extended drain region 280 to form a drain region 285; LDMOS transistor manufacturing method comprising a. The method of claim 3, wherein And the P well region (290) is formed by tilt ion implantation. The method of claim 3, wherein And the second type body region (260) and the first type extended drain region (280) have the same depth to form a current path therebetween.
KR1020080100202A 2008-10-13 2008-10-13 LDMOS transistors and methods of manufacturing the same KR101049877B1 (en)

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KR101049877B1 true KR101049877B1 (en) 2011-07-19

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980074299A (en) * 1997-03-24 1998-11-05 윤종용 LDMOS transistor (a lateral double-diffused MSO) transistor device and manufacturing method thereof
KR20060079370A (en) * 2004-12-30 2006-07-06 동부일렉트로닉스 주식회사 Lateral dmos transistor having uniform channel concentration distribution
KR100840667B1 (en) 2007-06-26 2008-06-24 주식회사 동부하이텍 Lateral dmos device and fabrication method therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980074299A (en) * 1997-03-24 1998-11-05 윤종용 LDMOS transistor (a lateral double-diffused MSO) transistor device and manufacturing method thereof
KR20060079370A (en) * 2004-12-30 2006-07-06 동부일렉트로닉스 주식회사 Lateral dmos transistor having uniform channel concentration distribution
KR100840667B1 (en) 2007-06-26 2008-06-24 주식회사 동부하이텍 Lateral dmos device and fabrication method therefor

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