KR101048351B1 - How Magnetic Memory Works - Google Patents

Abstract

According to the present invention, a plurality of magnetization inverting elements arranged in rows and columns, a bit line connecting lower portions of the magnetization inversion elements formed in the column direction and arranged in a column direction, are formed on the plurality of magnetization inversion elements. The present invention relates to a method of operating a magnetic memory in which a problem does not occur when driving a magnetic memory having bit lines connecting the magnetizing inverting elements arranged in a row direction. The recording of information according to the present invention is performed by applying a current to the magnetizing inverting element through the bit line and the word line and inverting the magnetization of the magnetizing inverting element by electron injection by a spin-transfer torque (STT) phenomenon. The information is erased by inverting the magnetization of the magnetization inversion element by a magnetic field applied from the outside of the magnetization inversion element.

Description

Method for operating magnetic memory {Method for operating magnetic device}

The present invention relates to a method of operating a magnetic memory, and more particularly, to a method of driving a magnetic memory using a diode as a switching element.

Flash memory has problems such as deterioration of cell characteristics due to reduction in coupling ratio due to interference between adjacent cells as cell size decreases, and cell reliability deterioration due to decrease of the number of electrons in the floating gate. It is becoming. In particular, due to the problem that the oxide-nitride-oxide (ONO) and the control gate material do not sufficiently cover the floating gate as the gap between the floating gates decreases, the conversion to the SONOS or TANOS structure is promoted below 20 nm. There is a situation.

However, nitride trapping memory, such as SONOS and TANOS, is currently undergoing research on improving various processes and materials due to serious problems of reliability deterioration such as retention. In addition, since the nitride trapping memory has a MOS transistor structure including a storage site, the MOS transistor characteristics deteriorate as the cell size decreases.

Various structures for improving the scaling problem of flash memory have been proposed. Among them, a magnetic memory using a magnetization inversion device such as a magnetic tunneling junction (MTJ) is one of them. In addition, research is being actively conducted to use diodes instead of MOS transistors as switching devices.

However, bidirectional current driving is required to record and erase information using the spin-transfer torque (STT) phenomenon. However, when a diode is used as a switching element, there is a limitation that bidirectional current driving cannot be performed. Therefore, a magnetic memory including a magnetization inversion element and a diode switching element using a spin transfer torque phenomenon is a problem in driving.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of operating a magnetic memory having no problem in driving even when using a diode as a switching device.

In order to solve the above technical problem, a method of operating a magnetic memory according to the present invention includes a plurality of magnetization inversion elements arranged in rows and columns, and a magnetization inversion element formed under the plurality of magnetization inversion elements and arranged in a column direction. And a bit line connecting the magnetization inversion elements arranged on the plurality of magnetization inversion elements and arranged in a row direction, wherein the recording of information is performed on the bit line and the word. A current is applied to the magnetization inversion element through a line to invert the magnetization of the magnetization inversion element by electron injection by a spin-transfer torque (STT) phenomenon, and information is erased. The magnetization of the magnetization inversion element is inverted by a magnetic field applied from the outside.

According to the present invention, recording of information is performed by electron injection by the STT phenomenon, and erasing of information is performed by applying an external magnetic field, so that there is no problem in driving even when a diode is used as the switching element. In addition, erasing of information may be performed in units of pages, and thus, efficiency is higher than that of a flash memory in units of blocks. As a result, while replacing the conventional flash memory, it is possible to solve the problem that occurs during scaling.

The present invention relates to a method of operating a magnetic memory.

The magnetic memory used in the present invention includes a plurality of magnet inverting elements arranged in rows and columns, a bit line which is formed under the plurality of magnetizing inversion elements and arranged in a column direction, and a plurality of magnetizing inversion elements. And a bit line formed at an upper portion of the connecting portion to connect the magnetization inversion elements arranged in the row direction.

Such a method of writing information to the magnetic memory includes applying a current to the magnetization inversion element through a bit line and a word line to invert the magnetization of the magnetization inversion element by electron injection by a spin-transfer torque (STT) phenomenon. It consists of a unit of magneto-inverting element. In addition, the method of erasing information comprises a page unit of magnetization inversion elements arranged in the same row by inverting magnetization of the magnetization inversion element by a magnetic field applied from the outside of the magnetization inversion element.

The magnetic memory may further include a switching element between the magnetization inversion element and the bit line, and the switching element may be a diode. The diode may be a P-N diode or a Schottky diode, and may be formed such that the bit direction is forward in the word line. If the diode is a P-N diode, the bit line may be formed as an active N + region.

Hereinafter, exemplary embodiments of a method of operating a magnetic memory according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the scope of the invention to those skilled in the art. It is provided for complete information.

FIG. 1 is a diagram showing the structure of a cell of a magnetic memory used in the present invention, showing an initial state and symbolizing the cell. 3 is a diagram showing the structure of a magnetic memory cell used in the present invention, showing a program state, and symbolizing it is shown in FIG.

As shown in Figs. 1 and 3, the magnetic memory cell used in the present invention is a magnetization inversion element composed of a magnetic tunneling junction (MTJ) 140 formed on top of a P-type impurity region 120 of a PN diode element. Structure.

In more detail, the magnetic memory cell used in the present invention forms a P-N diode by doping the P-type impurity region 120 on the line of the active N + region 110. The active N + region 110 becomes a bit line. The barrier conductive layer 130 is formed on the P-type impurity region 120, and the pinned layer 141, the insulating layer 142, and the free layer 143 are sequentially stacked on the barrier conductive layer 130. MTJ 140 is formed. The word line 150 is formed on the MTJ 140.

The pinned layer 141 and the free layer 143 are made of a ferromagnetic material such as permalloy, and the insulating layer 142 is made of an insulator such as AlO and MgO. In the pinned layer 141 and the free layer 143, horizontal magnetization in a direction parallel to the upper surface may be formed. The free layer 143 is a layer in which magnetization is inverted when a current of more than a threshold current density is applied or an external magnetic field of more than a critical magnetic field is applied. The MTJ 140 stores information by the magnetization direction of the free layer 143. . The pinned layer 141 is a layer that provides reference magnetization to read the magnetization direction of the free layer 143. An external magnetic field of a critical current density or a critical magnetic field is applied to which the magnetization of the free layer 143 is inverted. Even if the magnetization is not reversed.

As shown in FIG. 1, the magnetization direction of the free layer 143 is the opposite direction to the magnetization direction of the pinned layer 141. The magnetization directions of the free layer 143 and the pinned layer 141 are opposite to each other. Therefore, it has a relatively large magnetoresistance value. In order to program the magnetic memory cell in the initial state, the magnetization direction of the free layer 143 should be reversed. When the magnetization direction of the free layer 143 is reversed in the initial state, as shown in FIG. 3, the magnetization directions of the free layer 143 and the pinned layer 141 are the same to have a relatively small magnetoresistance value. A state in which the magnetization directions of the free layer 143 and the pinned layer 141 are formed in the same direction as shown in FIG. 3 is referred to as a “program state”. A state in which the magnetization directions of the free layer 143 and the pinned layer 141 are reversed as shown in FIG. 1 by inverting the magnetization directions of the free layer 143 in the program state is referred to as an “erased state”.

The magnetic memory cells shown in FIG. 1 are arranged in rows and columns to form a magnetic memory, and FIG. 5 shows an initial state of the magnetic memory. FIG. 5 shows an example in which magnetic memory cells are arranged in an 8 × 8 matrix, and the present invention is applied to the case where the magnetic memory cells are arranged in other forms. In FIG. 5, the bit line is represented by BL and the word line is represented by WL. And each bit line is BL1, BL2,… in order from the left. , BL8, and each word line is sequentially selected from WL1, WL2,... , WL8. In addition, since the bit line is formed as an active N + region, there is an N + resistance in the bit line, which is indicated by reference numeral 510 of FIG. 5.

Record of information

In the present invention, a method of recording information in the magnetic memory is achieved by inverting the magnetization of the magnetization inversion element by electron injection by the STT phenomenon. As an example, a method of writing information to the magnetic memory cell indicated by 520 of FIG. 5 is illustrated in FIG. 6. When information is written to the magnetic memory cell indicated by 520 of FIG. 5, the magnetic memory cell indicated by 520 of FIG. 5 is in a program state like the magnetic memory cell indicated by 620 of FIG. 6. For convenience of description, the magnetic memory cell 620 of FIG. 6 is referred to as a 'selected cell'.

As shown in FIG. 6, in order to put the selected cell 620 into a program state, the first write voltage V _{P , 1} is applied to the word line WL2 connected to the selected cell 620, and the selected cell 620 is programmed. A second write voltage V _{P , 2} is applied to one end of the bit line BL2 connected to 620. At this time, V _{P , 1} is set to be larger than V _{P , 2} so that current flows in the selected cell 620 as shown in the arrow direction of FIG. 6. When a current flows from WL2 to BL2 in the selected cell 620 in the direction of the arrow, electrons are injected by the STT phenomenon and the magnetization of the free layer of the selected cell 620 is inverted to record the information.

A third write voltage V _{P , 3} is applied to the bit lines BL1, BL3, BL4,..., BL8 that are not connected to the selected cell 620. At this time, V _{P , 3} is set to be larger than V _{P , 1} . If V _{P , 3} is greater than V _{P , 1} , current can flow from bit lines BL1, BL3, BL4, ..., BL8 to word line WL2, but in each magnetic memory cell a diode is placed from the word line to the bit line. The line direction is formed to be forward, so that current cannot flow from the bit line to the word line. Therefore, when V _{P , 3} greater than V _{P , 1} is applied to the bit lines BL1, BL3, BL4,..., BL8 that are not connected to the selected cell 620, current is applied to the remaining cells other than the selected cell 620. It will not flow and information will not be recorded.

In addition, no voltage is applied to the word lines WL1, WL3, WL4,..., And WL8 not connected to the selected cell 620, so that no current flows to the remaining cells.

In the present embodiment, since the bit line is configured as an active N + region, the N + resistor 510 exists as described above. Therefore, in order to improve efficiency, it is desirable to allow current to flow toward the N + resistance 510. To this end, as shown in FIG. 6, V _{P, 2} smaller than V _{P , 1} is applied to _one end of the N + resistance between the selected cell 620 and the bit line BL2, and the selected cell 620 and the bit are smaller. The fourth write voltage V _{P , 4} greater than V _{P , 1} is applied to the large end where the N + resistance between the lines BL2 is small. Since V _{P , 4} is greater than V _{P , 1} , the current flowing in the selected cell 620 from the word line WL2 does not flow toward the side where V _{P , 4} is applied, but only on the side where V _{P , 2} is applied. Since flows through, there is no waste of current and the efficiency is excellent.

A schematic diagram of recording information through the above-described process is shown in FIG. 7.

As shown in FIG. 7, before recording information, the magnetization directions of the free layers 143a and 143b provided in the two cells are opposite to the pinned layer 141. In the initial state, a method of changing information to a program state by recording information in only the left cell is shown in FIG. 7. That is, the second write voltage V _{P , 2} is applied to the bit line 110, and the first write voltage V _{P , 1} greater than the second write voltage is applied to the word line 150a connected to the left cell. When no voltage is applied to the word line 150b connected to the right cell, no current flows to the right cell, and only the left cell flows from the word line 150a toward the bit line 110. Through the injection of electrons by the STT phenomenon through the current flowing from the word line 150a toward the bit line 110, only the magnetization direction of the free layer 143a existing in the left cell is reversed to be in the same direction as the fixed layer 141. You can do it. When voltages are applied to the bit lines 110 and the word lines 150a and 150b as described above, information may be written only to desired cells and changed from an initial state to a program state.

Erasure of information

8 to 10 illustrate a method of erasing information in a program state and changing the state to an erase state. First, the method of changing from the initial state to the program state is made by the above-described information recording method. At this time, the recording of information may be performed for each cell, and thus a circuit diagram of the magnetic memory changed to a program state is shown in FIG. 8. Although the recording of information was performed by electron injection method by STT phenomenon, since current cannot flow from bit line to word line by diodes provided in each cell, erasure of information uses electron injection method by STT phenomenon. It cannot be done through. Therefore, in the present invention, erasing of information is performed by applying an external magnetic field to reverse magnetization of the free layer 143. When the external magnetic field is applied to erase the information, the information may be formed in a page unit composed of cells arranged in the same row. That is, the information of all the magnetizing and inverting elements provided in the cells sharing the word line is erased at once.

As an example, a method of erasing information recorded on two pages indicated by 810 of FIG. 8 is illustrated in FIG. 9. When the information recorded on the page indicated by 810 of FIG. 8 is erased, the page indicated by 810 of FIG. 8 is erased as shown by the page 820 of FIG. 9. For convenience of description, two pages indicated as 820 of FIG. 9 are referred to as 'selected pages'.

As shown in FIG. 9, in order to put the selected page 820 in an erased state, a first erase voltage V _{E , 1} is applied to the word lines WL2 and WL3 connected to the selected page 820. The second erase voltage V _{E , 2} is applied to all the bit lines BL1, BL2,..., BL8. At this time, V _{E , 1} is set to be smaller than V _{E , 2} . Since V _{E , 1} is smaller than V _{E , 2} , current may flow from the bit lines BL1, BL2,..., BL8 to the word lines WL2, WL3, but as described above, each of the magnetic memory cells may be provided. Since the diode is formed so that the direction of the bit line is forward from the word line, current cannot flow from the bit line to the word line. Therefore, when the voltage is applied as described above, as shown by the arrow of FIG. 9, current flows along the word lines WL2 and WL3 connected to the selected page 820. The current flowing along the word lines WL2 and WL3 generates a magnetic field, and all of the free layers provided on the page 820 connected to the word lines WL2 and WL3 from the magnetic field invert magnetization in the same direction as the magnetization direction of the fixed layer. You can do it. In this way, information can be erased in units of pages, and if necessary, information can also be erased in units of entire blocks.

The voltages are not applied to the word lines WL1, WL4, WL5,..., And WL8 not connected to the selected page 820 so that the magnetization of the free layer provided in the magnetic memory cells other than the selected page 820 is not inverted. do.

A schematic diagram of erasing information through the above-described process is shown in FIG. 10.

The upper figure of FIG. 10 shows a program state, and the lower figure shows an erase state by inverting magnetization in the program state. As shown in the upper figure, the magnetization direction of the free layers 143c and 143d provided in each of the two cells is the same as that of the fixed layer 141. In the program state, a method of erasing only the information recorded on the left page is shown in FIG. That is, the second erase voltage V _{E , 2} is applied to the bit line 110, and the first erase voltage V _{E , 1} smaller than the second erase voltage is applied to the word line 150c connected to the left cell. If no voltage is applied to the word line 150b connected to the right cell, no current flows to the right page, but current flows to the word line 150c connected to the left page. The magnetic field indicated by the dotted line is induced from the current flowing through the word line 150c, and only the magnetization direction of the free layer 143c provided on the left page is reversed by the induced external magnetic field to be opposite to the fixed layer 141. . When voltages are applied to the bit lines 110 and the word lines 150c and 150d as described above, only the information of the desired page can be erased and changed from the program state to the erase state.

When information is recorded and erased in this manner, the recording of the information is performed by electron injection by the STT phenomenon, and the erasing of information is performed by applying an external magnetic field. There will be no problem. In addition, erasing of information may be performed in units of pages, and thus, efficiency is higher than that of a flash memory in units of blocks. As a result, while replacing the conventional flash memory, it is possible to solve the problem that occurs during scaling.

Although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific preferred embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

1 is a diagram showing a structure of a cell of a magnetic memory used in the present invention, showing an initial state.

2 is a diagram illustrating an initial state of a magnetic memory cell.

3 is a diagram showing the structure of a magnetic memory cell used in the present invention, showing a program state.

4 is a diagram illustrating a program state of a magnetic memory cell.

5 is a circuit diagram showing an initial state of a magnetic memory used in the present invention.

6 is a diagram illustrating a voltage applied to record information according to the present invention.

7 is a schematic diagram for explaining a method of recording information according to the present invention.

8 is a circuit diagram showing a program state of the magnetic memory used in the present invention.

9 is a diagram illustrating a voltage applied to erase information according to the present invention.

10 is a schematic diagram for explaining a method of erasing information according to the present invention.

Claims (11)

A bit line formed between the plurality of magnetization inversion elements arranged in rows and columns, the magnetization inversion elements formed under the plurality of magnetization inversion elements and arranged in the column direction, and formed on the plurality of magnetization inversion elements A method of operating a magnetic memory having a word line connecting magnetic inversion elements arranged in a direction, The recording of information is performed by applying a current to the magnetization inversion element through the bit line and the word line, thereby inverting the magnetization of the magnetization inversion element by electron injection by a spin-transfer torque (STT) phenomenon. In units, The erasing of information is performed in units of pages of magnetization inversion elements arranged in the same row by inverting magnetization of the magnetization inversion element by a magnetic field applied from the outside of the magnetization inversion element. A diode is provided between the bit line and the word line as a switching element connected to the magnetization inversion element. The record of the information, A first write voltage is applied to a word line connected to the magnetization inversion element to record information, and a second write voltage is applied to one end of the bit line connected to the magnetization inversion element to record the information, and the information is to be recorded. A third write voltage is applied to a bit line not connected to the magnetizing inverting element, wherein the third write voltage is greater than the first write voltage and the first write voltage is greater than the second write voltage. , A fourth write voltage greater than the first write voltage is applied to the other end of the bit line connected to the magnetization inversion device for recording the information. The resistance value between one end of the bit line to which the second write voltage is applied and the magnetization inversion element to write the information is the resistance between the other end of the bit line to which the fourth write voltage is applied and the magnetization inversion element to write the information. A method of operating a magnetic memory, characterized in that less than the value. delete delete delete The method of claim 1, And the diode is formed between the bit line and the magnetization inverting element such that the direction of the bit line in the word line is in the forward direction. The method of claim 5, And the bit line is formed of an active N + region. delete delete The method of claim 1, The deletion of the information, The first erase voltage is applied to the word line connected to the page to be erased and the second erase voltage is applied to all the bit lines, but the voltage is applied so that the second erase voltage is larger than the first erase voltage. Characterized in that the operation method of the magnetic memory. The method according to any one of claims 1, 5, 6 or 9, The magnetizing inversion element is A pinned layer made of ferromagnetic material; An insulating layer formed on one side of the fixed layer and made of an insulator; And And a free layer formed on one side of the insulating layer so that the insulating layer is disposed between the pinned layer and a ferromagnetic material. The method of claim 10, The magnetization of the pinned layer is a direction parallel to the upper surface of the pinned layer, the magnetization of the free layer is characterized in that arranged in a direction parallel to the upper surface of the free layer.

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