KR101046713B1

KR101046713B1 - Package Substrate and Manufacturing Method of Package Substrate

Info

Publication number: KR101046713B1
Application number: KR20090126387A
Authority: KR
Inventors: 최원
Original assignee: 삼성전기주식회사
Priority date: 2009-12-17
Filing date: 2009-12-17
Publication date: 2011-07-06
Also published as: KR20110069591A

Abstract

A package substrate and a method of manufacturing the package substrate are disclosed. Insulators; A first pad formed on a surface of the insulator; A second pad spaced apart from the first pad on a surface of the insulator; A first solder resist stacked on the insulator such that the first pad and the second pad are open; A second solder resist stacked on the first solder resist adjacent to the first pad such that a cavity is formed on the first pad; And the package substrate including a top ball pad filled in the cavity, can increase the position of the top ball, even if the separation distance between the top ball and the top ball can prevent the top package substrate from falling off the top ball, the top package substrate Electrical connection with can be formed smoothly.

Package Board, Topball

Description

Package board and method of manufacturing printed circuit board {Printed circuit board and Method of manufacturing printed circuit board}

The present invention relates to a package substrate and a method for manufacturing the package substrate.

As electrical and electronic products become high performance and electronic devices become light and small, the thinning, high density, and high mounting of the core components are becoming important issues. Currently, in the case of computers, laptops, mobile phones, etc., as the memory capacity increases, the chip capacity increases, such as a large amount of random access memory (RAM) and flash memory (Flash memory), but the package is being miniaturized. In order to realize this, the size of a package used as a core component is naturally tended to be miniaturized, and various techniques for mounting a larger number of packages on a limited size package substrate have been proposed and studied.

As a method for reducing the size of such a package, a technique for minimizing the size and thickness of the package while using chips having the same storage capacity has been proposed, which is commonly referred to as a flip chip package.

The flip chip package is a high-density packaging bonding process that allows the positioning of the bonding pads in the circuitry of a semiconductor chip as needed to simplify circuit design, reduce resistance by circuit lines, and reduce power consumption. The shorter path of the semiconductor package can improve the operation speed of the semiconductor package, so the electrical characteristics are excellent, and the backside of the semiconductor chip is exposed to the outside, so the thermal characteristics are excellent, and a small package can be realized. Self-Alignment) facilitates bonding.

Such a package has a shape in which a top package substrate is mounted as a package substrate to enable electrical connection to a bottom package substrate on which a semiconductor chip is mounted and a ball formed on an upper portion of the bottom package substrate.

In recent years, the number of balls that transmit and receive electrical signals to the top package substrate is increasing, so to increase the number of balls, the ball size is miniaturized to form a fine ball pitch between the balls and the balls. I'm making it. However, there is a limit that the thickness of the semiconductor chip is lowered (Down size), and since the mounted height of the semiconductor chip is formed larger than the size of the ball, there is a fear that the ball is not connected to the top package substrate by the semiconductor chip.

The present invention provides a package substrate and a method for manufacturing the package substrate that can increase the position of the top ball.

According to an aspect of the invention, the insulator; A first pad formed on a surface of the insulator; A second pad spaced apart from the first pad on a surface of the insulator; A first solder resist stacked on the insulator such that the first pad and the second pad are open; A second solder resist stacked on the first solder resist adjacent to the first pad such that a cavity is formed on the first pad; And a top ball pad filled in the cavity.

Here, a top ball may be provided on the top ball pad, and a bump may be provided on the second pad.

Here, a top package substrate mounted on top of the top ball so as to be in electrical connection with the top ball; And a semiconductor chip mounted on the bump to make electrical connection with the bump.

Further, according to another aspect of the invention, preparing an insulator in which the first pad and the second pad is formed; Stacking a first solder resist on the insulator such that the first pad and the second pad are opened; Depositing a second solder resist on a surface of the first solder resist adjacent to the first pad such that a cavity is formed on the first pad; And a step of filling the top ball pad in the cavity.

The charging of the top pad may include nickel plating in the cavity.

The charging of the top pad may further include, after the nickel plating, gold plating on an upper side of the nickel plating.

Here, after the charging of the top pad, forming a bump on the second pad; And forming a top ball on the top ball pad.

Here, after the forming of the bump, further comprising mounting a semiconductor chip on the top of the bump so that the electrical connection with the bump, after the step of forming the top ball, the electrical connection with the top ball The method may further include mounting a top package substrate on top of the top ball.

According to an embodiment of the present invention, the position of the top ball can be increased, and even if the separation distance between the top ball and the top ball is reduced, the top package substrate can be prevented from falling off from the top ball, so that the electrical connection with the top package substrate can be smoothly performed. Can be formed.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, an embodiment of a package substrate and a method of manufacturing a package substrate according to the present invention will be described in detail with reference to the accompanying drawings, and in describing with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals. And duplicate description thereof will be omitted.

1 is a flowchart illustrating a method of manufacturing a package substrate according to an embodiment of the present invention, and FIGS. 2 to 8 are views illustrating a method of manufacturing a package substrate according to an embodiment of the present invention.

First, as shown in FIG. 2, an insulator 110 on which the first pad 111 and the second pad 113 are formed is prepared (S110). As the insulator 110, a prepreg impregnated with a reinforcing material such as glass fiber may be used in the resin, and any material that may be used for the package substrate may be used. In addition, a circuit pattern (not shown) and first and second pads 111 and 113 are formed on the surface of the insulator 110.

The first and second pads 111 and 113 serve as terminals that are partially exposed by circuit patterns formed on the insulator 110 to be connected to external components such as semiconductor chips or top package substrates. In order to form the first and second pads 111 and 113, a copper foil (not shown) is laminated on the surface of the insulator 110 and then etched and patterned to form the first and second pads 111 and 113. A seed layer (not shown) is formed on the surface of the insulator 110 by using an additive process and an inkjet head (not shown) to form a seed layer (not shown) and selectively perform electroplating thereon. Various methods may be used, such as an inkjet process for directly printing conductive ink on a surface. 2 illustrates a plurality of first and second pads 111 and 113 spaced apart from each other on the surface of the insulator 110.

Next, as shown in FIG. 3, the first solder resist 120 is stacked on the insulator 110 such that the first pad 111 and the second pad 113 are opened (S120). A first solder resist 120 is formed on the insulator 110 to cover a part or all of the first pad 111 and the second pad 113 and to cover the circuit pattern to prevent oxidation of the circuit pattern. . 3 illustrates a partially opened first pad 111 and second pad 113. The stack S120 of the first solder resist 120 includes, for example, applying a viscous solder resist ink to the insulator 110 and selectively exposing and developing the solder resist ink to form the first solder resist 120. Can be formed.

In this process, the solder resist ink which is not photoreacted by the photosensitive film may be removed through chemical treatment, and the portion subjected to ultraviolet rays remains, so that the first solder resist 120 is disposed on the upper and lower surfaces of the insulator 110. To be stacked.

Next, as shown in FIG. 4, the first pad 111 is formed such that the cavity 131 is formed in correspondence with the position where the top ball pad 140 described below is formed on the first pad 111. The second solder resist 130 is laminated on the surface of the first solder resist 120 adjacent to the one at step S130. The stacking of the second solder resist 130 may be performed by applying solder resist ink and exposing and developing the solder resist ink, as in the process of stacking the first solder resist 120.

Next, the top ball pad 140 is formed on the first pad 111 at the height of the second solder resist 130 (S140).

The top ball pad 140 is charged in the cavity 131 (S140). For example, the top ball pad 140 may be charged to the height of the second solder resist 130. In the formation of the top ball pad 140, first, as shown in FIG. 5, the nickel plating layer 141 may be formed by nickel plating the first pad 111 at the height of the second solder resist 130. (S141). Next, as shown in FIG. 6, the gold plating layer 143 may be formed by gold plating on the nickel plating layer 141 (S143).

6 illustrates a top ball pad 140 including a nickel plated layer 141 and a gold plated layer 143. In addition, the bump 150 is formed on the upper portion of the second pad 113 is shown.

If the bump 150 may be formed by applying a solder paste on the upper portion of the second pad 113 and through a reflow process (S150), as shown in FIG. 7, through the planarization process of the bump 150, The flat bump 151 may be formed.

As illustrated in FIG. 8, the semiconductor chip 153 may be mounted on the flat bump 151 so as to be electrically connected to the flat bump 151 (S160). Then, after the top ball 160 is formed on the top ball pad 140 (S170), the top package substrate 165 may be mounted on the top ball 160 to enable electrical connection with the top ball 160. There is (S180). For example, the top ball 160 may be formed by attaching a small solder ball.

As shown in the figure, the semiconductor chip 153 may be flip chip bonded to the package substrate 100, and the underfill 155 may be injected between the semiconductor chip 153 and the first solder resist 120. have. The underfill 155 may be formed by injecting a liquid material made of a silicon or epoxy resin composite between the semiconductor chip 153 and the first solder resist 120 using a capillary phenomenon and performing a curing process. have.

The package substrate 100 formed through the process may be spaced apart from the insulator 110, the first pad 111 formed on the surface of the insulator 110, and the first pad 111 on the surface of the insulator 110. The second pad 113 formed to be formed, the top ball pad 140 stacked on the first pad 111, and the first pad 111 and the second pad 113 stacked on the insulator 110 are opened. The second solder resist 130 is stacked on the first solder resist 120 adjacent to the first solder resist 120 and the top ball pad 140. In addition, the top ball pad 140 is provided with a top ball 160, the second pad 113 is provided with a flat bump 151, and the top ball pad 140 is formed with the height of the second solder resist 130.

According to such an embodiment, the package substrate 100 may stack the second solder resist 130 and form the height of the top ball pad 140 at the height of the second solder resist 130, so that the top ball 160 is formed. Ball pitch (d) between the top ball 160 and the top ball 160 becomes smaller, the top ball 160 can be prevented from falling off from the top package substrate 165. The seamless package 200 can be formed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

1 is a flow chart showing a manufacturing method of a package substrate according to an embodiment of the present invention.

2 to 8 illustrate a method of manufacturing a package substrate according to an embodiment of the present invention.

110: insulator 111: first pad

113: second pad 120: first solder resist

130: second solder resist 140: top ball pad

141: nickel plated layer 143: gold plated layer

150: bump 151: flat bump

153: semiconductor chip 160: top ball

Claims

Insulators;

A first pad formed on a surface of the insulator;

A second pad spaced apart from the first pad on a surface of the insulator;

A first solder resist stacked on the insulator such that the first pad and the second pad are open;

A second solder resist stacked on the first solder resist adjacent to the first pad such that a cavity is formed on the first pad;

A top ball pad filled in the cavity;

A top ball provided on the top ball pad;

A bump provided on the second pad;

A top package substrate mounted on an upper portion of the top ball to be electrically connected to the top ball; And

And a semiconductor chip mounted on the bump to make electrical connection with the bump.

delete

Preparing an insulator in which a first pad and a second pad are formed;

Stacking a first solder resist on the insulator such that the first pad and the second pad are opened;

Depositing a second solder resist on a surface of the first solder resist adjacent to the first pad such that a cavity is formed on the first pad;

Filling a top ball pad in the cavity;

Forming bumps on the second pads;

Mounting a semiconductor chip on the bump to make electrical connection with the bump;

Forming a top ball on the top ball pad; And

And mounting a top package substrate on top of the top ball so as to make electrical connection with the top ball.

5. The method of claim 4,

The filling of the top pad may include nickel plating in the cavity.

The method of claim 5,

Charging the top pad,

After the nickel plating step, further comprising the step of gold plating on the upper side of the nickel plating.

delete