KR101039803B1 - Floating body nonvolatile memory device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A floating body nonvolatile memory device and a manufacturing method thereof are provided to maintain programmed charges by trapping holes by injecting nano crystal to the floating body of a 1T-DRAM device even through the power is not supplied. CONSTITUTION: A buried insulation layer(110) is formed in a semiconductor substrate(100). A gate insulation layer(500) is grown from a groove unit on the surface of the semiconductor substrate. A gate electrode layer(600) is formed on the upper side of the gate insulation layer. A source region(200) and a drain region(300) are formed on both sides of the gate insulation layer. A channel region is formed between the buried insulation layer and the gate insulation layer.

Description

Floating body nonvolatile memory device and manufacturing method thereof

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly to a floating body nonvolatile memory device and a method of manufacturing the same.

The conventional dynamic random access memory (DRAM) structure consists of one transistor and one cell capacitor. Recently, with the introduction of high-density electronic products, the increase in DRAM integration is required. To satisfy this, the size of the cell device must be reduced. However, miniaturization of cell devices requires a very difficult manufacturing process. In order to solve this problem, recent studies using a MOS device having a floating body as a DRAM cell have been published. The device's operation allows operations such as DRAM memory operations, while storing or removing charges in the floating body. Since it requires one transistor, it can be implemented in a simple process unlike a conventional DRAM process. Such a DRAM cell is generally referred to as a single transistor floating body DRAM cell (1T-DRAM).

1 is a cross-sectional view illustrating a conventional single transistor floating body DRAM cell. Referring to FIG. 1, a conventional single transistor floating body DRAM cell includes a buried oxide (BOX) 12 disposed on a semiconductor substrate 10. The floating body 13, the source region 16, and the drain region 17 are disposed on the buried oxide layer BOX 12.

A gate dielectric film 14 and a gate electrode 15 sequentially stacked on the floating body 13 are provided. The source region 16 is connected to the ground GND, the drain region 17 is connected to the bit line BL, and the gate electrode 15 is connected to the word line WL.

As shown in FIG. 1, the floating body 13 is electrically isolated by the buried oxide film BOX 12, the gate dielectric film 14, the source region 16, and the drain region 17. . The single transistor floating body DRAM cell stores and reads data using a floating body effect.

A program operation (ie, data "1" is programmed) in the single transistor floating body DRAM cell will be described. In order to perform the program, the source region 16 is grounded, a word line program voltage equal to or greater than a threshold voltage is applied to the gate electrode 15, and a bit line program voltage is applied to the drain region 17.

The data program operation generates holes in the floating body 13 near the drain region 17, and holes are accumulated in the floating body 13. Due to the holes accumulated in the floating body 13, the potential of the floating body is increased to lower the threshold voltage of the transistor.

In contrast, an operation of erasing programmed data (programming “0”) applies a bit line program erase voltage having a polarity opposite to that of the program voltage to the drain region 17 to erase accumulated holes, In this case, the potential of the floating body drops, thereby increasing the threshold voltage of the transistor.

A read operation, that is, reading the data, to a single transistor floating body DRAM cell will be described. The source region 16 is grounded. A word line read voltage lower than the word line program voltage is applied to the gate electrode 15. A bit line read voltage is applied to the drain region 17. At this time, the amount of current flowing between the source region 16 and the drain region 17 is different depending on the presence of the holes (holes). That is, the amount of current flowing between the source region 16 and the drain region 17 is sensed to read data stored in the single transistor floating body DRAM cell.

That is, the threshold voltage is changed according to the accumulation amount of the holes. That is, the amount of current flowing between the source region 16 and the drain region 17 is different depending on the accumulation amount of the holes.

However, the floating body DRAM cell has a much shorter data retention time than the conventional DRAM cell, that is, the holes accumulated in the floating body in the DRAM cell are extinguished very quickly by the leakage current to the drain region. Lost. Therefore, since the refresh must be performed before the holes accumulated in the floating body disappear, the refresh cycle is very short compared to the conventional DRAM cells. As described above, when the refresh cycle is short, it is not easy to control the refresh operation, so that a function failure such as data stored in a cell is reversed is likely to occur.

In addition, since the floating body DRAM cell is a volatile memory device, when the power is removed, the programmed data is also removed.

An object of the present invention is to provide a nonvolatile memory device using a floating body and a method of manufacturing the same by adding a simple process to a conventional process of manufacturing a floating body DRAM cell.

In particular, an object of the present invention is to provide a nonvolatile memory device capable of multi-bit programming in one floating body cell and a method of manufacturing the same.

A nonvolatile memory device according to a preferred embodiment of the present invention for solving the above problems is a semiconductor substrate including a buried insulating film therein; A gate insulating film formed from a groove formed on a surface of the semiconductor substrate to protrude from the surface of the semiconductor substrate; A gate electrode layer formed on the gate insulating layer; Source and drain regions formed on both sides of the gate insulating layer below the surface of the semiconductor substrate; And a channel region formed between the buried insulating layer and the gate insulating layer, the channel region including charge trapping regions therein for trapping charge, wherein the channel region is formed between the source region and a lower portion of the gate insulating layer. A first charge trap region for trapping holes generated near the source region; And a second charge capture region formed between the drain region and the lower portion of the gate insulating layer to capture holes generated near the drain region.

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In addition, the first charge capture region and the second charge capture region of the nonvolatile memory device according to an exemplary embodiment of the present invention may be composed of nanocrystals formed by implanting any one of Si, Ge, and Au ions. .

In addition, the semiconductor substrate of the nonvolatile memory device according to the preferred embodiment of the present invention, the first layer formed of a single crystal silicon layer; A second layer on which the buried insulation film is formed; And a third layer formed of single crystal silicon on the second layer and having the groove, the channel region, the source region, and the drain region formed thereon.

On the other hand, a method of manufacturing a nonvolatile memory device according to a preferred embodiment of the present invention, (a) forming a groove on a semiconductor substrate including a buried insulating film; (b) forming charge trapping regions on both sides of the groove; (c) forming a gate insulating film from the groove, and forming a gate electrode layer on the gate insulating film; And (d) forming the source region and the dry region such that the charge trap region is positioned between the gate insulating layer and the source region and between the gate insulating layer and the drain region.

In addition, the step (a) of the method of manufacturing a nonvolatile memory device according to the preferred embodiment of the present invention, doping the impurities to form a channel region; And forming the groove in the center of the channel region.

In addition, the semiconductor substrate used in the method of manufacturing a nonvolatile memory device according to the preferred embodiment of the present invention, the first layer implemented with a single crystal silicon layer; A second layer, which is a buried insulation film formed on the first layer; And a third layer formed of a single crystal silicon layer on the buried insulating layer, and the groove portion may be formed in the third layer.

In addition, the step (b) of the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention, (b1) performing an ion implantation process in the channel region; And (b2) performing heat treatment on the semiconductor substrate on which the ion implantation process has been performed to form the charge trap region.

Further, in the step (b1) of the method of manufacturing a nonvolatile memory device according to the preferred embodiment of the present invention, the ions implanted through the groove portion are located in the buried insulating film, and the ions implanted through the region other than the groove portion are the third The ion implantation process may be performed on any one of Si, Ge, and Au so as to be located at the bottom of the layer.

In addition, the step (b2) of the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention, by performing a heat treatment to form the ions located under the third layer of nanocrystals, consisting of nanocrystals Charge trap regions can be formed.

On the other hand, a program method of a nonvolatile memory device according to a preferred embodiment of the present invention, a semiconductor substrate including a buried insulating film therein; A gate insulating film formed from a groove formed on a surface of the semiconductor substrate to protrude from the surface of the semiconductor substrate; A gate electrode layer formed on the gate insulating layer; Source and drain regions formed on both sides of the gate insulating layer below the surface of the semiconductor substrate; A channel region formed between the buried insulating film and the gate insulating film; And a first charge capture region formed between the source region and the gate insulating film, and a second charge capture region formed between the drain region and the gate insulating film, among the channel regions, as a program method of the floating body nonvolatile memory device. And forming a hole in the second charge trap region by grounding the source region, applying a first program voltage to the gate electrode layer, and applying a second program voltage to the drain region. By capturing the crystal, electric charges are programmed into the second charge trapping region, the drain region is grounded, a first program voltage is applied to the gate electrode layer, and a second program voltage is applied to the source region, thereby providing the source region. Capture the first charge in the vicinity of the hole generated The charge can be programmed into the first charge trapping region by trapping the nanocrystals formed in the region.

The present invention can provide a non-volatile function that can maintain programmed charge even when a power source is removed by injecting holes by injecting nanocrystals that trap charges (holes) in the floating body of a conventional 1T-DRAM device.

In addition, the nonvolatile memory device of the present invention can be manufactured by adding only an ion implantation step to the conventional manufacturing process of the 1T-DRAM device, so that the manufacturing process is simple and can be manufactured at low cost.

In addition, the present invention forms a groove in the channel region between the source region and the drain region, and grows the gate insulating film from the groove so that the groove formed in the channel region receives the lower portion of the gate insulating film, By forming nanocrystal particles that trap charge on both sides, local programming is possible, thus enabling multi-bit programming.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a structure of a floating body nonvolatile memory device according to an exemplary embodiment of the present invention. 2, in the floating body nonvolatile memory device of the present invention, a gate insulating film 500 and a gate electrode layer 600 are formed on a semiconductor substrate 100 including a buried insulating film 120, and a gate insulating film 500 is provided. The source region 200 and the drain region 300 are formed at both sides of the gate electrode layer 600 at a predetermined depth from the surface of the semiconductor substrate 100. Here, the semiconductor substrate 100 is preferably an SOI substrate, which is a semiconductor substrate 100 in which the lower single crystal silicon layer 110, the buried insulating film 120, and the upper single crystal silicon layer 130 are sequentially formed. (200,300) is preferably formed on the upper single crystal silicon layer (130). Hereinafter, an example in which an SOI substrate is used as the semiconductor substrate 100 will be described.

At this time, the groove 135 is formed on the surface of the upper single crystal silicon layer 130, and the gate insulating layer 500 is filled from the groove 135 formed in the upper single crystal silicon layer 130 to form the upper single crystal silicon layer 130. It is formed to protrude from the upper surface. In the channel region 400 of the upper single crystal silicon layer 130, charges (holes) are formed between the source region 200 and the lower portion of the gate insulating layer 500 and the region between the drain region 300 and the lower portion of the gate insulating layer 500. The nanocrystal 700 which captures the () is formed.

In the preferred embodiment of the present invention, the program is performed in the same manner as the general floating body DRAM, and in the programmed state, the charges (holes) accumulated in the channel region 400 are trapped in the nanocrystals 700 to disconnect the power supply. Since it is maintained even in the state, it operates as a nonvolatile memory device. The program operation according to the present invention will be described later with reference to FIGS. 4A to 5.

3A to 3E are diagrams illustrating a manufacturing process of a floating body nonvolatile memory device according to an exemplary embodiment of the present invention. 3A to 3E, a manufacturing process of a floating body nonvolatile memory device according to an exemplary embodiment of the present invention will be described.

In order to manufacture a floating body nonvolatile memory device according to a preferred embodiment of the present invention, first, as shown in FIG. 3A, a semiconductor substrate 100 including a buried insulating film 120 is prepared. In the present invention, a semiconductor substrate 100 in which the lower single crystal silicon layer 110, the buried insulating film 120, and the upper single crystal silicon layer 130 are sequentially formed is provided, and the upper single crystal silicon is disposed on the buried insulating film 120. The layer 130 is patterned to separate the active region and the device isolation region (not shown), and the upper single crystal silicon layer 130 to expose the channel region 400 with the photoresist PR1 used as a mask for channel doping. ) And the channel region 400 is formed by implanting a second conductivity type impurity into the upper single crystal silicon layer 130 using the photoresist PR1 as an ion implantation mask. In a preferred embodiment of the present invention, the second conductivity type is P-type.

3B, the photoresist PR1 is removed, an etch mask pattern 810 is formed on the upper single crystal silicon layer 130, and a portion of the upper single crystal silicon layer 130 is etched. After forming the groove 135 in which the gate insulating layer 500 is to be formed in the center of the channel region 400, the etching mask 810 is removed.

After the groove 135 is formed in the upper single crystal silicon layer 130, as illustrated in FIG. 3C, a hard mask pattern 820 is formed in the upper single crystal silicon layer 130, and the hard mask layer pattern 820 is formed. Ion implantation of Si, Ge, Au, etc. is performed from the top of the formed substrate to the substrate.

As illustrated in FIG. 3C, the ions 900a implanted from the upper portion of the groove 135 are injected into the buried insulating layer 120 through the hard mask layer and the upper single crystal silicon layer 130, and the groove 135. Ion implantation is performed so that the ions 900b implanted from the upper portion of the other region pass through the hard mask layer pattern and are positioned below the upper single crystal silicon layer 130.

Then, when annealing is performed at a temperature of about 500 ° C. to 1000 ° C., as shown in FIG. 3D, ions 900b located in the upper single crystal silicon layer 130 may be activated to capture charges. Crystal 700 is formed. However, the state of the ions 900a implanted into the buried insulating film 120 does not change. This is due to the difference in thermal conductivity between the silicon substrate and the buried insulating film, which is an oxide film. Even when the same temperature is applied in the heat treatment process, the ions located in the semiconductor layer with good heat transfer are formed of nanocrystals, but the ions located in the buried insulating film with poor heat transfer are formed. Not enough heat transfer to form nanocrystals.

After the nanocrystals 700 are formed, as shown in FIG. 3E, the hard mask layer pattern 820 is removed, and the gate insulating layer 500 and the gate electrode layer 600 are sequentially deposited on the substrate to form the grooves ( An etching mask pattern 830 corresponding to the width of the groove 135 is formed on the upper portion of the 135, and regions other than the region where the etching mask pattern 830 is formed are etched until the upper single crystal silicon layer 130 is exposed. The etching mask pattern 830 formed on the gate electrode layer 600 is removed.

Finally, the source region 200 and the drain region 300 are formed by ion implanting a first conductivity type impurity into the upper single crystal silicon layer 130 on both sides of the gate electrode layer 600 and the gate insulating layer 500. 2, a floating body nonvolatile memory device according to a preferred embodiment of the present invention is completed. In a preferred embodiment of the present invention, the first conductivity type is preferably n-type.

4A and 4B illustrate a process of performing a program on a floating body nonvolatile memory device according to an exemplary embodiment of the present invention. First, referring to FIG. 4A, a method of programming a charge in the nanocrystal 700 formed in a region between the source region 200 and a lower portion of the gate insulating layer 500 (first charge capture region 410) will be described.

In order to program the first charge trapping region 410, the first program voltage (+ Vp1, about 1 to 10 V) is applied to the gate electrode layer 600 while the drain region 300 is grounded, and the source region is applied. The second program voltage (+ Vp2, about 1 to 10 V) is applied to (200).

When a program voltage is applied to the gate electrode layer 600 and the source region 200, impact ionization occurs near the source region 200 to cause electron-hole pairs in the channel region 400 near the source region 200. -hole pair) occurs. At this time, electrons are erased through the source region 200, and holes are trapped in the nanocrystal 700 formed in the first charge trap region 410 and accumulated in the channel region 400. At this time, the lower portion of the gate insulating film 500 formed in the groove 135 has holes formed near the source region 200 proceeding to the drain region 300 to form nanocrystals (gates) formed in the second charge capture region 420. By blocking the nanocrystals 700 formed between the lower portion of the insulating film 500 and the drain region 300, 2-bit programming is possible. The accumulated holes raise the potential of the channel region 400, and the moon turn voltage of the memory device is lowered.

Referring to FIG. 4B, a method of programming electric charges in the nanocrystal 700 formed in the region between the drain region 300 and the lower portion of the gate insulating layer 500 (the second charge capture region 420) will be described.

In order to program the second charge capture region 420, the first program voltage (+ Vp1, about 1 to 10 V) is applied to the gate electrode layer 600 while the source region 200 is grounded, and the drain region The second program voltage (+ Vp2, about 1 to 10 V) is applied to 300.

When a program voltage is applied to the gate electrode layer 600 and the drain region 300, impact ionization occurs in the vicinity of the drain region 300, and thus the electron-hole pair ( electron-hole pairs). At this time, electrons are erased through the drain region 300, and holes are trapped in the nanocrystal 700 and accumulated in the channel region 400. In this case, the gate insulating film 500 formed in the groove 135 may have nanocrystals (gate insulating film) formed in the first charge trap region 410 by holes generated near the drain region 300 going to the source region 200. By blocking the nanocrystal 700 formed between the lower portion of the 500 and the source region 200, a 2-bit program is possible. The accumulated holes raise the potential of the channel region 400, and the moon turn voltage of the memory device is lowered.

5 is a diagram illustrating a process of erasing a programmed charge according to a preferred embodiment of the present invention. Referring to FIG. 5, a process of erasing charges programmed in the second charge capture region 420 will be described. First, the source region 200 of the floating body nonvolatile memory device is grounded, and the gate electrode ( A positive first erase voltage (+ Ve1) is applied to 112, and a negative second erase voltage (−Ve2) is applied to the drain region 300. Then, holes captured in the nanocrystals 700 of the second charge trapping region 420 are erased through the drain region 300, and when the holes are erased, the potential of the channel region 400 becomes relatively low, and thus the threshold The voltage will increase.

On the other hand, the process of erasing the electric charge programmed in the first charge trap region 410, similar to the method shown in FIG. 5, grounds the drain region 300 and positively discharges the gate electrode 112. The first erase voltage + Ve1 is applied, and a negative second erase voltage -Ve2 is applied to the source region 200. Then, holes captured in the nanocrystals 700 of the first charge trap region 410 are erased through the source region 200, and when the holes are erased, the potential of the channel region 400 becomes relatively low, and thus the threshold The voltage will increase.

6 is a diagram for explaining a process of reading data programmed according to a preferred embodiment of the present invention. As described above, the present invention is capable of multi-bit (2-bit) programming, and therefore, in order to read whether or not it is programmed and in which bit area, it is necessary to perform forward read and reverse read of each bit. First, a case where charge is programmed in the second charge trap region 420 will be described.

In order to read whether the second charge trap region 420 is programmed, the source region 200 is grounded, a positive first read voltage lower than the first program voltage is applied to the gate electrode layer 600, and the drain region ( A forward read voltage is applied to 300 by applying a second read voltage rather than the second program voltage. When the forward read voltage is applied in this way, current may flow through the channel region 400, and the drain current may be measured to determine whether the second charge capture region 420 is programmed.

The drain current is different depending on the amount of accumulated holes present in the channel region 400. For example, when no holes are trapped in the nanocrystal 700 in the channel region 400 (that is, not programmed), a very small current flows and holes in the second charge trapping region 420. When trapped and programmed in the nanocrystals 700, a large drain current flows.

Meanwhile, the drain region 300 is grounded, the first read voltage lower than the first program voltage is applied to the gate electrode layer 600, and the second read voltage is lower than the second program voltage in the source region 200. The reverse read voltage is applied by applying.

In this way, when the reverse read voltage is applied, a drain current that is larger than the current when not programmed in the second charge trap region 420 and smaller than the current when the forward read voltage is applied flows.

The program current of the nonvolatile floating body memory device can be checked by measuring the drain current.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

1 is a cross-sectional view illustrating a conventional single transistor floating body DRAM cell.

2 is a diagram illustrating a structure of a floating body nonvolatile memory device according to an exemplary embodiment of the present invention.

3A to 3E are diagrams illustrating a manufacturing process of a floating body nonvolatile memory device according to an exemplary embodiment of the present invention.

4A and 4B illustrate a process of performing a program on a floating body nonvolatile memory device according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a process of erasing a programmed charge according to a preferred embodiment of the present invention.

6 is a diagram for explaining a process of reading data programmed according to a preferred embodiment of the present invention.

Claims (11)

delete A semiconductor substrate including a buried insulating film therein; A gate insulating film formed from a groove formed on a surface of the semiconductor substrate to protrude from the surface of the semiconductor substrate; A gate electrode layer formed on the gate insulating layer; Source and drain regions formed on both sides of the gate insulating layer below the surface of the semiconductor substrate; And And a channel region formed between the buried insulating film and the gate insulating film and including charge trapping regions therein for trapping charge. The channel region is A first charge trap region formed between the source region and a lower portion of the gate insulating layer to trap holes generated near the source region, and And a second charge trapping region formed between the drain region and a lower portion of the gate insulating layer to trap holes generated in the vicinity of the drain region. The method of claim 2, And the first charge trap region and the second charge capture region are formed of nanocrystals formed by implanting any one of Si, Ge, and Au ions. The method of claim 2, wherein the semiconductor substrate is A first layer formed of a single crystal silicon layer; A second layer on which the buried insulation film is formed; And And a third layer formed of single crystal silicon on the second layer and having the groove, the channel region, the source region, and the drain region formed thereon. (a) forming a groove on the semiconductor substrate including the buried insulating film; (b) forming charge trapping regions on both sides of the groove; (c) forming a gate insulating film from the groove, and forming a gate electrode layer on the gate insulating film; And (d) forming the source region and the drain region such that the charge trap region is located between the gate insulating layer and the source region and between the gate insulating layer and the drain region. Manufacturing method. The method of claim 5, wherein step (a) Doping impurities to form a channel region; And Forming the groove in the center of the channel region. The method of claim 5, wherein the semiconductor substrate A first layer embodied as a single crystal silicon layer; A second layer, which is a buried insulation film formed on the first layer; And And a third layer formed of a single crystal silicon layer on the buried insulating layer, wherein the groove portion is formed in the third layer. The method of claim 6, Step (b) is (b1) performing an ion implantation process on the channel region; And and (b2) performing heat treatment on the semiconductor substrate on which the ion implantation process has been performed to form the charge trap region. The method of claim 8, In the step (b1), the ions implanted through the grooves are positioned in the buried insulating film, and the ions implanted through the regions other than the grooves are located under the third layer, for any one of Si, Ge, and Au. A method of manufacturing a floating body nonvolatile memory device, comprising performing an ion implantation process. The method of claim 9, wherein in step (b2) And heat-treating to form ions disposed under the third layer with nanocrystals, thereby forming a charge trap region composed of nanocrystals. A semiconductor substrate including a buried insulating film therein; A gate insulating film formed from a groove formed on a surface of the semiconductor substrate to protrude from the surface of the semiconductor substrate; A gate electrode layer formed on the gate insulating layer; Source and drain regions formed on both sides of the gate insulating layer below the surface of the semiconductor substrate; A channel region formed between the buried insulating film and the gate insulating film; And a first charge capture region formed between the source region and the gate insulating film, and a second charge capture region formed between the drain region and the gate insulating film, among the channel regions, as a program method of the floating body nonvolatile memory device. , Nanocrystals are formed in the second charge trap region by grounding the source region, applying a first program voltage to the gate electrode layer, and applying a second program voltage to the drain region, thereby forming holes generated in the vicinity of the drain region. Charges are programmed to the second charge trap region by Nanocrystals are formed in the first charge trap region by grounding the drain region, applying a first program voltage to the gate electrode layer, and applying a second program voltage to the source region to form holes generated in the source region. And programming a charge into the first charge trap region by trapping in the first charge trapping region.

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