KR101038984B1 - Sense Amplifier of Semiconductor Memory Apparatus - Google Patents

Abstract

A sense amplifier circuit with improved area efficiency is disclosed. The sense amplifier circuit of the disclosed semiconductor memory device includes a potential difference between a first bit line pair including a first bit line and a second bit line, and a second bit line pair including a third bit line and a fourth bit line. And a sense amplifier array including first and second sense amplifier units configured to sense and amplify the first and second sense amplifier units, respectively. A first data transfer unit connected between the first bit line and the second bit line, and the second sense amplifier unit configured to sense and amplify a potential difference between the second bit line pair, And a second data transfer unit connected between the third and fourth bit lines constituting the two bit line pairs.

Sense amplifier, pitch, area

Description

Sense amplifier circuit of semiconductor memory device {Sense Amplifier of Semiconductor Memory Apparatus}

The present invention relates to a semiconductor memory device, and more particularly to a sense amplifier circuit of a semiconductor memory device.

Among semiconductor memory devices, a DRAM (Dynamic Random Access Memory) device amplifies data stored in a memory cell using a sense amplifier circuit. The arrangement according to the area of the sense amplifier circuit is closely related to the bit line structure.

1 is a circuit diagram of a sense amplifier having an open bit line structure.

As is known, in the open bitline structure, a pair of bitlines is arranged above and below the sense amplifier.

Referring to FIG. 1, first and second sense amplifier units 1 and 2 connected to respective bit line pairs BL2-BL2B and BL0-BL0B are illustrated. Specifically, the first sense amplifier unit 1 includes a first data transfer unit 10, first and second latch units 20a and 20b, and a first equalizing unit 30. The second sense amplifier 2 comprises a second data transfer unit 40, third and fourth latch units 50a and 50b and an equalizing unit 60.

First, when the column select signal Yi is input, the first data transfer unit 10 transfers the signals of the amplified bit line pairs BL2 and BL2B to the data line pairs LIO2 and LIO2B. This first data transfer unit 10 comprises first and second NMOS transistors NM1, NM2.

The first and second latch units 20a and 20b sense sense amplify substantially the potential difference between the pair of bit lines BL2 and BL2B in the sense amplifier. Here, although shown separately, the first and second latch units 20a and 20b are, as is well known, in a cross coupled form consisting of PMOS transistors PM1 and PM2 and NMOS transistors NM6 and NM7. Has an inverter structure.

The first equalizing unit 30 is provided between the first and second latch units 20a and 20b to equalize the first bit line pair BL2 and BL2B to the bit line precharge voltage VBLP. . The first equalizing unit 30 includes third to fifth NMOS transistors NM3-NM5 that are turned on by the bit line equalizing signal BLEQ and connect the first bit line pairs BL2 and BL2B.

Meanwhile, the functions of the second data transfer unit 40, the third and fourth latch units 50a and 50b, the equalizing unit 60, and the first sense amplifier 1, which are respective components of the second sense amplifier 2, are described. Since the functions of each component of the same) are the same, redundant descriptions will be omitted.

As shown in FIG. 1, in the open bit line structure, a data transfer transistor should be connected to each bit line. Thus, four transistors NM8, NM9, NM1, and NM2 connected to the data lines LIO0, LIO0B, LIO2, and LIO2B are arranged side by side in an area where four bit lines BL0, BL0B, BL2, and BL2B are arranged. . That is, four transistors (NM1, NM2, NM8, NM9) must be placed within four bitline pitches, and further four transistors (NM1, NM2, NM8, NM9) and four data lines (or globals). Contacts must be configured to be connected. When the structure considering this area is fixed, it may be repeatedly arranged to form a sense amplifier array.

However, as the degree of integration of semiconductor memory devices increases recently, design rules of semiconductor memory devices become smaller. This also reduces the bit line pitch. Therefore, it is becoming more difficult to arrange the four transistors NM1, NM2, NM8, NM9 within four bit line pitches implemented with minimum line width.

An object of the present invention is to provide a sense amplifier circuit of a semiconductor memory device for improving the area margin.

In order to achieve the technical object of the present invention, the sense amplifier circuit of the present invention according to an embodiment has a phase inverted from each other, the first bit line and the second bit line forming a pair of bit lines, the first and second A sense amplifier unit configured to sense and amplify a potential difference between two bit lines, and a first data transfer unit positioned at one side of the sense amplifier unit and connected to the first bit line to transfer a signal of the first bit line to a first data line And a second data transfer unit positioned on the other side of the sense amplifier unit and connected to the second bit line to transfer a signal of the second bit line to a second data line.

In order to achieve the technical object of the present invention, the sense amplifier circuit of the present invention according to another embodiment, the first bit line, the pair and the third bit line and the fourth bit including a first bit line and a second bit line A sense amplifier array comprising sense amplifier units for sensing and amplifying a potential difference between a pair of second bit lines including a line, and provided at one side of the sense amplifier array and connected to first and third bit lines, respectively, And a first data transfer unit for transferring a signal of a third bit line to the first data line and the third data line, respectively, and the other side of the sense amplifier array, and connected to the second and fourth bit lines, respectively. And a second data transfer unit configured to transfer the signals of the second and fourth bit lines to the second and fourth data lines, respectively.
In addition, the sense amplifier circuit of the semiconductor memory device for achieving another technical problem of the present invention, the first bit line, the pair and the third bit line and the fourth bit line including a first bit line and a second bit line A sense amplifier array including sense amplifier units configured to sense and amplify a potential difference between a pair of second bit lines, the first bit line being provided at one side of the sense amplifier array and constituting the first bit line pair; A first data transfer unit connected between the second bit lines, and a second data transfer unit provided on the other side of the sense amplifier array and connected between the third bit line and the fourth bit line constituting the second bit line pair; 2 includes a data transfer unit.

According to the exemplary embodiment of the present invention, in the sense amplifier circuit having the open bit line structure, an area margin of the sense amplifier circuit portion may be secured by separating and disposing the data transfer transistor. In addition, due to the secured area margin, it is possible to improve the area efficiency of the semiconductor memory device to improve the production yield.

Hereinafter, a semiconductor integrated circuit according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a detailed circuit diagram of a sense amplifier circuit having an open bit line structure according to an embodiment of the present invention.

2, a sense amplifier circuit according to an embodiment of the present invention includes a first data transfer unit A, a second data transfer unit B, and a sense amplifier array C.

According to one embodiment of the present invention, all the data transfer transistors transferred to the data line are separated on both sides with respect to the first and second sense amplifier parts 3 and 4 so as not to be disposed only on one side or the other side. It is possible to reduce the number of transistors that must be implemented within the line pitch.

The sense amplifier array C includes first and second sense amplifier units 3 and 4, and senses and amplifies a potential difference between the first and second bit line pairs BL2-BL2B and BL0-BL0B. The signal names and the arrangement order of the illustrated first bit line pairs BL2 and BL2B and the second bit line pairs BL0 and BL0B are not important and have a meaning of distinguishing different bit line pairs.

The first data transfer unit A is provided at one side of the sense amplifier array C and is connected to a bit line of some of the first and second bit line pairs BL2-BL2B and BL0-BL0B, thereby The signal is delivered to data lines of some of the first and second data line pairs.

The second data transfer unit B is provided on the other side of the sense amplifier array C and connected to the remaining bit lines of the first and second bit line pairs BL2-BL2B and BL0-BL0B, thereby connecting the signals of the connected bit lines. Is transmitted to the remaining data lines of the first and second data line pairs.

First, the first sense amplifier unit 3 of the sense amplifier array C includes a first equalizing unit 120 and a first latch unit 130.

The first equalizing unit 120 equalizes the first bit line pair BL2 and BL2B to the bit line precharge voltage VBLP. That is, the first equalizing unit 120 includes second to fourth NMOS transistors N2-N4 that are turned on by the bit line equalizing signal BLEQ and connect the first bit line pairs BL2 and BL2B. Referring to the operation of the first equalizing unit 120 in detail, the bit line equalizing signal BLEQ of the 1/2 cell power supply voltage VCORE level is received at the gates of the second to fourth NMOS transistors N2-N4. do. At this time, the bit line precharge voltage VBLP is inputted from the common connection node of the third NMOS transistor N3 and the fourth NMOS transistor N4 to adjust the level of the first bit line pair BL2 and BL2B. Equalize to precharge voltage (VBLP) level.

The first latch unit 130 senses and amplifies the potential difference between the first bit line pair BL2 and BL2B. The first latch unit 130 includes PMOS transistors P1 and P2 and NMOS transistors N5 and N6 that are connected in a cross coupled form. Gates of the first PMOS transistor P1 and the fifth NMOS transistor N5, and gates of the second PMOS transistor P2 and the sixth NMOS transistor N6 are connected to the first bit line pair BL2B and BL2, respectively. The potential difference between the first bit line pair BL2 and BL2B is sensed. Thus, the first bit line pair BL2 and BL2B is turned on by the transistors P1, P2, N5 and N6 that are turned on in response to the sensed level of the pullup voltage signal CSP and the pulldown voltage signal CSN. Is amplified.

Subsequently, the second sense amplifier section 4 of the sense amplifier array C also includes a second equalizing unit 150 and a second latch unit 160.

The second equalizing unit 150 equalizes the second bit line pair BL0 and BL0B to the bit line precharge voltage VBLP. That is, the second equalizing unit 150 includes eleventh to thirteenth NMOS transistors N11-N13 that are turned on by the bit line equalizing signal BLEQ and connect the second bit line pairs BL0 and BL0B.

The second latch unit 160 senses and amplifies the potential difference between the second bit line pair BL0 and BL0B. The second latch unit 160 includes third and fourth PMOS transistors P3 and P4 and ninth and tenth NMOS transistors N9 and N10 connected in a cross coupled form. Thus, the second bit line pairs BL0 and BL0B are turned on by the transistors P3, P4, N9 and N10 turned on in response to the sensed level of the pull-up voltage signal CSP and the pull-down voltage signal CSN. Is amplified.

Meanwhile, the first data transfer unit A according to an embodiment of the present invention includes first and second data transfer units 110a and 140a.

The first data transfer unit 110a is connected to the positive bit line BL2 of the first bit line pair BL2 and BL2B, thereby receiving a signal of the connected bit line in response to the column select signal Yi. Transfers to the positive data line LIO2 of (LIO2, LIO2B). This first data transfer unit 110a includes a first NMOS transistor N1. The first NMOS transistor N1 may include a gate receiving the column select signal Yi, a source and a first data line pair LIO2 and LIO2B connected to the positive bit line BL2 of the first bit line pair BL2 and BL2B. And a drain connected to the data line LIO2.

The second data transfer unit 140a is connected to the positive bit line BL0 of the second bit line pair BL0 and BL0B, thereby receiving a signal of the connected bit line in response to the column select signal Yi. Transfers to the positive data line LIO0 of (LIO0, LIO0B). This second data transfer unit 140a includes an eighth NMOS transistor N8. The eighth NMOS transistor N8 is a gate receiving the column select signal Yi, a source and a second data line pair LIO0 and LIO0B connected to the positive bit line BL0 of the second bit line pair BL0 and BL0B. And a drain connected to the positive data line LIO0.

The second data transfer unit B includes third and fourth data transfer units 110b and 140b.

The third data transfer unit 110b is connected to the inverted bit lines BL2B of the first bit line pairs BL2 and BL2B, thereby receiving the signals of the connected bit lines in response to the column select signal Yi. Transfers to the inverting data line LIO2b of (LIO2, LIO2B). This third data transfer unit 110b includes a seventh NMOS transistor N7. The seventh NMOS transistor N7 is a gate receiving the column select signal Yi, a source and a first data line pair LIO2 and LIO2B connected to the inverting bit line BL2B of the first bit line pair BL2 and BL2B. It includes a drain connected to the inversion data line (LIO2b) of.

The fourth data transfer unit 140b is connected to the inverting bit lines BL0b of the second bit line pairs BL0 and BL0B to thereby receive a signal of the connected bit lines in response to the column select signal Yi. Transfers to the inverting data line LIO0b of (LIO0, LIO0B). This fourth data transfer unit 140b includes a fourteenth NMOS transistor N14. The fourteenth NMOS transistor N14 may include a gate receiving the column select signal Yi and a source and second data line pair LIO0 and LIO0B connected to an inverting bit line BL0b of the second bit line pair BL0 and BL0B. It includes a drain connected to the inversion data line (LIO0b) of.

In general, the sense amplifier circuit of the open bit line structure has a data transfer transistor for receiving the column select signal Yi only on one side of the circuit unit, and thus it is very complicated and difficult to implement by the fine design rule.

However, in one embodiment of the present invention, two data transfer units are disposed on both sides with respect to the first and second sense amplifier units 3 and 4, more precisely with respect to the vertical direction of the extension direction of the bit line. By separating them, the number of transistors to be implemented within the same four bit line pitches as before can be reduced.

In more detail, one side of the first sense amplifier 3 is provided with a first data transfer unit 110a, and the other side has a third data transfer unit 110b. That is, it can be seen that the first and third data transfer units 110a and 110b for transmitting signals of the first bit line pair BL2 and BL2B connected to the first sense amplifier 3 are separately disposed at both sides. . Similarly, the second sense amplifier 4 includes a second data transfer unit 110a on one side and a fourth data transfer unit 140b on the other side. Thus, the third and fourth data transfer units 140a and 140b transferring the signals of the second bit line pairs BL0 and BL0B connected to the second sense amplifier unit 4 may be separately disposed at both sides.

In other words, based on the respective sense amplifier units 3 and 4, the transistors that transfer data of the paired bit line pairs BL2, BL2B, BL0, and BL0B of each sense amplifier unit 3 and 4 may be different from each other. It is provided on both sides with respect to the sense amplifier part 3,4. In other words, when referring to the sense amplifier array c, the first and second data transfer units A and B are provided at both sides with respect to the vertical direction of the extension direction of the bit line. Therefore, as described above, since the data transfer transistors are disposed separately on both sides, it is possible to reduce the number of transistors to be implemented within the same bit line pitch.

3 is a detailed circuit diagram of a sense amplifier circuit according to another embodiment of the present invention.

According to another exemplary embodiment of the present invention, the first and second data transfer units D and E are provided at different positions with respect to the vertical direction of the extension direction of the bit line, as in the exemplary embodiment. Unlike the first and second data transfer units D and E, each of the sense amplifier units 5 and 6 is a data transfer unit.

Referring to FIG. 3, a sense amplifier circuit according to another embodiment includes a first data transfer unit D, a second data transfer unit E, and a sense amplifier array C.

The sense amplifier array C includes the first and second sense amplifier units 5 and 6, and senses and amplifies a potential difference between the first and second bit line pairs BL2-BL2B and BL0-BL0B.

The first data transfer unit D is provided on the other side of the sense amplifier array C and is connected to the first bit line pair BL2 and BL2B so that the signal of the connected bit line is connected to the first data line pair LIO2,. LIO2B). The first data transfer unit D includes first and second data transfer units N26 and N27. The first transfer unit N26 is an NMOS transistor, and includes a gate for receiving the column select signal Yi, a source and a first data line pair connected to the positive bit line BL2 of the first bit line pair BL2 and BL2B. And a drain connected to the positive data line LIO2 of the LIO2 and LIO2B. The second transfer unit N27 is an NMOS transistor, and includes a gate for receiving the column select signal Yi, a source and a first data line pair connected to the inversion bit line BL2B of the first bit line pair BL2 and BL2B. And a drain connected to the inversion data line LIO2B of the LIO2 and LIO2B.

The second data transfer unit E is provided at one side of the sense amplifier array C and is connected to the second bit line pair BL0-BL0B to thereby connect the connected bit line signal to the second data line pair LIO0 and LIO0B. To pass. The second data transfer unit E includes third and fourth data transfer units N28 and N29. The third transfer unit N28 is an NMOS transistor, and includes a gate for receiving the column select signal Yi, a source and a second data line pair connected to the positive bit line BL0 of the second bit line pair BL2 and BL2B. And a drain connected to the positive data line LIO0 of the LIO0 and LIO0B. The fourth transfer unit N29 is an NMOS transistor, and includes a gate for receiving the column select signal Yi, a source and a second data line pair connected to an inversion bit line BL0B of the second bit line pair BL0 and BL0B. It includes a drain connected to the inversion data line LIO0B of LIO0 and LIO0B.

Thus, the sense amplifier circuit according to another embodiment of the present invention arranges the independent data transfer units of the sense amplifier units 5 and 6, that is, the first and second transfer units D and E at different positions. Also, in another embodiment of the present invention, two transistors may be implemented within the same pitch of four bit lines as in the exemplary embodiment.

Meanwhile, the first and second sense amplifier parts 5 and 6 of the sense amplifier array C also include respective equalizing units and latch units as in the embodiment. The difference from the instant example is that the pull-up voltage signal (CSP) receiving transistor portion and the pull-down voltage signal (CSN) receiving transistor portion of the latch unit are separately disposed. This is merely illustrative of various arrangement embodiments in consideration of the area efficiency of the layout, but is not limited thereto.

In detail, the pull-up voltage signal CSP receiving transistor 210a and the pull-down voltage signal CSN receiving transistor 210b which are latch units of the first sense amplifier unit 5 are separately disposed. The pull-up voltage signal CSP receiving transistor unit 210a includes PMOS transistors P21 and P22, and the pull-down voltage signal CSN receiving transistor unit 210b includes NMOS transistors N24 and N25. In addition, the equalizing unit 220 of the first sense amplifier unit 5 is interposed between the pull-up voltage signal (CSP) receiving transistor unit 210a and the pull-down voltage signal (CSN) receiving transistor unit 210b. . In this case, the first data transfer unit D is disposed adjacent to the pull-down voltage signal CSN receiving transistor unit 210b.

Similarly, the pull-up voltage signal CSP receiving transistor unit 250b and the pull-down voltage signal CSN receiving transistor unit 250a, which are latch units of the second sense amplifier unit 6, are separately disposed. The pull-up voltage signal CSP receiving transistor unit 250b includes PMOS transistors P23 and P24, and the pull-down voltage signal CSN receiving transistor unit 250a includes NMOS transistors N30 and N31. In addition, the equalizing unit 260 of the second sense amplifier unit 6 is interposed between the pull-up voltage signal (CSP) receiving transistor unit 250b and the pull-down voltage signal (CSN) receiving transistor unit 250a. . In this case, the second transfer unit E is disposed adjacent to the pull-down voltage signal CSN receiving transistor unit 250a.

Thus, the effective resistance is equal by making the arrangement distance between each equalizing unit 220, 260 and each of the first and second data transfer units D, E of the sense amplifier circuit according to another embodiment of the present invention constant. There is a repelling effect.

As described above, according to the exemplary embodiments of the present invention, when transmitting a signal of a pair of bit lines to a data line, an area according to a design rule is disposed by separating the data transfer transistors on both sides based on a vertical direction of an extension direction of the bit line. It is possible to secure margins.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

1 is a circuit diagram of a sense amplifier according to the prior art,

2 is a circuit diagram of a sense amplifier according to an embodiment of the present invention, and

3 is a circuit diagram of a sense amplifier according to another embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

A: first data transfer unit B: second data transfer unit

C: sense amplifier array 110a: first data transfer unit

110b: third data transfer unit 140a: second data transfer unit

140b: fourth data transfer unit

Claims (13)

delete delete delete delete delete delete delete delete delete First and second sense amplifier units for sensing and amplifying a potential difference between a first bit line pair including a first bit line and a second bit line, and a second bit line pair including a third bit line and a fourth bit line, respectively. A sense amplifier array comprising; A first disposed on one side of the first sense amplifier unit that senses and amplifies a potential difference between the first bit line pair, and is connected between the first bit line and the second bit line constituting the first bit line pair A data transfer unit; And Second data disposed on the other side of the second sense amplifier unit that senses and amplifies a potential difference between the second bit line pair, and is connected between the third bit line and the fourth bit line constituting the second bit line pair; A sense amplifier circuit of a semiconductor memory device including a transfer unit. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, The first data transfer unit, A first data transfer unit for transferring a signal of a first bit line of the first bit line pair to a first data line; And And a second data transfer unit configured to transfer a signal of a second bit line of the first bit line pair to a second data line. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, The second data transfer unit, A third data transfer unit for transferring a signal of a third bit line of the second bit line pair to a third data line; And And a fourth data transfer unit configured to transfer a signal of a fourth bit line of the second bit line pair to a fourth data line. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12, The first to fourth data transfer unit, A sense amplifier circuit of a semiconductor memory device, which is a transistor driven in response to a column select signal.

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