KR101027452B1

KR101027452B1 - Wafer edge etching apparatus and method thereof

Info

Publication number: KR101027452B1
Application number: KR1020090085567A
Authority: KR
Inventors: 노길식
Original assignee: (주)케이에스텍
Priority date: 2009-09-10
Filing date: 2009-09-10
Publication date: 2011-04-06
Also published as: KR20110027464A; WO2011030966A1

Abstract

The present invention relates to a wafer edge etching apparatus and a method thereof, the main configuration of the etching apparatus comprises a chamber forming an outer body; A pair of electrodes for generating plasma in the reaction space according to a voltage difference across the two ends; A power supply unit connected to one of the pair of electrodes to generate a voltage difference between the electrodes; A pair of shielding rings projecting on opposite surfaces of the pair of electrodes to partition the wafer so that only its edges are exposed to the reaction space; An insulating gas supply unit supplying an insulating gas to the insulating space formed between the pair of electrodes in the pair of shielding rings; And a process gas supply unit supplying a process gas into the chamber so that the plasma can be generated out of the pair of shielding rings by a voltage difference applied between the pair of electrodes in a state in which the insulating gas is injected into the insulating space. According to the above configuration, the pair of shielding ring is edged by the reaction space where the edge is etched by the plasma and the insulating space where the plasma is not generated by the insulating gas is reliably partitioned, so that edge etching It is possible to prevent the wafer pattern region from being damaged by the plasma.

Wafer, Edge, Etch, Plasma, Shielding Ring

Description

Wafer edge etching apparatus and method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer edge etching apparatus and method thereof, and more particularly, to a wafer edge etching apparatus and an etching method for improving the yield of a semiconductor chip by etching and removing only an edge portion of a wafer used for manufacturing a semiconductor chip. It is about a method.

Silicon wafers are generally designed not to make a separate circuit pattern on the edge portion used for wafer transfer, and thus remove fine defects such as cracks in the deposited portion of the edge portion or unnecessary films generated during the wafer processing process. If the continuous process is not carried out without a process defect occurs there is a problem that the yield of the semiconductor chip is lowered.

In order to solve this problem, the edges have been removed through a conventional etching process. However, this method has a relatively large process, requires expensive equipment such as an exposure machine, and thus a long process time and a manufacturing cost. There was another issue that took too much time.

In addition, there is another edge removal method that heats and vaporizes HF to etch edges. However, this method is a single process, which is difficult to manage and handle HF vapor, which is a dangerous substance despite time and cost efficiency. Noodles are used very limitedly because of unevenness and environmental pollution.

Accordingly, various types of wafer edge etching apparatuses have been developed, and examples thereof include an etching apparatus illustrated in FIG. 1. In the etching apparatus, as shown by the reference numeral 101, the electrode block 105 and the baffle 107 are installed in the chamber 103, the wafer 110 is disposed to be adjacent to the bottom of the baffle 107, and then the baffle ( The process gas is injected through the outer passage 109, and the edge portion is etched by generating the plasma P to the edge portion of the wafer 110 by the electrode block 105.

In this case, an inert gas such as Ar is supplied from the central passage 111 of the baffle 107 to the outside of the baffle 107 to prevent the etching reaction caused by plasma in the edge of the wafer 110, that is, the pattern region. Ar plasma is generated in the shielding region (I) due to the problem that the etching reaction occurs in the pattern region is inevitable.

The present invention has been proposed to solve the problems of the conventional semiconductor wafer edge etching apparatus and method as described above, by mechanically shielding the edge of the wafer to be etched and the pattern region inside the wafer edge where the etching should not occur The purpose of the present invention is to protect the pattern region from the etching reaction caused by plasma of the process gas by reliably partitioning the reaction space where the process gas becomes plasma and the insulation space where plasma is not generated due to the insulation gas.

The present invention to achieve the above object, the chamber forming an outer body; A pair of electrodes installed in the chamber so as to be movable relative to each other so that a plasma can be generated in the reaction space according to a voltage difference across both ends while securing a reaction space at a nearest reaction position; A power supply unit connected to one of the pair of electrodes to generate a voltage difference between the electrodes; A pair of pairs of protrusions projecting on opposite surfaces of the pair of electrodes to contact the wafer when the pair of electrodes are in the reaction position, and partitioning the wafer such that only its edges are exposed to the reaction space; Shielding ring; An insulating gas supply unit supplying an insulating gas to the insulating space formed between the pair of electrodes in the pair of shielding rings; And a process gas supply unit supplying a process gas into the chamber so that the plasma can be generated out of the pair of shielding rings by a voltage difference applied between the pair of electrodes in a state in which the insulating gas is injected into the insulating space. Provided is a wafer edge etching apparatus.

The vacuum pump may further include a vacuum pump for evacuating the inside of the chamber before injecting the insulating gas from the insulating gas supply unit to the insulating space.

In addition, the present invention is a wafer loading step of placing a wafer to be edge-etched on the shielding ring protruding on the opposite surface of any one of the pair of electrodes that are open inside the chamber; In the wafer loading step, when the wafer is placed on the shielding ring, one of the pair of electrodes is moved relative to the other side so that the wafer is brought into contact between the shielding rings. A wafer shielding step of partitioning the reaction space to be exposed to the reaction space; An insulating gas injection step of injecting an insulating gas into an insulating space formed between the pair of electrodes in the pair of shielding rings in contact with the wafer in the wafer shielding step; A process gas injection step of injecting process gas into the chamber while the insulation gas is injected into the insulation space in the insulation gas injection step; And applying a voltage difference between the pair of electrodes while injecting the process gas into the chamber in the process gas injection step, thereby converting the process gas into plasma outside the pair of shielding rings between the pair of electrodes. And an edge etching step of etching the edge portion of the wafer by the plasma generated in this way.

The method may further include a vacuum step of evacuating the inside of the chamber before injecting the insulation gas into the insulation space in the insulation gas injection step.

In addition, the insulation gas is SF ₆ , the process gas is preferably a mixed gas of Ar and CF ₄ .

According to the wafer edge etching apparatus and method thereof of the present invention, when etching the edges of the wafer interposed between the upper and lower electrodes, a plasma is generated to prevent the etching reaction and the reaction space which causes the etching reaction to occur so that the etching reaction does not occur. Since the insulating space can be reliably blocked by a pair of upper and lower shielding rings, no plasma etching occurs in the pattern region inside the edge even while the wafer edge is etched by the plasma generated in the reaction space. As a result, since the pattern area can be protected, it is possible to prevent the degradation of the wafer due to the plasma used for the edge etching.

Hereinafter, a wafer edge etching apparatus according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the wafer edge etching apparatus of the present invention, as shown by reference numeral 1 in FIG. 2, the chamber 3, the pair of electrodes 4 and 5, the power supply unit 6, and the pair of shielding rings 7, 8), the insulating gas supply unit 9, and the process gas supply unit 11, and further comprises a vacuum pump (13).

Here, the chamber 3 is a part forming the outer body of the etching apparatus 1 of the present invention, and makes a sealed space to make the inner space into a vacuum or inject a process gas into the inner space.

In addition, as shown in FIG. 2, the pair of electrodes 4 and 5 generates a plasma P for etching the edge 12 of the wafer 10 interposed therebetween. 3) Bars arranged up and down in the state facing the inside, for example, although not shown, only the electrode plate may be used as it is, and as shown in FIG. 2, the dielectric 25 layer may be disposed on the outside of the electrode plate. It is preferable to use it in the enclosed state.

At this time, the one electrode, for example, the lower electrode 5 can be relatively moved up and down relative to the other electrode, that is, the upper electrode 4 by connecting the movement means such as the hydraulic cylinder 23 to the bottom as shown. On the contrary, the lower electrode 5 may be fixed and the upper electrode 4 may be elevated. Therefore, the upper and lower electrodes 4 and 5 can be spaced apart as shown in FIG. 4, and the upper and lower electrodes 4 and 5 are approached to the nearest reaction position as shown in FIGS. 2 and 5. The wafer 10 may be interposed in contact between the upper shielding ring 7 and the lower shielding ring 8. Accordingly, the pair of upper and lower electrodes 4 and 5 are secured by the reaction space 15 while the electrodes 4 and 5 are driven by a high-voltage alternating voltage transmitted from the power supply 6 to one side, that is, the upper electrode 4. Plasma P can be generated through the process gas G injected into the reaction space 15 according to the voltage difference across both ends.

In addition, as shown in FIG. 2, the power supply unit 6 is connected to one of the pair of electrodes 4 and 5, for example, the upper electrode 4, to apply an alternating voltage of high voltage to the electrode 4. ) And a voltage difference for generating plasma between the electrode 5 is generated.

In addition, as shown in FIG. 2, the pair of shield rings 7 and 8 contact the upper and lower surfaces of the wafer 10 to expose the wafer surface to the reaction space 15 and the insulating space. As a means for dividing into a pattern region exposed by (16), a pair of upper and lower electrodes 4 and 5 protrude in a circle in a parabolic cross-section on opposite surfaces 21 and 22, respectively. Thus, the upper and lower pair of shielding rings 7 and 8 contact the wafer 10 when the pair of electrodes 4 and 5 are in the reaction position, so that the edge 10 of the outer edge portion of the wafer 10 is contacted. By dividing into and inside the pattern region, the insulating space 16 surrounding the pattern region of the wafer 10 serves to shield the edge 12 from the surrounding reaction space 15.

In addition, the insulating gas supply unit 9 supplies the insulating gas I to the insulating space 16 formed between the pair of electrodes 7 and 8 inside the pair of shield rings 7 and 8 as described above. As shown in FIG. 2, the insulating gas is supplied to the insulating space 16 through a supply pipe 27 installed outside the chamber 3 and connected to the upper and lower electrodes 7 and 8, respectively. do. At this time, there are various kinds of insulating gas used, SF ₆ is the most representative of them.

In addition, the process gas supply unit 11 is connected to one side of the chamber 3, as shown in FIG. 2, into the chamber 3, in particular, the process gas into the reaction space 15 between the upper and lower electrodes 4 and 5. (G) is a portion for supplying the voltage difference between the upper and lower electrodes (4, 5) by injecting the process gas (G) into the reaction space (15) while the insulating gas (I) is injected into the insulating space (16) When the process gas (G) is injected into the plasma, the process gas (G) can be plasma-formed. Allow the wafer edge 12 to be etched. At this time, the gas used as the process gas may be of various kinds, but the most representative of them is a mixed gas of Ar and CF _4, the mixing ratio of these is preferably 4: 1, in addition to He, N Gases such as ₂ and O ₂ may be used as process gases.

Meanwhile, as shown in FIG. 2, the vacuum pump 13 is connected to one side of the chamber 3 to inject the insulating gas I from the insulating gas supply unit 9 into the insulating space 16. As a means for evacuating the inside, the process gas (G) is injected into the reaction space (15) and a voltage difference is generated between the electrodes (4, 5) to smoothly process the process gas (G) into a plasma. To be performed.

Now, the operation of the wafer edge etching apparatus 1 according to the preferred embodiment of the present invention configured as described above will be described.

As shown in FIG. 3, a method of etching the edge 12 of the wafer 10 by the wafer edge etching apparatus 1 of the present invention includes a wafer loading step S10, a wafer shielding step S20, and an insulating gas. The injection step (S30), the process gas injection step (S40), and the edge etching step (S50) of the bar, first of all, in the wafer loading step (S10), as shown in Figure 4, the inside of the chamber 3 An edge on a shield ring 8 protruding on one of the pair of open electrodes 4, 5, ie on the other side of the lower electrode 5, ie on the surface 22 opposite the upper electrode. The wafer 10 to be etched (12) is placed.

Then, in the wafer shielding step S20, as shown in FIG. 5, the pair of electrodes 4 and 5 in the state where the wafer 10 is loaded on the lower shielding ring 8 in the wafer loading step S10. ), That is, the lower electrode 5 is pushed toward the other side, that is, the upper electrode 4, so that the wafer 10 is brought into contact between the upper and lower shield rings 7 and 8. At this time, the wafer 10 is exposed to only the portion of the edge 12 to be etched out of the shield rings (7, 8), that is, the reaction space (15).

Then, in the insulating gas injection step (S30), as shown in Figure 6, in the wafer shielding step (S20), the upper and lower electrodes 4, the inside of the upper and lower shield rings (7, 8) in contact with the wafer 10 5) Insulating gas I supplied from the insulating gas supply unit 9 is injected into the insulating space 16 formed therebetween.

Then, in the process gas injection step (S40), as shown in Figure 7, in the insulating gas injection step (S30) in the state injecting the insulating gas (I) in the insulating space 16, the process gas supply unit 11 Open to inject the process gas (G) into the chamber (3). As a result, the process gas G is filled around the edge 12 exposed to the outside of the upper and lower shielding rings 7 and 8.

Next, in the edge etching step (S50), as shown in Figure 2, in the process gas injection step (S40) in the process gas (G) is injected into the chamber 3, the power supply unit 6 is turned on By generating a voltage difference between the upper and lower electrodes 4 and 5, the process gas G filled in the space between the upper and lower electrodes 4 and 5 outside the upper and lower shielding rings 7 and 8, that is, the reaction space 15 is plasma. To be angry. As a result, a portion of the edge 12 of the wafer 10 exposed to the reaction space 15 is etched by the generated plasma P, so that a minute defect such as a crack present in the deposition film of the edge portion or the like occurs during the wafer processing process. Unnecessary films and the like can be removed.

When the etching of the edge portion 12 of the wafer 10 is completed in this way, the power supply is turned off in the reverse order, the supply of the process gas G is stopped, and the hydraulic cylinder 23 is returned to its original state. ) And then release the vacuum and remove the wafer 10 to complete a series of wafer edge etching process.

1 is a front sectional view showing a conventional wafer edge etching apparatus.

2 is a schematic front cross-sectional view of a wafer edge etching apparatus according to the present invention.

3 is a block diagram sequentially showing a wafer edge etching method according to the present invention.

4 is a view for explaining a wafer loading step shown in FIG.

5 is a view for explaining a wafer shielding step shown in FIG.

6 is a view for explaining an insulating gas injection step shown in FIG.

7 is a view for explaining a process gas injection step shown in FIG.

1: wafer edge etching device 3: chamber

4,5: upper and lower electrodes 6: power supply

7,8: upper and lower shielding ring 9: insulated gas supply

10 wafer 11 process gas supply unit

12 edge 13 vacuum pump

15: reaction space 16: insulation space

23: hydraulic cylinder

Claims

An outer chamber 3;

Plasma (P) is installed in the reaction space (15) in accordance with the voltage difference across both ends while being installed in the chamber (3) so as to be movable relative to each other in the opposite state to secure the reaction space (15) at the nearest reaction position. A pair of electrodes 4, 5 to be generated;

A power supply unit 6 connected to one of the pair of electrodes 4 and 5 to generate a voltage difference between the electrodes 4 and 5;

Protrude on the mutually opposing surfaces 21 and 22 of the pair of electrodes 4 and 5, respectively, and contact the wafer 10 when the pair of electrodes 4 and 5 are in the reaction position, A pair of shield rings (7, 8) partitioning the wafer (10) such that only its edge (12) is exposed to the reaction space (15);

An insulation gas supply unit (9) for supplying insulation gas (I) to the insulation space (16) formed between the pair of electrodes (4, 5) inside the pair of shielding rings (7, 8); And

In the state where the insulating gas I is injected into the insulating space 16, the plasma outside the pair of shielding rings 7 and 8 by the voltage difference applied between the pair of electrodes 4 and 5. And a process gas supply unit (11) for supplying a process gas (G) into the chamber (3) so that P) can occur.

According to claim 1,

And a vacuum pump 13 for evacuating the inside of the chamber 3 before injecting the insulating gas I from the insulating gas supply unit 9 to the insulating space 16. Etching device.

The edge 12 is etched on the shield ring 7 or 8 protruding on the opposing surface 21 or 22 of either of the pair of electrodes 4, 5 which are open inside the chamber 3. A wafer loading step (S10) on which the wafer 10 to be placed;

In the wafer loading step S10, one of the pairs of electrodes 4 and 5 is placed on the other side 4 while the wafer 10 is placed on the shield ring 7 or 8. A wafer shielding step in which the wafer 10 is brought into contact between the shielding rings 7 and 8 by moving relative to each other, and partitions the wafer 10 so that only the edge 12 is exposed to the reaction space 15. (S20);

Insulating into the insulating space 16 formed between the pair of electrodes 4 and 5 inside the pair of shield rings 7 and 8 to which the wafer 10 is in contact in the wafer shielding step S20. Insulating gas injection step (S30) for injecting the gas (I);

A process gas injection step (S40) of injecting a process gas (G) into the chamber (3) while the insulation gas (I) is injected into the insulation space (16) in the insulation gas injection step (S30); And

In the process gas injection step (S40), a voltage difference is applied between the pair of electrodes 4 and 5 in a state in which the process gas G is injected into the chamber 3. The process gas (G) is made into a plasma outside the pair of shield rings (7, 8) between the edges (5) and the edge (12) of the wafer (10) by the generated plasma (P). Edge etching step of etching a portion (S50); Wafer edge etching method comprising a.

The method of claim 3,

And a vacuum step (S60) for evacuating the inside of the chamber (3) before injecting the insulating gas (I) into the insulating space (16) in the insulating gas injection step (S30). Wafer edge etching method.

The method according to claim 3 or 4,

The insulation gas (I) is SF ₆ , the process gas (G) is a wafer edge etching method, characterized in that the mixed gas of Ar and CF ₄ .