KR101024255B1 - Method for fabricating dual polysilicon gate - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can uniformly improve the profile of the gate pattern of the NMOS and PMOS by improving the etching rate of the N-type polysilicon and P-type polysilicon when forming the dual polysilicon gate, The present invention provides a method comprising: providing a substrate having an NMOS and a PMOS; Forming an N-type polysilicon film and a P-type polysilicon film on the NMOS and PMOS substrates, respectively; Stacking a gate electrode metal film and a gate hard mask film on the N-type and P-type polysilicon films; Patterning the gate hard mask layer and the gate electrode metal layer to expose the N-type and P-type polysilicon layers; Counter doping the exposed P-type polysilicon film with N-type impurities to form an N-type polysilicon film; Etching the N-type polysilicon layer using the gate hard mask layer as an etch barrier to form a gate pattern having a uniform profile in the NMOS and the PMOS, and as the etching rate of the PMOS increases, an etching margin is secured, and the metal Etching process margins are improved by improving etching profile problems such as bowing of electrodes, slanting profiles and loading of polysilicon films.

 Dual polysilicon, ion implantation, etching rate

Description

Dual polysilicon gate manufacturing method {METHOD FOR FABRICATING DUAL POLYSILICON GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing dual polysilicon gates.

Currently, a process of forming a dual poly gate is used in the DRAM process to develop high speed and high speed / low power products.

As the P-type polysilicon process through boron ion implantation is added, compared to the conventional single poly gate process, many issues arise in the etching process for forming the gate structure.

Typically, there is a problem in that a non-uniform profile is formed by an etching rate difference between N-type polysilicon and P-type polysilicon during polysilicon etching of the peripheral region.

Furthermore, barrier metal is applied between polysilicon and the upper gate electrode to improve problems such as boron penetration and depletion when forming P-type polysilicon, and an etching process for forming a gate pattern is performed. In case of etching at the same time, profile control is more difficult.

1A and 1B are TEM photographs for comparing the etching rates of N-type polysilicon and P-type polysilicon. 1A and 1B are profiles when etching a gate pattern under the same conditions.

As shown in FIGS. 1A and 1B, after etching a tungsten electrode and using an etching gas containing chlorine (Cl) gas to etch the lower barrier metal and the polysilicon film, the etch rate of the N-type polysilicon becomes While it is about 10 times faster than undoped polysilicon, the etch rate of P-type polysilicon is reduced by 1/2 compared to undoped polysilicon.

This is because the Fermi-Level of polysilylcon is increased by the phosphorus (P) or arsenic (AS) dopant doped with polysilicon, which lowers the energy barrier to electron transition to chemically bound chlorine. .

Accordingly, the N-type polysilicon has a vertical profile and a high etching rate, whereas the P-type polysilicon stops etching in the polysilicon film after the barrier metal etching, and the bowing of the tungsten electrode, the inclined profile of the polysilicon, Problems such as increased loading occur.

The present invention has been proposed to solve the above-described problems of the prior art, and improves the etch rate of N-type polysilicon and P-type polysilicon when forming dual polysilicon gates to uniformly improve the profile of gate patterns of NMOS and PMOS. It is an object of the present invention to provide a method for manufacturing a dual polysilicon gate.

A dual polysilicon gate manufacturing method of the present invention for achieving the above object comprises the steps of providing a substrate having an NMOS and PMOS; Forming an N-type polysilicon film and a P-type polysilicon film on the NMOS and PMOS substrates, respectively; Stacking a gate electrode metal film and a gate hard mask film on the N-type and P-type polysilicon films; Patterning the gate hard mask layer and the gate electrode metal layer to expose the N-type and P-type polysilicon layers; Counter doping the exposed P-type polysilicon film with N-type impurities to form an N-type polysilicon film; And etching the N-type polysilicon layer using the gate hard mask layer as an etch barrier.

In particular, the gate electrode metal film may include tungsten, and the gate hard mask film may include a nitride film.

In addition, the patterning of the gate hard mask film and the metal film for the gate electrode and the etching of the N-type polysilicon film may be performed in any one plasma apparatus selected from the group consisting of ECR, ICP, and CCP. .

In addition, the etching of the N-type polysilicon film may include: firstly etching the N-type polysilicon film; Forming a capping film along a step of the entire structure including the N-type polysilicon film; And etching the remainder of the N-type polysilicon layer using the gate hard mask layer as an etch barrier.

In addition, the capping film is characterized in that it comprises a nitride film.

In addition, the etching of the N-type polysilicon film may be performed using an etching gas containing chlorine.

The above-described method for manufacturing a dual polysilicon gate according to the present invention has a gate pattern having a uniform profile in NMOS and PMOS by counter-doping N-type impurities into a P-type polysilicon film to be etched when the gate pattern is formed, thereby converting it into an N-type polysilicon film. To form.

In addition, as the etching speed of the PMOS increases, an etching margin is secured.

In addition, the etching process margins are improved by improving the etching profile problems such as bowing of the metal electrode, tilt profile and loading of the polysilicon film.

In addition, as the ion implantation is partially performed only on the portion to be etched, only the etching rate may be selectively increased without unnecessary effects on device characteristics.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

(Example 1)

2A to 2D are cross-sectional views illustrating a method of manufacturing a dual polysilicon gate according to a first embodiment of the present invention.

As shown in FIG. 2A, the gate insulating layer 12 is formed on the substrate 11 provided with the NMOS and the PMOS. The substrate 11 is a semiconductor (silicon) substrate on which the DRAM process proceeds, and the gate insulating film 12 is preferably formed of an oxide film. The gate insulating film 12 may be formed of a thermal oxide film or a plasma oxide film.

Subsequently, an N-type polysilicon film 13A is formed in the NMOS on the gate insulating film 12, and a P-type polysilicon film 13B is formed in the PMOS. The dual polysilicon film is formed by first forming an N-type polysilicon film on the entire surface of the substrate 11, then forming a mask pattern for opening the PMOS, and selectively doping P-type impurities into the N-type polysilicon film of the PMOS. Can be formed. Alternatively, after the undoped polysilicon film is formed on the substrate 11, each mask pattern for opening the NMOS or the PMOS may be formed and doped with N-type or P-type impurities. In addition, it can be formed by any method of forming a dual polysilicon film.

Subsequently, a barrier metal 14, a gate electrode metal film 15, and a gate hard mask film 16 are laminated on the N-type and P-type polysilicon films 13A and 13B. For the resistance of the gate electrode, the gate electrode metal film 15 is preferably formed of tungsten. In addition, the gate hard mask film 16 may be formed of a nitride film.

Subsequently, a hard mask film 17 is formed on the gate hard mask film 16, and a photosensitive film pattern 18 is formed on the hard mask film 17. The hard mask layer 17 is used to secure an etching margin when the gate pattern is formed. The hard mask layer 17 is formed of a carbon-based material, but preferably formed of amorphous carbon. In addition, an anti-reflection film may be formed before the photoresist pattern 18 is formed.

As illustrated in FIG. 2B, the hard mask film 17 (see FIG. 2A) is etched using the photoresist pattern 18 (see FIG. 2A) as an etch barrier, and the hard mask film 17 is etched by the gate hard mask film (see FIG. 2A). 16, see FIG. 2A). The etching of the gate hard mask layer 16 may be performed in any one plasma apparatus selected from the group consisting of ECR, ICP, and CCP.

Subsequently, the gate electrode metal film 15 (see FIG. 2A) and the barrier metal 14 (see FIG. 2A) are etched to expose the N-type and P-type polysilicon films 13A and 13B.

The etching of the gate electrode metal film 15 and the barrier metal 14 may be performed in the same chamber as the etching of the gate hard mask pattern 16A, but may be performed in any one plasma apparatus selected from the group consisting of ECR, ICP, and CCP. Can be.

The photoresist pattern 18 and the hard mask layer 17 may be removed after the gate hard mask layer 16 is etched or removed after the etching of the barrier metal 14 is completed. The photoresist pattern 18 and the hard mask layer 17 may be removed by dry etching, but may be removed by an oxygen strip process.

Hereinafter, the etched gate hard mask layer 16 is referred to as a 'gate hard mask pattern 16A', and the etched gate electrode metal layer 15 is referred to as a 'metal electrode 15A' and the barrier metal 14 is formed. This is called a "barrier metal pattern 14A".

As shown in Fig. 2C, the exposed P-type polysilicon film 13B is counter-doped with N-type impurities to be replaced with the N-type polysilicon film 13A. At this time, since the gate hard mask pattern 16A serves as an ion implantation barrier and the portion used as the gate electrode is not doped, the P-type polysilicon film 13B remains as it is.

It is preferable to use phosphorus (P) or arsenic (As) as the N-type impurity, and the doping treatment is performed on the entire surface of the substrate 11, but the region to operate as the actual gate pattern is not doped by the gate hard mask pattern 16A. Therefore, it does not affect device characteristics. In addition, since the P-type polysilicon film 13B of the PMOS is counter-doped to be changed to the N-type polysilicon film 13A in the exposed area, it is relatively compared with the P-type polysilicon film 13B during subsequent polysilicon film etching. Etch rate characteristics are faster.

As illustrated in FIG. 2D, a gate pattern is formed by etching the N-type polysilicon film 13A having the gate hard mask pattern 16A exposed as an etch barrier. The etching of the N-type polysilicon film 13A is performed in the same chamber as the etching of the metal electrode 15A, the barrier metal pattern 14A, and the etching of the gate hard mask pattern 16A, but is a group consisting of ECR, ICP, and CCP. It may proceed in any one of the plasma equipment selected from.

The etching of the N-type polysilicon film 13A is preferably performed using an etching gas containing chlorine (Cl).

In the case of using an etching gas containing chlorine, the N-type and P-type polysilicon films 13A and 13B have different etching rates, respectively, and the portions to be etched by ion implantation in FIG. 2C are all N-type polysilicon films 13A. ), The etching rate of the NMOS and the PMOS can be the same, and the etching can proceed at a uniform speed. Thus, it is possible to form dual polysilicon gates having a uniform profile.

In addition, as the etching speed of the PMOS increases, an etching margin may also be secured. That is, the N-type polysilicon film 13A is about 10 times faster than the undoped polysilicon, whereas the etch rate of the P-type polysilicon film 13B is reduced to 1/2 compared to the undoped polysilicon, so P By counter-doping the type polysilicon film 13B with the N-type polysilicon film 13A, the etching rate of the polysilicon film in the PMOS is increased by about 20 times.

In addition, the etching process margin is improved by improving the etching profile problems such as bowing of the metal electrode 15A and the tilting profile and loading of the polysilicon film generated by the slow etching speed of the P-type polysilicon film 13B. It can be improved.

In addition, as the ion implantation is partially performed only on the portion to be etched, only the etching rate may be selectively increased without unnecessary effects on device characteristics.

In the PMOS, the portion used as the gate electrode is not doped by the gate hard mask pattern 16A and the P-type polysilicon film 13B remains as it is, whereby the P-type polysilicon electrode 13D and the barrier metal pattern 14A. A gate pattern having a stacked structure of the metal electrode 15A and the gate hard mask pattern 16A is formed.

In the NMOS, a gate pattern having a stacked structure of an N-type polysilicon electrode 13C, a barrier metal pattern 14A, a metal electrode 15A, and a gate hard mask pattern 16A is formed.

(Example 2)

3A to 3E are cross-sectional views illustrating a method of manufacturing a dual polysilicon gate according to a second embodiment of the present invention.

As shown in FIG. 3A, the gate insulating layer 22 is formed on the substrate 21 provided with the NMOS and the PMOS. The substrate 21 is a semiconductor (silicon) substrate on which the DRAM process proceeds, and the gate insulating film 22 is preferably formed of an oxide film. The gate insulating film 22 may be formed of a thermal oxide film or a plasma oxide film.

Subsequently, an N-type polysilicon film 23A is formed on the gate insulating film 22 in the NMOS, and a P-type polysilicon film 23B is formed in the PMOS. The dual polysilicon film first forms an N-type polysilicon film on the entire surface of the substrate 21, then forms a mask pattern for opening the PMOS, and selectively counter-dopes P-type impurities to the N-type polysilicon film of the PMOS. Can be formed. Alternatively, after the undoped polysilicon film is formed on the substrate 21, each mask pattern for opening the NMOS or the PMOS may be formed and doped with N-type or P-type impurities. In addition, it can be formed by any method of forming a dual polysilicon film.

Subsequently, a barrier metal 24, a gate electrode metal film 25, and a gate hard mask film 26 are laminated on the N-type and P-type polysilicon films 23A and 23B. The gate electrode metal film 25 is preferably formed of tungsten for resistance of the gate electrode. In addition, the gate hard mask film 26 may be formed of a nitride film.

Subsequently, a hard mask film 27 is formed on the gate hard mask film 26, and a photosensitive film pattern 28 is formed on the hard mask film 27. The hard mask layer 27 is used to secure an etching margin when forming the gate pattern. The hard mask layer 27 is formed of a carbon-based material, but preferably formed of amorphous carbon. In addition, an anti-reflection film may be formed before the photoresist pattern 28 is formed.

As shown in FIG. 3B, the hard mask layer 27 (see FIG. 3A) is etched using the photoresist pattern 28 (see FIG. 3A) as an etch barrier, and the hard mask layer 27 is etched by the gate hard mask layer as the etch barrier (see FIG. 3A). 26, see FIG. 3A). The etching of the gate hard mask layer 26 may be performed in any one plasma apparatus selected from the group consisting of ECR, ICP, and CCP.

Subsequently, the gate electrode metal film 25 (see FIG. 3A) and the barrier metal 24 (see FIG. 3A) are etched to expose the N-type and P-type polysilicon films 23A and 23B.

The etching of the gate electrode metal layer 25 and the barrier metal 24 may be performed in the same chamber as the etching of the gate hard mask pattern 26A, but may be performed in any one plasma apparatus selected from the group consisting of ECR, ICP, and CCP. Can be.

The photoresist pattern 28 and the hard mask layer 27 may be removed after the gate hard mask layer 26 is etched or removed after the etching of the barrier metal 24 is completed. The photoresist pattern 28 and the hard mask layer 27 may be removed by dry etching, but may be removed by an oxygen strip process.

Hereinafter, the etched gate hard mask layer 26 is referred to as a 'gate hard mask pattern 26A', and the etched gate electrode metal layer 25 is referred to as a 'metal electrode 25A' and the barrier metal 24 is used. This is called a "barrier metal pattern 24A".

As shown in Fig. 3C, the exposed P-type polysilicon film 23B is counter-doped with N-type impurities to be replaced with the N-type polysilicon film 23A. At this time, since the gate hard mask pattern 26A serves as an ion implantation barrier and the portion used as the gate electrode is not doped, the P-type polysilicon film 23B remains as it is.

It is preferable to use phosphorus (P) or arsenic (As) as the N-type impurity, and the doping treatment is performed on the entire surface of the substrate 21. However, the region to operate as the actual gate pattern is not doped by the gate hard mask pattern 26A. Therefore, it does not affect device characteristics. In addition, since the P-type polysilicon film 23B of the PMOS is counter-doped to be converted to the N-type polysilicon film 23A among the exposed areas, it is relatively compared with the P-type polysilicon film 23B during subsequent polysilicon film etching. Etch rate characteristics are faster.

As shown in FIG. 3D, the N-type polysilicon film 23A having the gate hard mask pattern 26A exposed as an etch barrier is partially etched.

Subsequently, the capping film 29 is formed along the step of the entire structure including the N-type polysilicon film 23A. The capping film 29 is for preventing abnormal oxidation of the metal electrode 25A by a high temperature thermal process such as subsequent gate reoxidation, and is preferably formed of a nitride film.

Since both NMOS and PMOS etch the N-type polysilicon film 23A, the etching speed is the same, so that the first partial etching may be performed with a uniform profile.

As shown in FIG. 3E, the gate hard mask pattern 26A is etched to form a gate pattern by second etching the remainder of the N-type polysilicon film 23A. At this time, the capping layer 29A formed on the N-type polysilicon layer 23A is etched together and remains in a form surrounding the gate pattern.

The primary and secondary etching of the N-type polysilicon film 23A is performed in the same chamber as the etching of the metal electrode 25A, the barrier metal pattern 24A and the etching of the gate hard mask pattern 26A, but the ECR and ICP And it can proceed in any one of the plasma equipment selected from the group consisting of CCP.

In addition, the primary and secondary etching of the N-type polysilicon film 23A is preferably performed using an etching gas containing chlorine (Cl).

In the case of using an etching gas containing chlorine, the N-type and P-type polysilicon films 23A and 23B have different etching rates, respectively, and the portions to be etched by ion implantation in FIG. 3C are all N-type polysilicon films 23A. ), The etching rate of the NMOS and the PMOS can be the same, and the etching can proceed at a uniform speed. Thus, it is possible to form dual polysilicon gates having a uniform profile.

In addition, as the etching speed of the PMOS increases, an etching margin may also be secured. That is, the N-type polysilicon film 23A is about 10 times faster than the undoped polysilicon, whereas the etch rate of the P-type polysilicon film 23B is reduced to 1/2 compared to the undoped polysilicon, so P By counter-doping the type polysilicon film 23B with the N-type polysilicon film 23A, the etching rate of the polysilicon film is increased by about 20 times in the PMOS.

In addition, the etching process margin is improved by improving the etching profile problems such as bowing of the metal electrode 25A and the tilting profile and loading of the polysilicon film caused by the slow etching speed of the P-type polysilicon film 23B. It can be improved.

In addition, as the ion implantation is partially performed only on the portion to be etched, only the etching rate may be selectively increased without unnecessary effects on device characteristics.

In the PMOS, the portion used as the gate electrode is not doped by the gate hard mask pattern 26A and the P-type polysilicon film 23B remains as it is, whereby the P-type polysilicon electrode 23D and the barrier metal pattern 24A. A gate pattern having a stacked structure of the metal electrode 25A and the gate hard mask pattern 26A is formed.

In the NMOS, a gate pattern having a stacked structure of an N-type polysilicon electrode 23C, a barrier metal pattern 24A, a metal electrode 25A, and a gate hard mask pattern 26A is formed.

Furthermore, since the capping film surrounds the metal electrode 25A, abnormal oxidation of the metal electrode 25A can be prevented during a high temperature thermal process such as subsequent gate reoxidation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are TEM photographs for comparing the etch rate of N-type polysilicon and P-type polysilicon,

2A to 2D are cross-sectional views illustrating a method for manufacturing a dual polysilicon gate according to a first embodiment of the present invention;

3A to 3E are cross-sectional views illustrating a method for manufacturing a dual polysilicon gate according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11 substrate 12 gate insulating film

13A: N-type polysilicon film 13B: P-type polysilicon film

14 barrier metal 15 metal film for gate electrode

16: gate hard mask film 17: hard mask film

18: photosensitive film pattern

Claims (6)

Providing a substrate having an NMOS and a PMOS; Forming an N-type polysilicon film and a P-type polysilicon film on the NMOS and PMOS substrates, respectively; Stacking a gate electrode metal film and a gate hard mask film on the N-type and P-type polysilicon films; Patterning the gate hard mask layer and the gate electrode metal layer to expose the N-type and P-type polysilicon layers; Counter doping the exposed P-type polysilicon film with N-type impurities to form an N-type polysilicon film; And Etching the N-type polysilicon layer using the gate hard mask layer as an etch barrier Dual polysilicon gate manufacturing method comprising a. The method of claim 1, The gate electrode metal film may include tungsten, and the gate hard mask layer may include a nitride film. The method of claim 1, Patterning the gate hard mask layer and the metal layer for the gate electrode and etching the N-type polysilicon layer include: A method of manufacturing dual polysilicon gates in any one of the plasma equipment selected from the group consisting of ECR, ICP and CCP. The method of claim 1, Etching the N-type polysilicon film, Primary etching the N-type polysilicon film; Forming a capping film along a step of the entire structure including the N-type polysilicon film; Second etching the remaining portion of the N-type polysilicon layer using the gate hard mask layer as an etch barrier Dual polysilicon gate manufacturing method comprising a. The method of claim 4, wherein Dual polysilicon gate manufacturing method including the capping film nitride film. The method according to claim 1 or 4, Etching the N-type polysilicon film, A method of manufacturing dual polysilicon gates using an etching gas containing chlorine.

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