KR101022282B1 - 3? graphic accelerator and 3? graphic accelerating method - Google Patents

Abstract

The present invention relates to a three-dimensional graphics acceleration device and a three-dimensional graphics acceleration method, the three-dimensional graphics acceleration device according to the present invention, as the pixel information to be displayed, at least one or more depth information, color information, and stencil-alpha information A frame memory to be stored, a per-fragment unit that performs at least one depth test, color conversion, and stencil operation-alpha test on a current fragment, depth information, color information, and an area corresponding to the current fragment; Dual port cache memory capable of reading and storing stencil-alpha information from the frame memory, and capable of reading and writing at the same clock, and depth testing, color conversion, or the like for the current fragment from the per-fragment unit. The string for performing stencil arithmetic-alpha test If there is a request for depth information, color information, or stencil-alpha information on an area corresponding to the ash fragment, the dual port cache memory reads and outputs the requested information, and the request information is stored in the dual port cache memory. If not present, the cache controller reads from the frame memory and stores in the dual port cache memory, thereby reducing the stall of the graphics pipeline, thereby improving the performance of the pipeline.

Description

3D GRAPHIC ACCELERATOR AND 3D GRAPHIC ACCELERATING METHOD}

The present invention relates to a three-dimensional graphics acceleration device and a three-dimensional graphics acceleration method, and more particularly, to a three-dimensional graphics acceleration device and a three-dimensional graphics acceleration method using a dual port cache memory.

Three-dimensional graphics technology is a technology that visualizes the shape, color, and motion of an object located in three-dimensional space. In particular, three-dimensional objects are expressed using three axes of height, width, and length. It is the technology displayed on the screen.

The series of processing performed by the three-dimensional graphics accelerator is called the graphics pipeline. If any part of the processing in the graphics pipeline is late, the entire pipeline slows down.

1 is a block diagram showing a process of processing a general three-dimensional graphic.

As shown in FIG. 1, the three-dimensional graphics processing process includes a three-dimensional graphics pipeline 130 for three-dimensional graphics data sent by the three-dimensional application software 110 through an application program interface (API) 120. After performing the real-time hardware acceleration in the process of outputting to the display unit 140.

On the other hand, the 3D graphics pipeline 130 is largely provided with a geometry processing unit 132 and a rendering processing unit 134. The geometry processor 132 mainly converts an object of a 3D coordinate system according to a viewpoint and projects it into a 2D coordinate system, and the rendering processor 134 determines a color value of an image of the 2D coordinate system and displays the display unit ( The process is stored in the frame memory 142 of the 140. After the processing of all three-dimensional data input for one frame is finished, color values and the like stored in the frame memory 142 of the display 140 are displayed on a monitor (not shown). On the other hand, the calculation amount in the geometry processing unit 132 is proportional to the number of vertices of the polygon to be processed, and the calculation amount in the rendering processing unit 134 is proportional to the number of pixels to be generated.

3D graphics are mainly composed of points, lines, or triangles, and most 3D rendering processing units 134 have a structure of processing triangles at high speed. Recently, when rendering a real-time scene in a three-dimensional graphics application such as the three-dimensional graphics pipeline 130, various textures and various color blending methods are used to obtain a more natural and smooth image. On the other hand, since the perfragment unit accesses a lot of the frame memory 142 of the display unit 140, it has the greatest influence on the improvement of the performance of the 3D graphics pipeline 130. Thus, when the 3D graphics pipeline 130 accesses the external frame memory 142, the cache memory is prevented from lengthening the stall of the 3D graphics pipeline 130 due to the long latency. Is used.

However, the conventional cache memory is a single port cache memory and cannot simultaneously read and write. Therefore, the stall in the three-dimensional graphics pipeline 130 is still long, so the performance of the three-dimensional graphics pipeline 130 is degraded.

In order to solve the above problems, an object of the present invention is to provide a three-dimensional graphics acceleration device and a three-dimensional graphics acceleration method using a dual port cache memory to reduce the stall of the pipeline in the per-fragment unit.

Another object of the present invention is to provide a three-dimensional graphics accelerator and a three-dimensional graphics acceleration method using the same clock in the pipeline and dual port cache memory of the three-dimensional graphics accelerator to reduce time loss.

It is also an object of the present invention to provide a three-dimensional graphics acceleration device and a three-dimensional graphics acceleration method including a cache controller having a coordinator for efficiently storing the data of the dual port cache memory to an external frame memory.

In order to solve the above-mentioned problems, the three-dimensional graphics acceleration device according to the present invention, as pixel information to be displayed, a frame memory for storing at least one or more depth information, color information, and stencil-alpha information in the present fragment, A per-fragment unit that performs at least one depth test, a color conversion, and a stencil arithmetic-alpha test, and depth information, color information, and stencil-alpha information about an area corresponding to the current fragment, from the frame memory. Dual port cache memory capable of reading and storing, and also capable of reading and writing on the same clock, and for performing depth tests, color conversion or stencil arithmetic-alpha tests on the current fragment from the perfragment unit. For an area corresponding to the current fragment When there is a request for this information, color information, or stencil-alpha information, if there is request information in the dual port cache memory, the corresponding information is read and outputted. If there is no request information in the dual port cache memory, the request is read from the frame memory. Provides a cache controller that stores in dual-port cache memory.

The cache controller includes a coordinator section having a high speed logic circuit for adjusting priority when two or more of depth information, color information, or stencil-alpha information of the dual port cache memory are simultaneously written to the frame memory. It is desirable to.

The coordinator unit includes a coordinator for determining a priority, an address mux for selecting and outputting one from address lines of depth information, color information, or stencil-alpha information of the dual port cache memory under control of the coordinator; It is preferable to include a data mux to select one of the data line of the depth information, color information, or stencil-alpha information of the dual-port cache memory under the control of.

Preferably, the coordinator unit gives priority to the color information, depth information, and stencil-alpha information of the dual port cache memory and outputs the priority to the write bus.

The dual port cache memory is preferably SRAM (Static RAM).

Preferably, the dual port cache memory and the perfragment unit use the same clock.

Preferably, the cache controller further includes a tag field for managing the dual port cache memory, and an LRU algorithm for block replacement of the dual port cache memory.

In order to solve the above problems, the three-dimensional graphics acceleration method according to the present invention is a pixel memory to be displayed, the frame memory for storing at least one or more depth information, color information, and stencil-alpha information, and for the current fragment A per-fragment unit that performs at least one depth test, color conversion, and stencil arithmetic-alpha test, and depth information, color information, and stencil-alpha information for an area corresponding to the current fragment are read from the frame memory. A three-dimensional graphics acceleration method using a graphics accelerator having a dual port cache memory capable of storing and reading and writing at the same clock, the depth test of the current fragment from the perfragment unit, color Transform or Stencil Arithmetic-Alpha Testing If depth information, color information, or stencil-alpha information of a region corresponding to the current fragment is requested for a row, reading and outputting the requested information if the request information is present in the dual port cache memory; and If there is no request information in the dual port cache memory, a step of reading from the frame memory and storing in the dual port cache memory is provided.

The method may further include adjusting priorities when two or more of depth information, color information, or stencil-alpha information of the dual port cache memory are simultaneously written to the frame memory.

If there is no request information in the dual port cache memory, it is preferable to check whether the update bit of the oldest block tag is set and to store the data of the oldest block in the frame memory if the update bit is set.

According to the above-described configurations, the present invention can improve the performance of the pipeline by reducing the stall of the graphics pipeline by separately providing the input port and the output port and enabling continuous read or write simultaneously with the same clock. .

In addition, the present invention can reduce time loss by using the same clock for the dual port cache memory and the graphics pipeline, thereby improving the performance of the graphics pipeline.

In addition, the present invention can efficiently store data in the dual port cache memory into the external frame memory by use of the coordinator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an apparatus for accelerating 3D graphics according to an embodiment of the present invention.

As shown in FIG. 2, the 3D graphics accelerator 200 may include a frame memory 210, an AXI BUS MATRIX 220, a perfragment unit 230, and a dual port for rendering a real-time scene in a 3D graphics application. Cache memory 240 and cache controller 250.

The frame memory 210 stores pixel information to be displayed on the LCD screen 20 through the LCD controller 10. In particular, the frame memory 210 stores at least one of depth information, color information, and stencil-alpha information related to rendering of a real-time scene as pixel information to be displayed.

The AXI BUS MATRIX 220 is a bus matrix that connects a number of peripheral modules and operates at a high frequency, and is a bus matrix using the Advanced eXtensible Interface (AXI) protocol.

Perfragment unit 230 performs at least one depth test, color conversion, and stencil-alpha blending on the current fragment. Generally, fragments mean pixels, but they can be defined and used in other units. In FIG. 2, although only the perfragment unit 230 is illustrated as a three-dimensional graphics pipeline, it may further include a geometry engine, a raster riser, a fragment shader, and a texture unit.

The dual port cache memory 240 is a cache memory capable of a read function and a write function at the same clock, and includes depth information, color information, and stencil-alpha for an area corresponding to the current fragment read from the frame memory 210. Stores information or stores depth information, color information, or stencil-alpha information of the current fragment according to the depth test, color conversion, or stencil-alpha blending for the current fragment in the perfragment unit 230. In addition, the dual port cache memory 240 may operate synchronously or asynchronously, and is preferably SRAM (Static RAM).

The dual port cache memory 240 also uses the same clock as the clock of the perfragment unit 230 for read / write to eliminate time loss.

That is, according to the present invention, by using the dual port cache memory 240 as the cache memory, the read function and the write function may be simultaneously performed on the dual port cache memory 240 at the same clock. That is, the read request from the perfragment unit 230 is performed independently of the write request to the dual port cache memory 240.

The cache controller 250 is a part that caches data of the frame memory 210 for 3D graphic rendering. That is, the cache controller 250 may perform the depth test, the color information, or the depth information on the area corresponding to the current fragment to perform the depth test, the color conversion, or the stencil-alpha blending on the current fragment from the per fragment unit 230. If there is a request for stencil-alpha information, the dual port cache memory 240 reads the requested information and outputs the information, and if there is no request information in the dual port cache memory 240, reads from the frame memory 210 and the dual port. Stored in the cache memory 210. In addition, the cache controller 250 may determine the depth information, the color information, or the stencil-alpha information of the current fragment according to the depth test, the color conversion, or the stencil-alpha blending for the current fragment in the per-fragment unit 230. Store in dual port cache memory 240

In addition, the cache controller 250 further includes a tag field 252 for managing the dual port cache memory 240, and also has a Least Recently (LRU) for block replacement of the dual port cache memory 240. Used) algorithm.

In addition, the cache controller 250 includes an AXI read port 252, an AXI write port 254, and an adjuster unit 256.

The AXI read port 252 is a port for reading data from the frame memory 210 and updating it to the dual port cache memory 240.

The AXI write port 254 is a port for reading the data of the dual port cache memory 240 updated according to the rendering process of the perfragment unit 230 and storing the data in the frame memory 210.

The adjuster unit 256 is a high-performance logic circuit, in which a plurality of data, for example, depth information, color information, or stencil-alpha information is read from the dual port cache memory 240 and output to the frame memory 210. Priority is determined by a round-robin method and output to the AXI write port 254. Accordingly, the coordinator unit 256 may efficiently store the data of the dual port cache memory 240 in the frame memory 210.

FIG. 3 is a flowchart for describing an operation of the 3D graphic accelerator shown in FIG. 2.

The operation of the cache controller 250 begins with an access from the perfragment unit 230, that is, an operation request.

First, the cache controller 250 checks whether the dual port cache memory 240 is initialized (S302).

If the dual port cache memory 240 is not initialized, the cache controller 250 initializes all the tag fields 252 to '0' or a default value (S304).

When the dual port cache memory 240 is composed of 32 blocks (hereinafter referred to as 'cache blocks') that can hold 8 X 8 pixel information, the tag field 252 of the cache controller 250 includes 32 cache block values. Block tags (TAG [0] to TAG [31]) capable of storing the data, and each block tag has an ID value for determining the location of the block in the frame memory 210, a value indicating whether the block has been updated, A value indicating whether the block is valid or the like is stored. In addition, the cache controller 250 may store usage ranks (LRU [0] to LRU [31]) for 32 cache blocks to indicate a recent order of use of the cache blocks.

Meanwhile, when the dual port cache memory 240 is initialized, the cache controller 250 calculates a corresponding block id (nw_blk_id) from the coordinate values u and v input from the perfragment unit 230 (S306). It is checked whether the corresponding block of the frame memory 210 is cached in the dual port cache memory 240 (S308). That is, since the block tag TAG [X] [15: 2] bit value represents the cache block id, whether the requested block exists in the dual port cache memory 240 by comparing the id values of valid cache blocks with the newly requested nw_blk_id. Investigate. In this case, if the requested nw_blk_id matches the cache block's id (TAG [X] [15: 2] and TAG [X] [0] == 1, then the cache block is valid, a cache hit, or a cache miss do.

If the cache controller 250 is a cache miss, the cache controller 250 replaces the oldest cache block among the cache blocks with new data. The oldest cache block number is the last value of the LRU array, that is, the value stored in the LRU [31]. In this case, it is checked whether the oldest cache block number, for example, the update bit TAG [X] [1] of the block tag is set to '1' (S310).

If the update bit TAG [X] [1] of the block tag is set to '1', the cache controller 250 first uses the AXI write port 254 to replace the cache block data before replacing the cache block. Is stored in the corresponding area of the frame memory 210 (S312).

If the update bit TAG [X] [1] of the block tag is set to '0' or the data of the corresponding cache block is stored in the corresponding area of the frame memory 210 through step S312, the cache controller 250 Data corresponding to the requested new block nw_blk_id is read from the frame memory 210 using the AXI read port 252 and stored in the cache block indicated by the LRU [31] (S314).

If it is a cache hit or if new block data is stored in that cache block via step 314, the cache controller 250 writes to perform the requested operation, ie read operation or write operation, for the corresponding pixel of that cache block. Check whether the operation (S316).

If the requested operation is a read operation, the cache controller 250 reads data of the corresponding pixel of the cache block and provides the read data to the perfragment unit 230 (S318). On the other hand, if the requested operation is a write operation, the cache controller 250 stores the pixel data provided from the perfragment unit 230 in the corresponding cache block, and sets the update bit of the block tag corresponding to the cache block to '1'. Set (S320).

Once a read or write operation is performed, cache controller 250 updates the LRU order. That is, the cache controller 250 writes the most recently used cache block number to the LRU [0], and increments the order of the remaining block numbers by one step.

After performing this series of steps, the cache controller 250 returns to the state where it can receive the next new request.

4 is a block diagram of a three-dimensional graphics acceleration device according to an embodiment of the present invention in detail, Figure 5 is a view showing in detail the adjuster shown in FIG.

The frame memory 210 includes a Z buffer 482 for storing depth information, an SA buffer 484 for storing stencil-alpha information, and a C buffer 486 for storing color information.

The pipelines of the perfragment unit 230 are scissor test, depth value read, depth test, depth value write, stencil-alpha value read. alpha value read, stencil operation, alpha test, alpha blending, stencil-alpha value write, color value read, logical operation (logical operation), dithering / color format conversion, and color value write.

FIG. 4 illustrates only the fine lines that interoperate with the cache controller among various pipelines of the perfragment unit 230. The perfragment unit 230 includes a depth value reading 402, a depth test 404, and a depth value. Write (406), read stencil-alpha value (412), stencil operation (414), alpha test (416), write stencil-alpha value (418), read color value (422), color format conversion (424), and color A value write 426 is provided.

The dual port cache memory 240, on the other hand, is a Z cache memory 432 associated with the depth test 404 of the perfragment unit 230, and a stencil operation 414 and alpha test 416 of the perfragment unit 230. SA cache memory 434 associated with and C cache memory 436 associated with color format conversion 424 of perfragment unit 230.

The cache controller 250 controls the Z controller 440 for controlling the Z cache memory 432, the SA controller 450 for controlling the SA cache memory 434, and the C cache memory 436. C control unit 460 and adjuster unit 470 is provided.

The Z controller 440 includes a Z tag field 442 for managing the Z cache memory 432, and the SA controller 450 includes an SA tag field 452 for managing the SA cache memory 434. In addition, the C controller 460 is provided with a C tag field 462 for managing the Z cache memory 436.

If the depth value 402 pipeline operation for the current fragment is performed, the perfragment unit 230 provides a read command signal and a depth address z_add to the Z controller 440 of the cache controller 250.

The Z control unit 440 checks whether the depth address z_add is in the Z tag field 442, and if it is a cache hit, reads depth information from the corresponding address zr_add of the Z cache memory 432 to read the depth value of the perfragment unit 230 ( 402). However, if the cache misses, the Z control unit 440 reads the depth information from the Z buffer 482 of the frame memory 210 based on the depth address z_add, stores the depth information in the Z cache memory 432, and stores the depth information of the perfragment unit 230. Provide to depth value read 402. The depth value reading 402 pipeline of the perfragment unit 230 is stalled until the cache controller 250 receives the requested depth information.

Upon receiving the depth value of the current fragment, the per-fragment unit 230 may perform a depth test operation in the depth test 404 pipeline. When the depth test is normally performed, the depth value write 406 provides a new depth value to the Z controller 440, and the Z controller 440 stores the new depth value in the corresponding cache block of the Z cache memory 432. The update information is recorded in the block tag of the Z tag field 442.

The Z control unit 440 receives a new read command signal and a new depth address z_add from the perfragment unit 230 while storing a new depth value in the corresponding cache block of the Z cache memory 432 and, if the cache hit, the Z cache memory. Depth information may be read from the corresponding address zr_add at 432 and provided to the depth value read 402 of the perfragment unit 230.

In operation of the stencil-alpha value read 412 pipeline for the current fragment, the perfragment unit 230 provides a read command signal and a stencil-alpha address sa_add to the SA controller 450 of the cache controller 250. Here, the stencil-alpha value may consist of 16 bits or 8 bits.

The SA controller 450 checks whether the stencil-alpha address sa_add is in the SA tag field 452, and if it is a cache hit, reads the stencil-alpha information from the corresponding address sar_add of the SA cache memory 434 to determine the perfragment unit 230. Provide for reading stencil-alpha values 412. However, if the cache misses, the SA controller 450 reads the stencil-alpha information from the SA buffer 484 of the frame memory 210 based on the stencil-alpha address sa_add, stores the stencil-alpha information in the SA cache memory 434, and stores the perfragment unit. Read 412 of stencil-alpha values (230). The stencil-alpha value read 412 pipeline of the perfragment unit 230 is stalled until the cache controller 250 receives the requested depth information.

Upon receiving the stencil-alpha value of the current fragment, the per-fragment unit 230 performs a stencil test operation in the stencil operation 414 pipeline and an alpha test operation in the alpha test 416 pipeline. When the stencil operation and the alpha test are normally performed, the stencil-alpha value write 418 provides a new stencil-alpha value to the SA controller 450, and the SA controller 450 provides a corresponding cache of the SA cache memory 434. The new stencil-alpha value is stored in the block, and update information is recorded in the corresponding block tag of the SA tag field 452.

In addition, when the color value read 422 pipeline operation of the current fragment is performed, the perfragment unit 230 provides a read command signal and a color address c_add to the C controller 460 of the cache controller 250.

The C control unit 460 checks whether the color address c_add is in the C tag field 462 and if it is a cache hit, reads color information from the corresponding address cr_add of the C cache memory 436 and reads the color value of the perfragment unit 230 ( 422). However, if the cache misses, the C controller 460 reads color information from the C buffer 486 of the frame memory 210 based on the color address c_add, stores the color information in the C cache memory 436, and then stores the color information in the per fragment unit 230. Provided to the color value read (422). The color value reading 422 pipeline of the perfragment unit 230 is stalled until the cache controller 250 receives the requested color information.

Upon receiving the color value of the current fragment, the perfragment unit 230 performs color format conversion in the color test 424 pipeline. When the color format conversion is normally performed, the color value write 406 provides a new color value to the C controller 460, and the C controller 460 sends the new color value to the corresponding cache block of the C cache memory 436. The update information is stored in the corresponding block tag of the C tag field 462.

The adjuster unit 470 is a high-performance logic circuit. When the depth information, the color information, or the stencil-alpha information of the dual port cache memory 240 is read and output to the frame memory 210, the priority is efficiently set and managed. Module.

As shown in FIG. 5, the coordinator unit 470 includes an address mux 502, a data mux 504, and a coordinator 506.

The address mux 502 connects the address lines of the Z controller 440, the address lines of the SA controller 450, and the address lines of the C controller 460 to the input port, and the AXI write port 254 to the output port. Connect the address lines.

The data mux 504 connects the data lines of the Z controller 440, the data lines of the SA controller 450, and the data lines of the C controller 460 to the input port, and the AXI write port 254 to the output port. Connect the data lines of the.

When the coordinator 506 receives the request signal REQ from the Z control unit 440, the SA control unit 450, and the C control unit 460, the coordinator 506 assigns the priority according to the priority round robin scheduler. In the present invention, priority is given to color, depth, and stencil-alpha.

A request signal for a write request has been input from the Z controller 440 to the Z buffer 482 of the frame memory 210, but a request for a write request from the C controller 460 to the C buffer 486 of the frame memory 210 is received. When no signal is input, the coordinator 506 outputs an acknowledgment signal ACK to the Z control unit 440, outputs a control signal for selecting a Z address line to the address mux 502, and Z to the data mux 504. Outputs a control signal for selecting a data line. The Z control unit 440 then provides an address signal to the Z address line, and also reads the data of the cache block from the cache memory 432 and provides it to the Z data line, thereby providing the corresponding signal received through the AXI write port 254. The data of the cache block is stored in the corresponding area of the Z buffer 482 of the frame memory 210.

However, although a request signal for a write request is input from the Z controller 440 to the Z buffer 482 of the frame memory 210, a request signal for writing to the C buffer 486 of the frame memory 210 is input from the C controller 460. When the request signal is input, the coordinator 506 outputs an acknowledgment signal ACQ to the C control unit 460, outputs a control signal for selecting the C address line to the address mux 502, and outputs a C to the data mux 504. Outputs a control signal for selecting a data line. The C control unit 460 then provides an address signal to the C address line, and also reads the data of the corresponding cache block from the cache memory 436 and provides it to the C data line, thereby receiving the corresponding signal received through the AXI write port 254. The data of the cache block is stored in the corresponding area of the C buffer 486 of the frame memory 210.

Since the coordinator unit 470 has three masters, that is, the Z control unit 440, the SA control unit 450, and the C control unit 460 communicate with one interface, two master ports need to be added to the AXI bus matrix. There is no.

6 is a timing diagram when a single port is used as the cache memory, and FIG. 7 is a timing diagram when a dual port is used as the cache memory.

6 and 7 illustrate a process of reading existing depth data from the perfragment unit 230 and updating and writing the input depth value back into the cache memory when the input depth value is smaller than the existing depth value. Illustrated. If this read / write operation occurs N times, it takes (N x 3) clock for single port and (N + 2) clock for dual port. As can be seen in Figures 6 and 7, if three reads / writes have been made, i.e. the operation between points A and B in Figures 6 and 7 takes 9 clocks for a single port, and for dual ports It takes 5 clocks.

The protection scope of the present invention should be interpreted by the following claims. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. It should be interpreted that it is included in the scope of right.

1 is a block diagram showing a process of processing a general three-dimensional graphic.

2 is a block diagram of an apparatus for accelerating 3D graphics according to an embodiment of the present invention.

FIG. 3 is a flowchart for describing an operation of the 3D graphic accelerator shown in FIG. 2.

4 is a block diagram illustrating in detail a 3D graphic accelerator according to an exemplary embodiment of the present invention.

FIG. 5 is a view illustrating in detail the adjuster unit illustrated in FIG. 4.

6 is a timing diagram when a single port is used as the cache memory.

7 is a timing diagram when a dual port is used as a cache memory.

<Explanation of symbols for the main parts of the drawings>

210: frame memory 220: AXI BUS MATRIX

230: fragment unit 240: dual port cache memory

250: cache controller 252: tag field

254: AXI lead port 256: AXI light port

256: adjuster part

Claims (10)

Frame information for storing at least one of depth information, color information, and stencil-alpha information as pixel information to be displayed; A per-fragment unit that performs at least one depth test, color conversion, and stencil arithmetic-alpha test for the current fragment; A dual port cache memory capable of reading and storing depth information, color information, and stencil-alpha information of an area corresponding to the current fragment from the frame memory, and having a read function and a write function at the same clock; A request for depth information, color information, or stencil-alpha information for an area corresponding to the current fragment is performed from the per fragment unit to perform a depth test, color conversion, or stencil arithmetic-alpha test on the current fragment. If there is a request information in the dual port cache memory, if the information is read and output, and if there is no request information in the dual port cache memory includes a cache controller for reading from the frame memory and storing in the dual port cache memory, The dual port cache memory and the perfragment unit use the same clock, The cache controller includes a coordinator section having a high speed logic circuit for adjusting priority when two or more of depth information, color information, or stencil-alpha information of the dual port cache memory are simultaneously written to the frame memory. 3D graphics accelerator, characterized in that. delete The method of claim 1, The coordinator unit includes a coordinator for determining a priority, an address mux for selecting and outputting one from address lines of depth information, color information, or stencil-alpha information of the dual port cache memory under control of the coordinator; And a data mux which selects and outputs one from data lines of depth information, color information, or stencil-alpha information of the dual port cache memory under control of the dual port cache memory. The method of claim 1, The adjuster unit gives priority to the color information, depth information, stencil-alpha information of the dual port cache memory in order to output to the light bus. The method according to claim 1, 3 or 4, And said dual port cache memory is a static RAM (SRAM). delete The method of claim 5, The cache controller further comprises a tag field for managing the dual port cache memory, and an LRU algorithm for block replacement of the dual port cache memory. As pixel information to be displayed, a frame memory for storing at least one or more depth information, color information, and stencil-alpha information, and a fur for performing at least one depth test, color conversion, and stencil arithmetic-alpha test for the current fragment. A dual port cache that can read and store a fragment unit, depth information, color information, and stencil-alpha information for the region corresponding to the current fragment from the frame memory, and can read and write at the same clock. In the three-dimensional graphics acceleration method using a graphics acceleration device having a memory, A request for depth information, color information, or stencil-alpha information for an area corresponding to the current fragment is performed from the per fragment unit to perform a depth test, color conversion, or stencil arithmetic-alpha test on the current fragment. If there is request information in the dual port cache memory, reading the information and outputting the requested information; If there is no request information in the dual port cache memory, reading from the frame memory and storing in the dual port cache memory; and Adjusting priority if at least two of depth information, color information, or stencil-alpha information of the dual port cache memory are simultaneously written to the frame memory, And the dual port cache memory and the perfragment unit use the same clock. delete The method of claim 8, If there is no request information in the dual port cache memory, it is checked whether the update bit of the oldest block tag is set, and if the update bit is set, the data of the oldest block is stored in a frame memory. Graphics acceleration method.

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