KR20080006136A - Cache memory apparatus for 3-dimensional graphic computation, and method of processing 3-dimensional graphic computation - Google Patents

Abstract

A cache memory device for 3D graphic computation and a 3D graphic computation processing method are provided to refer to apex index arrangement for more accurately predicting the processing order of apex data used in the 3D graphic computation to improve a cache hit rate although a cache memory of a limited size is used. A cache memory array(411) stores apex data used in 3D graphic computation. A tag memory(412) stores first apex indexes corresponding to the apex data. An index buffer(421) stores second apex indexes associated with the graphic computation according to the processing order of the graphic computation. A cache memory control unit(410) compares the second apex index with the first apex indexes, and judges whether to perform a cache hit of the apex data.

Description

CACHE MEMORY APPARATUS FOR 3-DIMENSIONAL GRAPHIC COMPUTATION, AND METHOD OF PROCESSING 3-DIMENSIONAL GRAPHIC COMPUTATION}

1 is a block diagram illustrating a data flow of a conventional data processing system including a cache memory.

2 is a flowchart illustrating a method of performing a cache memory read operation in the system of FIG. 1.

3 is a block diagram illustrating a data flow between a main memory, a cache memory, and an execution unit of a three-dimensional graphics accelerator according to the present invention.

4 is a block diagram showing in detail the internal configuration of the cache memory and its peripheral circuit according to the present invention.

5 is a flowchart illustrating step by step a three-dimensional graphics operation processing method using a cache memory according to the present invention.

<Explanation of symbols for the main parts of the drawings>

310: cache memory 320: cache memory controller

330 and 430: processing sequence buffer 340: execution unit

350: main memory 360: main memory controller

370: memory bus 411: cache memory array

412: tag memory 413: cache memory control unit

421: Index buffer 431: Processing sequence buffer

The present invention relates to a cache memory applied to a three-dimensional graphics accelerator, and more particularly, to a configuration of a vertex data cache memory for storing vertex data used for three-dimensional graphics operations and determining whether or not a cache hit using a vertex index. will be.

Three-dimensional graphics technology refers to a technology for visualizing the shape, color, and motion of an object located in three-dimensional space using a digital computer and three-dimensional software. 3D graphics technology has been greatly developed in recent years due to the growth of the 3D game market, and in fact, it is also a core foundation technology that is already widely used in the fields of education, medical care, military, and art.

This 3D graphics technology is widely used because this technology can intuitively convey information to the user by showing the object realistically. In a typical 3D graphic image, an object is composed of a plurality of edges or polygons. The three-dimensional graphics processing unit or three-dimensional graphics accelerator allows the user to visualize objects modeled in three-dimensional space by applying three-dimensional graphics operations on the vertices constituting the polygon.

Due to the nature of three-dimensional graphics operations that require complex calculations that refer to a large number of parameters, it is important to optimize performance by minimizing duplication of computation and data access when designing three-dimensional graphics accelerators.

In particular, the 3D graphics processing system often uses a main memory composed of synchronous dynamic random access memory (SDRAM) to store a large amount of image data, in which case the main memory resources are shared with other devices besides the 3D graphics accelerator. The memory bus is used to do this. If the main memory is directly accessed to refer to the vertex data used as a parameter in three-dimensional graphics operations, the overhead of using the memory bus reduces the efficiency of the graphics accelerator. Thus, to prevent this performance degradation, cache memory is placed between the main memory and the graphics accelerator to reduce main memory access overhead.

1 is a block diagram illustrating the data flow of a conventional general data processing system including a cache memory. Referring to FIG. 1, the execution unit 130, such as an arithmetic unit that performs 3D graphic calculation, first reads the cache memory 110 through the cache memory controller 120 before reading data from the main memory 140. See.

The cache memory controller 120 reads the data from the cache memory 110 when the data to be used by the execution unit 130 is stored in the cache memory 110, that is, the cache hit, and executes the execution unit 130. To pass). However, when the data to be used by the execution unit 130 is not stored in the cache memory 110, that is, when the cache misses, the main memory 140 is connected to the main memory controller 150 connected to the memory bus 160. The data is copied from the cache memory 140 to the execution unit 130 after being copied.

2 is a flowchart illustrating a method of performing a cache memory read operation in the system of FIG. 1. As shown in FIG. 2, when a cache read request or a command is transmitted from the execution unit 130 by step S210, the cache memory 110 is referred to in step S220. The cache hit of the data associated with the cache read request is checked. If it is a cache hit, the data is read from the cache memory 110 by the step S230 and transferred to the execution unit 130. Otherwise, if the cache is missed, in step S240, the main memory (S240) is used to copy the data. 140). At this time, as described in the illustrated step S250, not only the necessary data but also a certain amount of data of an adjacent address are copied from the main memory.

The reason why a certain amount of data is copied together in addition to the necessary data is due to the locality of the data. That is, the execution logic of the general program and the data storage structure of the general program is likely to use the data stored in the near future in the near future memory execution unit 130.

However, when applying such a general cache memory to the 3D graphics accelerator, some problems may occur.

First, when the execution unit 130 checks the data in the cache memory 110 when the execution unit 130 is needed as in the conventional general cache memory and approaches the main memory 140 when there is no data, the execution unit 130 is the cache memory. While the controller 120 is copying data from the main memory 140 to the cache memory 110, execution must be stopped for many hours. This problem occurs because the conventional cache memory does not reflect the specificity of the three-dimensional graphics operation.

Second, in order for the conventional cache memory control method that copies a certain amount of data to be collectively based on the locality effect, the cache memory must be at least a certain level that is at least several times the amount of data copied at one time. do. Therefore, when the size of the cache memory is designed to be small or the size of the available cache memory is limited by necessity, the conventional general cache memory structure does not exhibit satisfactory performance.

Accordingly, in order to solve the above problems, the present invention proposes a cache memory structure designed to operate more efficiently by reflecting the specificity of three-dimensional graphic operations.

SUMMARY OF THE INVENTION The present invention has been made to improve the prior art as described above, and an object thereof is to provide a configuration of a new cache memory that determines whether a cache hit is made by referring to an index array of vertex data.

By referring to a vertex index array that makes it possible to more accurately predict the processing order of vertex data used in three-dimensional graphics operations, the present invention aims to improve the cache hit rate even when using a limited size cache memory.

In addition, through the above configuration, the present invention aims to significantly reduce the size of the cache memory array used in the conventional general cache memory, to save circuit area, and to reduce the process cost and process failure rate.

In addition, the present invention by copying the vertex data required for the next operation from the main memory while the three-dimensional graphics operation is being performed, thereby reducing the idle waiting time of the three-dimensional graphics accelerator device The purpose is to improve the operation efficiency.

It is also an object of the present invention to use a small size cache memory more efficiently by copying only necessary vertex data instead of collectively copying a predetermined amount of data adjacent to necessary vertex data from the main memory.

In addition, an object of the present invention is to minimize the performance degradation caused by the main memory access overhead by copying a number of vertex indexes at the same time when copying the vertex index array stored in the main memory to the index buffer.

In addition, the present invention is to increase the operation throughput of the cache memory by storing the address value of the cache memory array for storing the vertex data in the processing order buffer according to the processing order of the vertex data so that it can be externally referenced. It is done.

In order to achieve the above object and to solve the above-mentioned problems of the prior art, the cache memory device according to the present invention is a cache memory array for storing the vertex data used for the three-dimensional graphics operation, corresponding to each of the vertex data Tag memory for storing vertex indices, an index buffer for storing second vertex indices associated with a graphic operation according to the processing order of the graphic operation, and whether the vertex data is cache hit by comparing the second vertex index with the first vertex indices. It characterized in that it comprises a cache memory control unit for determining the.

Further, a method of storing vertex data in a cache memory according to the present invention includes a first step of storing previously referenced vertex data and first vertex indices corresponding to the vertex data in a cache memory, associated with the graphic operation. A second step of reading the second vertex indexes from the main memory and storing the second vertex indexes in the index buffer according to the processing order of the graphic operation; and a third step of determining whether or not the cache hit is performed by comparing the second vertex index with the first vertex indexes. A fourth step of reading the vertex data corresponding to the second vertex index from the main memory and storing the vertex data corresponding to the second vertex index in the cache memory, and the address at which the vertex data corresponding to the first vertex index is stored on the cache memory. And a fifth step of storing the value in the processing sequence buffer.

In addition, the three-dimensional graphics processing method according to the present invention comprises the steps of maintaining a processing order buffer for storing the address value stored in the vertex data on the cache memory, by reading the address value from the processing order buffer, And reading the vertex data by accessing the address on the cache memory, and performing the 3D graphic operation using the read vertex data as a parameter.

Hereinafter, a configuration of a cache memory device and a method of efficiently processing a graphic operation using the cache memory device will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a data flow between a main memory, a cache memory, and an execution unit of a three-dimensional graphics accelerator according to the present invention.

Referring to FIG. 3, the cache memory controller 320 is connected to the memory bus 370 to access the main memory 350 through the main memory controller 360 like the conventional cache memory circuit. The main memory 350 stores vertex data of each vertex necessary for 3D graphic calculation. In addition, the main memory 350 stores a vertex index array in which graphic vertex processing sequences of various vertices are stored. The vertex index array stored in the main memory 350 is input from the user. The use of the vertex index array will be described later in more detail. On the other hand, the main memory 350 is composed of synchronous dynamic random access memory (SDRAM) and the like, and a considerable cycle is required to access the memory for reading data.

As pointed out above, the execution unit 340 represented by a T & L engine (Transform & Lighting engine) that performs coordinate transformation and lighting processing operations, etc., is loaded into the main memory 350 each time in order to obtain vertex data used for graphic calculation. When directly approaching, the execution unit 340 may not perform the graphic operation while reading the vertex data from the main memory 350, resulting in a decrease in the efficiency of the graphic operation processing. For this reason, the cache memory controller 320 copies the vertex data to be used by the execution unit 340 in the near future among the vertex data stored in the main memory 350 to the cache memory 310 which can be accessed relatively quickly. The overhead of accessing the main memory 350 of the execution unit 340 may be reduced.

However, unlike conventional cache memory circuits in the related art, the cache memory device according to the present invention does not transmit a cache read request to the cache memory controller 320 when the execution unit 340 needs vertex data. The vertex data stored at a specific address of the cache memory 310 is directly taken by referring to the process order buffer 330 managed by the controller 320.

That is, the cache memory controller 320 does not determine whether the cache is hit when the cache read request of the execution unit 340 is transmitted, but before the execution unit 340 refers to the cache memory 310, the execution unit is executed in advance. Vertex data to be used next by 340 is stored in the cache memory 310. As such, the execution unit 340 stores the next vertex data in advance in the cache memory 310 before referring to the cache memory 310, so that the cache memory device according to the present invention vertex data from the main memory 350 at the time of cache miss. Idle waiting time of the execution unit 340 by copying can be eliminated or greatly reduced.

As such, the reason why the cache memory controller 320 may predict and store vertex data to be used next by the execution unit 340 is due to the specificity of the 3D graphic operation. As described above, in a 3D graphic image, an object is composed of primitives such as edges or polygons, and the primitives are composed of a plurality of vertices. For example, a line consists of two vertices and a triangular polygon consists of three vertices. Therefore, it can be said that the 3D graphic calculation is performed with a plurality of vertices.

In the 3D graphic operation, the processing sequence of vertex data, that is, data related to each vertex, can be known through the vertex index array input from the user. For reference, the vertex index array stores indexes of vertices to be processed in order of processing.

OpenGL, a popular open graphics library standard, supports API functions called DrawArray () and DrawElement () as functions for visualizing three-dimensional objects. Among them, DrawElement () is a function that performs vertex operations in the order specified by the user. At this time, the processing order is often determined to sequentially process the vertices associated with successive primitives, and there are shared vertices among successive primitives.

For example, adjacent triangular polygons share one or two vertices, and adjacent lines share one vertex. Hence, vertex data currently used for three-dimensional graphics operations are shared by adjacent primitives and are likely to be used again in the near future.

Therefore, the cache memory controller 320 reads the vertex index array stored in the main memory 350 while the execution unit 340 is performing the 3D graphic operation, and vertex data corresponding to the stored vertex index is stored in the cache memory ( If it is stored in 310). If so, the address value of the cache memory storing the vertex data is stored in the next entry of the processing sequence buffer 330.

However, if no vertex data corresponding to the stored vertex index is stored in the cache memory 310, the cache memory controller 320 transfers the vertex data corresponding to the vertex index from the main memory 350 to the cache memory 310. Copy and store, and add the stored address value to the processing sequence buffer 330.

At this time, the cache memory controller 320 may remove any one of the vertex data previously stored from the cache memory 310 according to a predetermined replacement algorithm. The vertex data to be removed is generally the least hit data, and the replacement algorithm for selecting the vertex data to be removed is the least recently used (LRU) algorithm, first-in-first-out, FIFO. ) Algorithm, Least Frequently Used (LFU) algorithm, and random selection algorithm.

When using the cache memory device operating as described above, the execution unit 340 does not read from the cache memory through the required vertex data cache memory controller 320, but refers to the processing sequence buffer 330 to process the processing sequence buffer. The vertex data is read directly by accessing the cache memory 310 address corresponding to the address value sequentially stored in the.

4 is a block diagram showing in detail the internal configuration of the cache memory and the peripheral circuits that operate in this manner. Specifically, FIG. 4 illustrates a more practical configuration of the cache memory device including the cache memory 310, the cache memory controller 320, and the processing order buffer 330 shown in FIG. 3. FIG. 3 is a simplified illustration of some of the components according to the actual configuration shown in FIG. 4 for convenience of description, in order to explain the operation of the cache memory device according to the present invention. Thus, the components shown in FIG. 4 correspond to the cache memory 310, the cache memory controller 320, and the processing order buffer 330 of FIG. 3, one-to-one, some, or a combination thereof, respectively.

Referring to FIG. 4, a cache memory device according to the present invention includes a vertex data cache memory block 410, an index buffer block 420, and a processing sequence buffer block 430. For reference, FIG. 4 illustrates a case in which the cache memory device stores vertex data for 64 vertices.

The index buffer block 420 may further include an index buffer 421 for storing the vertex index array and an index buffer controller 422 for controlling data read / write operations of the index buffer 421. The vertex index array stored in the index buffer 421 is copied from the main memory 350 by the cache memory controller 413. The cache memory controller 413 may obtain vertex data for several vertices from the main memory 350 at one time and store the vertex data in the index buffer 421 in order to minimize the number of times the main memory 350 is accessed.

Meanwhile, in the cache memory array 411 included in the vertex data cache memory block 410, vertex data used as a parameter for three-dimensional graphic operations is stored. As shown, the cache memory array 411 may include a plurality of memory blocks for storing various types of vertex data for each type.

As an example, a memory block for each vertex data type constituting the cache memory array 310 may include a vertex coordinate block that stores the coordinates of the vertex, a normal coordinate block that stores the coordinates of the vertical vector of the vertex, and a vertex A vertex color block that stores data related to the color of the texture, a texture 0 coordinate block that stores the coordinates associated with the 0th texture, and a texture 1 coordinate that stores the coordinates associated with the 1st texture coordinate block, a point size block that stores the point size data of the vertices, a matrix palette weight block that stores the weights and indices of the matrix palette related to the movement of the vertices, and a matrix palette index, respectively. palette index) block and the like.

The vertex data cache memory block 410 also includes a tag memory 412 that stores tag information for determining whether a cache hit is made. The tag information stored in the tag memory 412 is an index of each vertex. Each entry in the tag memory 412 corresponds to each entry in the cache memory array 411. That is, the vertex index corresponding to the vertex data stored in the n th entry among the 64 entries of the cache memory array 411 is stored in the n th entry of the tag memory 412.

The cache memory controller 413 reads one vertex index stored in the index buffer to determine whether the cache is hit, and compares the vertex index with the vertex index stored in the tag memory 412. When an entry storing a matching vertex index is found in the tag memory 412, the cache memory controller 413 stores the entry number or address value of the corresponding cache memory array 411 in the processing sequence buffer 431. Save it.

However, if no tag memory entry is stored that matches the vertex index, the cache memory controller 413 copies the vertex data corresponding to the vertex index from the main memory 350 to the cache memory array 411. Come and save The stored address value of the cache memory array 411 is stored in the processing sequence buffer 431.

Finally, the processing sequence buffer block 430 controls the processing sequence buffer 431 for storing address values of the cache memory array 411 in which the vertex data is stored, and the processing sequence buffer control unit for controlling data read / write operations of the processing sequence buffer. 432. The position where each address value is stored in the processing sequence buffer 431 corresponds to the position where each vertex index is stored in the index buffer 421. That is, the address value stored in the i th entry among the 64 entries in the processing sequence buffer 431 means an address value in which vertex data corresponding to the vertex index stored in the i th entry of the index buffer 421 is stored.

An operation of the cache memory device configured as shown in FIG. 4 will be described more easily with one example. For example, when the cache memory controller 413 performs processing for the i th vertex stored in the vertex index array, the vertex index and the vertex data of the i th vertex are respectively tagged memory 412 and cache memory array 411. Is stored in the nth entry of the.

The cache memory controller 413 searches the entries of the tag memory 412 for an index value corresponding to the i th vertex index and determines whether the cache is hit. If a matching index value is found in the n th entry as a result of the search, the cache memory controller 413 determines that the cache hit is the address value 'n' of the n th entry of the cache memory array 411 at the i th position of the processing order buffer. Save it.

If the vertex data of the i th vertex is not stored in the cache memory array 411, the corresponding vertex index is not stored in the tag memory 412. Therefore, the cache memory controller 413 does not find an index value corresponding to the i th vertex index in the entry of the tag memory 412, and determines it as a cache miss. Accordingly, the cache memory controller 413 copies the vertex data corresponding to the i th vertex index from the main memory 350 and stores the vertex data in the m th entry of the cache memory array 411. At this time, the i th vertex index is stored in the m th entry of the tag memory. In addition, the address value 'm' of the m th entry of the cache memory array 411 is stored in the i th position of the processing sequence buffer 431.

If 64 entries in the cache memory array 411 are already used to store vertex data, then further storage of the vertex data means that the mth entry is replaced with new vertex data and vertex index. The replacement algorithm for selecting the m-th entry to be replaced at this time has been described above.

According to an embodiment, the operation of obtaining the vertex index array from the main memory 350 or determining whether the hit is related to the i th vertex index and the updating operation of the processing sequence buffer 431 according to the execution unit 340 may be performed by the execution unit 340. Vertex data read from the device may be used to perform simultaneous three-dimensional graphics operations.

5 is a flowchart illustrating step by step a three-dimensional graphics operation processing method using a cache memory according to the present invention.

Referring to FIG. 5, in operation S510, a process of reading a vertex index array from the main memory 350 and storing the vertex index array in the index buffer 421 is performed. In the vertex index array, vertex indices of vertices to be processed are stored in the graphic operation processing order.

In operation S520, one of the vertex indexes stored in the index buffer is compared with the vertex index values stored in the entries of the tag memory 412 to determine whether the cache is hit.

As a result of the determination, if a matching index value is found in the tag memory 412, it is determined as a cache hit and the address value of the cache memory array 411 corresponding to the location found on the tag memory 412 is determined in step S530. Stored in the processing sequence buffer 431.

On the other hand, if a matching index value is not found in the tag memory 412, determining a cache miss and accessing the main memory 350 through the memory bus (S540) and a vertex corresponding to the vertex index in the main memory The data is copied and stored in the cache memory array 411 (S550). Next, the address value of the cache memory array 411 in which the vertex data is stored is stored in the processing sequence buffer 431 so that the cache memory array 411 may be directly referenced from the outside.

In operation S560, the vertex data is read from the cache memory array 411 with reference to the processing sequence buffer 431. This step (S560) is performed by the execution unit 340 connected to the outside of the cache memory device, according to this step to the address of the cache memory array 411 corresponding to the address value stored in the processing sequence buffer 431 The stored vertex data will be read directly.

The vertex data read out in step S560 is used as a parameter in the three-dimensional graphic calculation of step S570. According to one embodiment, at least one of steps S510 to S550 is performed simultaneously with step S570 of performing a 3D graphic operation. As such, while the three-dimensional graphic operation for a specific vertex is performed, the vertex data associated with the next vertex is stored in the cache memory in advance, and the address value in which the vertex data is stored can be referred to from the outside so that the main memory 350 can be cached at the time of cache miss. ), We can eliminate or significantly reduce the idle wait time waiting for 3D graphics operations while copying vertex data.

The lighting processing calculation method according to the present invention has been described above with reference to FIG. 5. Since the details of the embodiments described above with reference to FIGS. 1 to 4 may be applied to the illumination processing calculation method according to the present invention, the description of the details related to the present method will be omitted.

The method of storing the vertex data in the cache memory according to the present invention may be implemented in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the media may be those specially designed and constructed for the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks such as floppy disks. -Magneto-Optical Media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like.

The medium may be a transmission medium such as an optical or metal wire, a waveguide, or the like including a carrier wave for transmitting a signal specifying a program command, a data structure, or the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, in the present specification, the description of the present invention has been provided through specific embodiments and limited embodiments and drawings, but the present invention is provided to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. The present invention may be devised by those skilled in the art to which the present invention pertains without departing from the scope of the present invention.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and all the things that are equivalent to or equivalent to the scope of the claims as well as the claims to be described later belong to the scope of the present invention. will be.

According to the cache memory device and the method of processing a 3D graphic operation using the cache memory device according to the present invention, by referring to the vertex index array to predict the processing order of the vertex data more accurately, The cache hit rate can be improved while using.

In addition, according to the present invention, the size of a cache memory array used in a conventional general cache memory can be greatly reduced, thereby reducing the circuit area and reducing the process cost and the process failure rate.

In addition, the present invention copies the vertex data required for the next operation from the main memory while the three-dimensional graphics operation is being performed, thereby reducing the idle waiting time of the three-dimensional graphics accelerator device to improve the operational efficiency of the entire three-dimensional graphics accelerator. Can be improved.

In addition, the present invention makes it possible to use a small size cache memory more efficiently by copying only necessary vertex data instead of copying a certain amount of data from the main memory to the cache memory at once.

In addition, the present invention can minimize the performance degradation caused by the main memory access overhead by copying a number of vertex indexes at the same time when copying the vertex index array stored in the main memory to the index buffer.

In addition, according to the present invention, the address value of the cache memory array that stores the vertex data according to the processing order of the vertex data is stored in the processing order buffer to be externally referred to, thereby improving the operation throughput of the cache memory. Can be.

Claims (16)

A cache memory array for storing vertex data used for three-dimensional graphics operations; A tag memory for storing first vertex indices corresponding to each of the vertex data; An index buffer that stores second vertex indices associated with the graphics operation according to the processing order of the graphics operation; And A cache memory controller configured to determine whether the vertex data is cache hit by comparing the second vertex index with the first vertex indexes Cache memory device comprising a. The method of claim 1, A processing sequence buffer for storing the address value in which the vertex data is stored in the cache memory array according to the processing sequence More, The cache memory controller stores the address value with reference to the index buffer. Cache memory device, characterized in that. The method of claim 2, The cache memory controller determines a cache hit when an entry in which the matching first vertex index value is found as a result of the comparison is determined, and further stores the address value corresponding to the found entry in the processing sequence buffer. Cache memory device, characterized in that. The method of claim 2, The cache memory controller determines that a cache miss is detected when an entry storing the matching first vertex index value is not found, and vertex data corresponding to the first vertex index is read from a main memory and the cache is read. And storing the stored address value in the processing sequence buffer. The method of claim 2, The cache memory device is connected to a three-dimensional graphics computing device for performing coordinate transformation or lighting operation, Wherein the graphics computing device reads the vertex data from the cache memory array with reference to the processing order buffer. Cache memory device, characterized in that. The method of claim 1, And the cache memory controller reads a plurality of second vertex indexes from a main memory at a time and stores the plurality of second vertex indexes in the index buffer. The method of claim 1, And when the vertex data is read from the main memory, the cache memory controller reads only the vertex data except for data of an adjacent address. The method of claim 1, The cache memory device comprises a plurality of memory blocks for storing the vertex data for each type. The method of claim 1, And the vertex data includes at least one of vertex coordinates, vertical coordinates, vertex colors, vertex sizes, matrix palette weights, and matrix palette indexes. In the method of storing the vertex data for the vertices in the three-dimensional space in the cache memory, A first step of storing previously referenced vertex data and first vertex indexes corresponding to the vertex data in a cache memory; A second step of reading second vertex indices associated with the graphic operation from a main memory and storing the second vertex indexes in an index buffer according to a processing order of the graphic operation; A third step of determining whether to hit a cache by comparing the second vertex index with the first vertex indexes; A fourth step of reading vertex data corresponding to the second vertex index from the main memory and additionally storing the vertex data in the cache memory when the result of the determination is a cache miss; And A fifth step of storing an address value in which vertex data corresponding to the first vertex index is stored in a cache in a processing sequence buffer; Vertex data storage method comprising a. The method of claim 10, A sixth step of reading the vertex data from the cache memory with reference to the processing sequence buffer; And A seventh step of performing a 3D graphic operation using the read vertex data as a parameter Vertex data storage method characterized in that it further comprises. The method of claim 11, At least one of the first to fifth steps is performed simultaneously with the seventh step. The method of claim 10, And the graphic operation is a coordinate transformation or lighting operation for the vertex. In the graphic operation processing method for a vertex in three-dimensional space, Maintaining a processing order buffer for storing an address value in which vertex data is stored on a cache memory; Reading the address value from the processing sequence buffer, accessing a address on the cache memory corresponding to the address value, and reading the vertex data; And Performing a 3D graphic operation using the read vertex data as a parameter Graphic processing method comprising a. The method of claim 14, Maintaining the processing sequence buffer, Reading a vertex index array input from a user and stored in the main memory; Determining whether to hit a cache of vertex data corresponding to the vertex index using the vertex index included in the vertex index array; And Storing the vertex data in the cache memory according to whether the cache is hit, and updating the stored address value in the processing sequence buffer. Graphic processing method comprising a. A computer-readable recording medium having recorded thereon a program for executing the method according to any one of claims 10 to 15.

Images