KR101017683B1 - Voltage doubler circuit - Google Patents

Abstract

The present invention relates to a voltage doubling circuit that improves a phenomenon in which an output voltage drops in accordance with a load at an output terminal. The present invention relates to a first transistor for switching a battery voltage by a first pulse signal applied to a base terminal, A second transistor receiving a second pulse signal inverting one pulse signal, the second transistor and a push-pull circuit, and a third transistor receiving the battery voltage switched from the first transistor at a base end and the second transistor; A first capacitor that charges the battery voltage and discharges charged power based on a switching operation of a second and a third transistor, wherein the first and second transistors are of NPN type, and the third transistor is of PNP type. Prepare the composition.

By using the voltage multiplier circuit as described above, it is possible to reduce the time required for outputting the DC driving voltage in the steady state by reducing the drop of the output voltage according to the load at the output stage, and to output the output voltage at a stable voltage level. Can be.

Voltage multiplier, NPN type, push-pull, pulse signal

Description

Voltage multiplier circuit {VOLTAGE DOUBLER CIRCUIT}

The present invention relates to a voltage doubler circuit, and more particularly, to a voltage doubler circuit for doubling and outputting a battery voltage.

As a motor driving apparatus for fuel pumps used in a vehicle, a voltage doubling circuit is used for the purpose of using a voltage doubled by an applied voltage, for example, 12V, such as 24V.

1 is a circuit diagram of a voltage multiplier circuit according to the prior art.

As shown in FIG. 1, the conventional voltage multiplier circuit includes a first transistor Q11 and a push-pull circuit for switching the battery voltage VCC according to a pulse signal output from a motor controller not shown. The second and third transistors Q22 and Q33 configured to switch the battery voltage VCC according to the switching signal of the first transistor Q11, and the battery voltage according to the switching signal of the second transistor Q22. VCC), the first capacitor C1 for discharging the charged power, the second capacitor C2 for limiting the battery voltage VCC and improving the ripple voltage, and the ripple of the output voltage of the output terminal. And a third capacitor C3 for improving the voltage.

Between the input terminal of the pulse signal and the base terminal of the first transistor Q11, between the input terminal of the battery voltage VCC and the collector terminal of the first transistor Q11, the collector terminal of the first transistor Q11 and the second and second First to fourth resistors R1, R2, R3, and R4 are connected between the base terminals of the three transistors Q22 and Q33, and between the input terminal of the battery voltage VCC and the collector terminal of the second transistor Q2, respectively. do. The first to fourth resistors R1, R2, R3, and R4 may limit current flowing therein. The second resistor R2 is a pull-up resistor that pulls up the voltage level of the battery voltage VCC.

First and second diodes D1 and D2 are connected between the input terminal of the battery voltage VCC and the first capacitor C1, and between the first capacitor C1 and the output terminal, respectively. The first and second diodes D1 and D2 charge a current in the first capacitor C1 and change a current direction to discharge the charged current.

The conventional voltage multiplier circuit configured as described above operates according to a pulse signal applied from the motor controller to the first transistor Q11.

When a high level pulse signal is input, the first transistor Q11 is turned on, and the second and third transistors Q22 and Q33 are voltages of the analog ground terminal AGND level. Is authorized. Then, the second transistor Q22 is turned off and the third transistor Q33 is turned on.

Accordingly, the battery voltage VCC is supplied to the first capacitor C1 via the first diode D1, and the first capacitor C1 charges the supplied battery voltage VCC.

In contrast, when a low level pulse signal is input, the first transistor Q11 is turned off and the battery voltage VCC is applied to the base terminals of the second and third transistors Q22 and Q33. Then, the second transistor Q22 is turned on and the third transistor Q33 is turned off.

Accordingly, the battery voltage VCC is supplied to the first capacitor C1 through the second transistor Q22, and the first capacitor C1 supplies the already charged battery voltage VCC and the second transistor Q22. The battery voltage VCCX2, which is doubled to a voltage level of twice, is output through the second diode D2 and the output terminal by adding the battery voltage VCC supplied through the second diode D2 and the output terminal.

This conventional voltage doubling circuit has the following problems.

First, the conventional voltage multiplier circuit drives the push-pull circuit by a switching signal applied to the base ends of the second and third transistors Q22 and Q33 constituted by the push-pull circuit. At this time, since the second transistor Q22 is composed of an NPN type transistor, the current of the battery voltage VCC due to the turn-on operation cannot be quickly transferred to the output terminal.

The fourth resistor R4 limits the current of the battery voltage VCC supplied to the second transistor Q22, thereby limiting the current supplied to the output terminal.

In addition, since the push-pull circuit operates by using the same switching signal applied to the base terminals of the second and third transistors Q22 and Q33, after the second transistor Q22 is turned on, there is no delay time. The third transistor Q33 is turned on so that the second and third transistors Q22 and Q33 are turned on at the same time. This phenomenon causes unnecessary current consumption and causes a decrease in power efficiency.

Therefore, the conventional voltage multiplier circuit has a problem in that the load on the output terminal is increased to decrease the output voltage, and the time taken to output the doubled battery voltage VCCX2 is delayed.

According to the experimental results, the conventional voltage multiplier circuit is required to output a steady state output voltage due to unnecessary current consumption due to the current supply delay problem of the second transistor Q22 and the current limit of the fourth resistor R4. As the rise time increases, the output voltage drop occurs at the output stage under high load.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a voltage multiplier circuit for improving the drop phenomenon of the output voltage according to the load at the output terminal.

According to a feature of the present invention for achieving the above object, the present invention is a first transistor for switching the battery voltage by a first pulse signal applied to the base end, the inverting the first pulse signal to the base end A second transistor receiving a second pulse signal, the second transistor and a push-pull circuit, and a third transistor receiving a battery voltage switched from the first transistor at a base end, and the second and third transistors. And a first capacitor for charging the battery voltage and discharging the charged power based on a switching operation, wherein the first and second transistors are of NPN type, and the third transistor is of PNP type.

The present invention further includes a second capacitor provided between the input terminal and the output terminal of the battery voltage, and first and second diodes connected in parallel in opposite directions between the first and second capacitors to switch current directions. The first diode is supplied with the battery voltage to charge the first capacitor and supplied to the first capacitor, and the second diode is charged with the first capacitor and the battery voltage transferred from the third transistor. It adds to the battery voltage of the doubled voltage level is characterized in that for transmitting to the output terminal.

The present invention is connected in series between the first and second resistors connected to the base ends of the first and second transistors respectively to limit the current input to the first and second transistors, and between the third transistor and the input terminal of the battery voltage. And third and fourth resistors connected to each other, wherein the third resistor limits a current input to the third transistor, and the fourth resistor pulls up the battery voltage.

When the voltage level of the first pulse signal is low and the voltage level of the second pulse signal is high, the first capacitor charges the battery voltage applied through the second transistor and the first diode. It features.

When the voltage level of the first pulse signal is high and the voltage level of the second pulse signal is low, the first capacitor multiplies the charged battery voltage with the battery voltage applied through the third transistor. The battery voltage is output through the second diode.

A dead time is set in the first and second pulse signals to prevent the second and third transistors from being turned on at the same time.

As described above, the present invention can reliably supply the current required at the output terminal by increasing the speed of supplying the current of the battery voltage to the output terminal using the PNP type transistor.

The dead time is set for the two pulse signals in the inverted state to adjust the switching time of the second and third transistors, thereby preventing them from being turned on at the same time, thereby reducing unnecessary current consumption.

As a result, the present invention reduces the drop of the output voltage according to the load at the output stage, shortens the time required to output the battery voltage in a steady state, and has an effect of outputting an output voltage having a stable voltage level. .

Hereinafter, a voltage multiplier circuit according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a detailed circuit diagram of a voltage multiplier circuit according to a preferred embodiment of the present invention.

As shown in FIG. 2, the voltage multiplier circuit of the present invention includes first and second transistors Q1 and Q2 and second transistors Q2 that receive first and second pulse signals PS1 and PS2, respectively. ) And a current of the first capacitor C1 and the battery voltage VCC charging and discharging the battery voltage VCC based on the switching operation of the third transistor Q3 and the third transistor Q3 constituting the push-pull circuit. It comprises the first and second diodes (D1, D2) for changing the direction.

The first transistor Q1 is an NPN type transistor. The first transistor Q1 receives the first pulse signal PS1 output from the motor controller (not shown) through the base terminal, and the emitter terminal of the first transistor Q1 is an analog ground terminal ( AGND). The first transistor Q1 receives a battery voltage VCC, for example, a 12V voltage through a collector terminal, and switches the battery voltage VCC according to the voltage level of the first pulse signal PS1.

The second transistor Q2 is an NPN type transistor. The second transistor Q2 receives the second pulse signal PS2 output from the motor controller through the base terminal, and the emitter terminal of the second transistor Q2 is connected to the analog ground terminal AGND. Connected. The second transistor Q2 switches the battery voltage VCC applied through the collector terminal according to the voltage level of the second pulse signal PS2.

The third transistor Q3 is a PNP type transistor. The third transistor Q3 is connected to the collector terminal of the first transistor Q1 through the base terminal and receives the battery voltage VCC through the emitter terminal. The third transistor Q3 switches the battery voltage VCC according to the switching operation of the first transistor Q1.

The second and third transistors Q2 and Q3 are composed of push-pull circuits in which the collector stages are connected to each other.

The first capacitor C1 is connected to the collector terminals of the second and third transistors Q2 and Q3, and the second capacitor C2 is connected in series between the input terminal and the output terminal of the battery voltage VCC, and the second capacitor The third capacitor C3 is connected between the C2 and the analog ground terminal AGND.

2, first and second diodes D1 and D2 are connected between the input terminal of the battery voltage VCC and the first capacitor C1, and between the first capacitor C1 and the output terminal, respectively. The first and second diodes D1 and D2 charge a current in the first capacitor C1 and change a current direction to discharge the charged current.

That is, the first capacitor C1 charges the battery voltage VCC applied through the first diode D1 according to the switching operations of the second and third transistors Q2 and Q3, and charges the battery voltage Vc. The battery voltage VCCX2, for example, 24 V, which is doubled by combining the battery voltage VCC applied through the VCC and the third transistor Q3, is transferred to the output terminal.

The second capacitor C2 limits the voltage level of the doubled battery voltage VCCX2 delivered to the output terminal, improves the ripple voltage, and the third capacitor C3 of the voltage VCCX2 output through the output terminal. Improve ripple voltage.

The output terminal is connected to a gate terminal of a motor driving circuit for a fuel pump, for example, a high side N-channel field effect transistor (hereinafter referred to as a 'FET') of an H-bridge circuit. The doubled battery voltage VCCX2 is transferred to the input voltage of the gate terminal.

In addition, a first resistor R1 for limiting a current input to the first transistor Q1 is provided at the base end of the first transistor Q1, and a second transistor Q2 is provided at the base end of the second transistor Q2. A second resistor R2 is provided to limit the current input to Q2).

The third and fourth resistors R3 and R4 are connected in series between the collector terminal of the first transistor Q1 and the battery voltage VCC. The third resistor R3 limits the current input to the third transistor Q3, and the fourth resistor R4 pulls up the battery voltage VCC.

Hereinafter, the operation of the voltage multiplier circuit according to a preferred embodiment of the present invention having the configuration as described above.

The motor controller, not shown, generates the first pulse signal PS1 and the second pulse signal PS2 inverted therefrom. At this time, the first and second pulse signals PS1 and PS2 have a dead time for a predetermined time to prevent a section in which the second and third transistors Q2 and Q3 are turned on at the same time. Has

The voltage levels of the first and second pulse signals PS1 and PS2 are divided into a low / high state and a high / low state, respectively.

First, the case where the voltage level of the first pulse signal PS1 is low and the voltage level of the second pulse signal PS2 is high will be described.

Since the voltage level of the first pulse signal PS1 is low, the first and third transistors Q1 and Q3 maintain the turn-off state.

On the other hand, since the voltage level of the second pulse signal PS2 is high, the second transistor Q2 is turned on to apply the battery voltage VCC applied through the first diode D1 and the first capacitor C1. To form a current path. Then, the first capacitor C1 charges the battery voltage VCC.

Next, the case where the voltage level of the first pulse signal PS1 is high and the voltage level of the second pulse signal PS2 is low will be described.

Since the voltage level of the second pulse signal PS2 is low, the second transistor Q2 is turned off.

On the other hand, since the voltage level of the first pulse signal PS1 is high, when the first transistor Q1 is turned on, the third transistor Q3 is turned on as the low signal is applied through the base terminal. .

Thus, a current path of the battery voltage VCC is formed through the third transistor Q3, the first capacitor C1, and the second diode D2. Then, the first capacitor C1 outputs the battery voltage VCCX2 that is doubled by adding the charged battery voltage VCC and the battery voltage VCC applied through the third transistor Q3, for example, a 24V voltage. do.

Accordingly, an input voltage of 24 V is applied to the gate terminal of the N-channel FET of the fuel pump motor drive circuit.

In the process as described above, the voltage doubling circuit of the present invention uses the PNP type third transistor Q3 to rapidly supply the current of the battery voltage VCC to the output terminal, thereby reliably supplying the current required at the output terminal. Supply it.

In addition, by setting the dead time at the time of switching the first and second pulse signals PS1 and PS2 to prevent the second and third transistors Q2 and Q3 from being turned on at the same time, unnecessary current consumption can be reduced.

Therefore, the present invention reduces the drop in the output voltage according to the load at the output terminal, and shortens the rise time to the doubled battery voltage corresponding to twice the battery voltage.

For example, FIGS. 3A and 3B are graphs of no-load and high-load output voltages of a voltage doubling circuit for explaining the difference between the present invention and the prior art.

First, as shown in FIG. 3A, when no load is applied to the output terminal, the output voltage A of the voltage doubler circuit of the present invention is about 23.5V, which is the output voltage B of the conventional voltage doubler circuit. Phosphorus has a voltage value of 1V or higher than about 22.5V, and the rise time for entering the steady state of the output voltage A is about 900 ms, which is significantly shortened than the rise time of the conventional circuit of about 3600 Hz. It can be seen that it takes time.

As shown in FIG. 3B, when a high current consumption load is connected to the output terminal, the output voltage D of the conventional voltage doubling circuit is about 14.5V, and the output voltage (about 22.5V) and about 7V at no load are shown. Although the above voltage drop occurs, the output voltage C of the voltage doubling circuit of the present invention is about 21.5V, and it can be seen that only a voltage drop of about 2V occurs when compared to the output voltage (about 23.5V) at no load. . That is, it can be seen that the voltage doubling circuit of the present invention can reduce the voltage drop phenomenon due to the load when a high load is connected to the output terminal.

Through the above process, the present invention can shorten the time required to output the output voltage in the steady state, thereby reducing the drop in the output voltage according to the load at the output terminal, and outputting the output voltage at a stable voltage level. .

The scope of the present invention is not limited to the embodiments described above, but is defined by the claims, and various changes and modifications can be made by those skilled in the art within the scope of the claims. It is self evident.

1 is a circuit diagram of a conventional voltage doubling circuit.

2 is a circuit diagram of a voltage multiplier circuit according to a preferred embodiment of the present invention.

3A and 3B are graphs of no-load and high-load output voltages for explaining the difference between the present invention and the prior art.

`` Explanation of symbols for main parts of drawings ''

Q1, Q2, Q3: Transistors C1, C2, C3: Capacitor

D1, D2: Diodes R1, R2, R3, R4: Resistance

Claims (6)

A first transistor for switching the battery voltage by a first pulse signal applied to the base end; A second transistor receiving a second pulse signal inverting the first pulse signal to a base end; A third transistor comprising a second transistor and a push-pull circuit and receiving a battery voltage switched from the first transistor at a base end thereof; A first capacitor charging the battery voltage and discharging the charged power based on the switching operation of the second and third transistors; First and second resistors connected to base ends of the first and second transistors to limit current input to the first and second transistors, A third resistor connected in series between the first transistor and an input terminal of a battery voltage to limit a current input to the third transistor; A fourth resistor for pulling up the battery voltage; And wherein the first and second transistors are of NPN type, and the third transistor is of PNP type. The method of claim 1, A second capacitor provided between an input terminal and an output terminal of the battery voltage; Further comprising first and second diodes connected in parallel in opposite directions between the first and second capacitors to switch current directions, The first diode receives the battery voltage to supply the first capacitor to the first capacitor, and supplies the first capacitor to the first capacitor. And the second diode combines the voltage charged in the first capacitor and the battery voltage delivered from the third transistor to transfer the battery voltage of the doubled voltage level to the output terminal. delete The method according to claim 1 or 2, When the voltage level of the first pulse signal is low and the voltage level of the second pulse signal is high, the first capacitor charges the battery voltage applied through the second transistor and the first diode. A voltage multiplier circuit. The method of claim 4, wherein When the voltage level of the first pulse signal is high and the voltage level of the second pulse signal is low, the first capacitor multiplies the charged battery voltage with the battery voltage applied through the third transistor. And a battery voltage outputted through the second diode. The method of claim 5, And a dead time is set in the first and second pulse signals to prevent the second and third transistors from being turned on at the same time.

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