KR101015532B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device may include a substrate defined as a first region in which a high voltage element is to be formed and a second region in which a low voltage element is to be formed, a first conductive buried layer formed in the substrate of the first region, and the first conductive buried. A first conductivity type drift region formed in the substrate in the first region above the layer, a second conductivity type body formed in one region in the first conductivity type drift region spaced apart from the first conductivity type buried layer, and the first A trench poly gate pattern having a stepped structure is formed to extend through a first conductive body to a part of the first conductive drift region and become narrower toward a lower portion thereof.

Trench MOSFET.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a vertical trench transistor and a method of manufacturing the same.

As the degree of integration of semiconductor devices increases, the channel lengths of transistors also become very short. As the channel length becomes shorter, a so-called short channel effect, in which the threshold voltage of the transistor is sharply lowered, becomes a problem. In addition, as the channel length becomes shorter, more channel ions need to be implanted to improve punchthrough characteristics between the source and the drain.

In order to improve the show channel effect, a vertical trench transistor is used, and the vertical trench transistor can be used as a high voltage device.

The vertical trench transistor includes a silicon substrate having an N-drift region and a P-type body, a trench formed in the silicon substrate, a gate poly formed in the trench, and a substrate around the gate poly. It includes a source formed by implanting impurities into the surface. The channel length of the vertical trench transistor may be increased by vertically forming a channel between the source formed on the substrate surface and the N drift region formed inside the substrate. At this time, the N drift region corresponds to a drain.

In order to improve the break down voltage between the drain and the source of the vertical trench transistor, the concentration of the N drift region must be decreased or the depth of the N drift region must be increased. Herein, the depth of the N drift region refers to the depth from the boundary between the P-type body and the N drift region to the bottom of the N drift region.

However, when the concentration of the N drift region is decreased or the depth of the N drift region is increased in order to improve the break down voltage between the drain and the source of the vertical trench transistor. There is a problem that the resistance of the N drift region is increased.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device capable of improving a break down voltage between a drain and a source without increasing a resistance, and a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention for achieving the above object is a substrate defined by a first region in which a high voltage element is to be formed and a second region in which a low voltage element is to be formed, and within the substrate of the first region. A first conductive buried layer formed, a first conductive drift region formed in a substrate of a first region above the first conductive buried layer, and the first conductive drift region spaced apart from the first conductive buried layer A second conductive body formed in one region of the inside, and a stepped trench poly that extends to a portion of the first conductive drift region through the first conductive body and becomes narrower toward the bottom It includes a gate pattern.

According to an embodiment of the present disclosure, an oxide film is formed on a semiconductor substrate on which a first region in which a high voltage element is to be formed and a second region in which a low voltage element is to be defined are defined. Forming an N-type buried layer in one region of the semiconductor substrate by selectively implanting a first conductivity type impurity into a semiconductor substrate on which an oxide film is formed; Implanting first conductivity type impurity ions into the semiconductor substrate on the N-type buried layer, and selectively implanting second conductivity type impurity ions into the first conductivity type drift region Forming a second conductivity type body and extending through a portion of the first conductivity type drift region through the second conductivity type body, Parts and increasing comprises the step of forming the trench poly gate pattern of the step-like structure in which the narrower width.

The semiconductor device and the method of manufacturing the same according to the embodiment of the present invention have the effect of improving the breakdown voltage between the drain and the source without increasing the resistance of the drift region.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

1A is a sectional view of a semiconductor device 100 according to an embodiment of the present invention. Referring to FIG. 1A, the semiconductor device 100 may include a substrate 101, a first conductive buried layer 105, a first conductive drift region 120, a second conductive body 125, and a first conductive layer. Deep well 122, stepped trench (not shown), gate oxide film 135, stepped trench poly gate pattern 140, field oxide film 145, first conductivity type impurity regions 170, 171, 172, 192 And second conductivity type impurity regions 176, 178, and 179.

In this case, the substrate 101 may be defined as a region in which a high voltage element is to be formed (hereinafter referred to as an “A region”) and a region in which a low voltage element is to be formed (hereinafter referred to as a “B region”).

The first conductive buried layer 105 is formed in the substrate 101 in the A region. For example, the first conductive buried layer 105 may be an N type buried layer and may be formed in the lower region of the substrate 101.

The first conductivity type drift region 120 is formed in the substrate 101 on the buried layer 105. The second conductivity type body 125 is formed in one region of the first conductivity type drift region 120 spaced apart from the buried layer 105.

The first conductivity type deep well 122 is spaced apart from the second conductivity type body 125 and is formed in the first conductivity type drift region 120 and is in contact with the buried layer 105. It extends from the surface to the buried layer 105 in the vertical direction.

The stepped trench extends through a portion of the first conductivity type drift region 120 through the first conductivity type body. The stepped trench has a stepped structure in which the width of the trench becomes narrower toward the bottom.

For example, the stepped trench may include a first trench penetrating the first conductive body 125 and a second trench formed in the first conductive drift region 120. At this time, the width of the second trench is narrower than the width of the first trench. The first trench may be partially extended to the first conductive drift region 120 through the first conductive body 125.

According to the embodiment of the present invention, the stepped trench structure including the first trench and the second trench is illustrated, but the technical concept of the present invention is not limited thereto, and the stepped trench including a plurality of trenches having different widths. It may have a structure.

A gate oxide layer 135 is formed on the stepped trench inner surface. For example, the gate oxide layer 135 may be formed along sidewalls and bottom surfaces of the stepped trench.

The stepped trench poly gate pattern 140 may be formed to fill an inside of the stepped trench in which the gate oxide layer 135 is formed. The field oxide layer 145 is formed on the substrate 101 on which the stepped trench poly gate pattern 140 is formed for device isolation.

The first conductivity type impurity regions 170, 171, 172, and 192 may be formed in one regions of the second conductivity type body 125 adjacent to the trench type poly gate pattern 140, and the first conductivity type deep well region 122. Is formed. The second conductivity type impurity regions 176, 178, and 179 are formed in other regions of the second conductivity type body 125.

In addition, the semiconductor device 100 may be spaced apart from the first conductivity type well 139 (eg, an N type well) and the first conductivity type well 139 formed in a region B of the substrate 101. A second conductivity type well 137 (for example, a P type well) formed in a region B of the first region, a first gate pattern 164 formed on the first conductivity type well 139, and an upper portion of the second conductivity type well 137 A second gate pattern 162 formed in the second gate pattern 162, second conductive regions 185 and 187 formed in adjacent first conductive wells 139 on both sides of the first gate pattern 164, and the second gate pattern ( 162) The semiconductor device may further include first conductive regions 184 and 186 formed in adjacent second conductive wells 137 on both sides thereof.

FIG. 1B is a cross-sectional view for describing breakdown voltage improvement between a drain and a source of the semiconductor device illustrated in FIG. 1A. Referring to FIG. 1B, a gate voltage VG is applied to the stepped trench poly gate pattern 140, and the first conductivity type impurity regions 170, 171, 172, 192 and the second conductivity type impurity regions 176, 178, and 179 are provided. The source voltage VS is applied, and the drain voltage VS is applied to the first conductivity type drift region 120.

Ground voltage is applied to the stepped trench poly gate pattern 140, the first conductivity type impurity regions 170, 171, 172, 192, and the second conductivity type impurity regions 176, 178, 179 and the first conductivity type drift. When the drain voltage VD is applied to the region 120, holes are gathered around the poly gate formed in the second conductive body 125 and around the poly gate formed in the first conductive drift region 120. In the electrons are collected.

A depletion layer is formed around the interface between the first conductivity type drift region 120 and the second conductivity type body 120. That is, the depletion layer may be widened to extend to the first conductivity type drift region 120 to relax the electric field to improve the breakdown voltage between the drain and the source.

In order to improve the breakdown voltage between the drain and the source, the breakdown voltage between the drain and the source may be improved without lowering the impurity concentration of the first conductivity type drift region. The problem that the resistance of the first conductivity type drift region is increased by increasing the impurity concentration may be solved.

The trench poly gate pattern 140 has a stepped structure in which the poly gate in the first conductive drift region 120 is narrower than the width of the poly gate in the second conductive body 125. As a result, an electric field may be prevented from being concentrated and damaged at a portion of the poly gate pattern of the boundary region between the first conductive type drift region 120 and the second conductive type body 125.

2A to 2K illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 2A, an oxide film 210 is formed on the semiconductor substrate 200. In this case, in the semiconductor substrate 200, a region A in which a high voltage element is to be formed and a region B in which a low voltage element is to be formed may be defined.

A first conductive type (eg N-type) impurity is selectively injected into a semiconductor substrate (eg, P-type substrate) 200 on which the oxide film 210 is formed, and an N-type buried layer N in one region of the semiconductor substrate 200. -type Buried Layer (205).

For example, the N-type buried layer 205 is implanted by implanting N-type impurity ions into a region inside the semiconductor substrate 200 of the A region using a photoresist pattern (not shown) covering the A region and the B region. ) Can be formed.

Subsequently, a first doped region 212 is formed by selectively implanting first conductivity type impurities (eg, N + ions) into the semiconductor substrate 200 of the region A. FIG.

Next, as illustrated in FIG. 2B, a first conductive impurity ion (eg, N− ion) is implanted into the entire surface of the semiconductor substrate 200 in region A to form a second doped region.

Subsequently, a high temperature annealing process is performed to diffuse impurities implanted into the first doped region to form a deep well region 222, and to diffuse impurities implanted into the second doped region. An N-drift region 220 is formed in the semiconductor substrate 200 on the N-type buried layer 205. In this case, the deep well region 222 is diffused to contact the N-type buried layer 205 from the surface of the semiconductor substrate 200.

Next, as shown in FIG. 2C, a second conductive type impurity ion (eg, P-type ion) is selectively implanted into the N-drift region 220 to form a second conductive type body 225 (eg, P-type). Body). The P-type body 225 is formed so as not to overlap with the deep well region 222.

Next, as shown in FIG. 2D, the first nitride film pattern 230 is formed on the oxide film 210 formed on the A region and the B region. The first nitride layer pattern 230 is used to form a field oxide for device isolation.

For example, after depositing a nitride film on the oxide film 210, a photolithography process is performed to form a photoresist pattern (not shown) on the deposited nitride film, and the formed photoresist pattern is an etch mask. The nitride layer is etched using the etching mask to form the first nitride layer pattern 230, and then the photoresist pattern is removed.

Next, as shown in FIG. 2E, the field oxide 235 is formed in the A region and the B region by performing a thermal oxidation process on the oxide layer exposed by the first nitride layer pattern 230. After the formation of the field oxide 235, the first nitride layer pattern 230 is removed.

Subsequently, impurity ions are selectively implanted into the semiconductor substrate 200 in the region B to form a first conductivity type well 239 and a second conductivity type well 237. Here, the first conductivity type well 239 may be an N type well, and the second conductivity type well 237 may be a P type well.

Next, as illustrated in FIG. 2F, the nitride film 240 is deposited on the entire surface of the semiconductor substrate 200 on which the field oxide 235 is formed.

Next, as shown in FIG. 2G, a photoresist pattern is formed by performing a photolithography process, and the nitride layer 240 is etched using the photoresist pattern as an etching mask to form a second nitride layer pattern. To form 240-1. In this case, the second nitride film pattern 240-1 may be patterned to expose a portion of the oxide film 210 formed on the P-type body 225 in order to form a trench in the semiconductor substrate 200 in the A region. . Subsequently, the exposed oxide film 210 is etched using the second nitride film pattern 240-1 as an etch mask to expose a portion of the semiconductor substrate 200.

Next, as shown in FIG. 2H, the semiconductor substrate 200 of the exposed A region is etched using the second nitride film pattern 240-1 as an etch mask to form the P-type body 225. ) To form the first trenches 251 and 252 exposing the N drift region 220. In this case, the first trenches 251 and 252 may be formed to partially etch the N drift region 220 through the P-type body 225.

Subsequently, a nitride film is further deposited on the entire surface of the semiconductor substrate 200 on which the second nitride film pattern 240-1 is formed to form a nitride film on the inner surface of the first trenches 252 and 254. For example, a nitride film may be deposited on a surface of the semiconductor substrate 200 on which the first trenches 251 and 252 are formed to form a nitride film on sidewalls and bottom surfaces of the first trenches 251 and 252. Before depositing the nitride layer inside the first trenches 251 and 252, a thermal oxidation process may be performed to repair damage to the semiconductor substrate 200 by an etching process for forming the first trenches 251 and 252. Can be.

The nitride film additionally deposited on the surface of the semiconductor substrate 200 on which the second nitride film pattern 240-1 is formed is etched back to etch and remove the nitride films formed on the bottoms of the first trenches 251 and 252. In other words, the nitride films formed on the sidewalls of the first trenches 251 and 252 remain by the etch back process, but the nitride films formed on the bottoms of the first trenches 251 and 252 are removed to expose the N-drift region 220. do. The nitride film remaining after the etch back process is referred to as a third nitride film pattern 255.

Next, as illustrated in FIG. 2I, the second trenches 253 and 254 are formed by etching the exposed N-drift region 220 using the third nitride layer pattern 255 as an etching mask. In this case, the second trenches 253 and 254 have a smaller width than the first trenches 251 and 252. The second trenches 253 and 254 are formed in the N-drift region 220 and are formed so as not to expose the N-type buried layer 205.

Accordingly, a stepped trench including a first trench 251 and 252 penetrating the P-type body 225 and a second trench 253 and 254 formed in the N drift region 220 is formed in the semiconductor substrate 200. Can be formed.

In the exemplary embodiment of the present invention, the formation of a two-stage stepped trench structure including the first trenches 251 and 252 and the second trenches 253 and 254 has been exemplified, but the technical spirit of the present invention is not limited thereto. It is possible to form a structure including a plurality of trenches that become narrower toward.

Next, as shown in FIG. 2J, the third nitride film pattern 255 remaining on the semiconductor substrate 200 is removed using wet etching. Before removing the third nitride layer pattern 255 through wet etching, a thermal oxidation process may be performed to restore damage to the semiconductor substrate 200 by an etching process for forming the second trenches 253 and 254. have.

Subsequently, a thermal oxidation process is performed to form the gate oxide layer 260 on the stepped trench inner surface. That is, the gate oxide layer 260 may be formed on sidewalls and bottom surfaces of the first trenches 251 and 252 and the second trenches 253 and 254.

In addition, a gate poly layer is formed in the stepped trench in which the gate oxide layer 260 is formed to form a high voltage gate pattern, that is, a trench poly gate pattern 261. In this case, low voltage gate patterns 262 and 264 may be simultaneously formed on the trench type poly gate pattern 261 in the semiconductor substrate of region B.

For example, a gate poly (not shown) is deposited to fill the first trenches 251 and 252 and the second trenches 253 and 254 on the entire surface of the semiconductor substrate A and B regions, and a photolithography process is performed on the deposited gate poly. Through the photoresist pattern (not shown) is formed. The photoresist pattern may be patterned to form a high voltage gate pattern 261 in region A, and may be patterned to form low voltage gate patterns 262 and 264 in region B. FIG.

The gate poly may be etched using the photoresist pattern as an etch mask to form trench-type poly gate patterns 261 in the A region and low voltage gate patterns 262 and 264 in the B region. In this case, the low voltage gate patterns 262 and 264 may be formed on the first conductivity type well 239 and the second conductivity type well 237.

The poly gate patterns formed on the first trenches 251 and 252 are referred to as first poly gate patterns 265, and the poly gate patterns formed on the second trenches 253 and 254 are referred to as second poly gate patterns 267. do.

Since the widths of the second trenches 253 and 254 are smaller than the widths of the first trenches 251 and 252, the first poly gate pattern 265 and the second poly gate pattern 267 have a stepped shape. That is, the width of the second poly gate pattern 267 is smaller than the width of the first poly gate pattern 265.

The first poly gate pattern 265 may be formed through the P-type body 225, and the second poly gate pattern 267 may be formed in the N-drift region 220. In addition, the first poly gate pattern 265 may partially extend through the P-type body 225 to the N-drift region 220, and the second poly gate pattern 267 may be formed in the N- It may be formed in the drift region 220.

Next, as shown in FIG. 2K, first conductive impurity ions in one regions of the P-type body 225 adjacent to the trench-type poly gate pattern 261 and the second conductive well 237 of the region B are formed. (Eg, N + ions) are simultaneously implanted to form first conductivity type impurity regions 270, 271, 272, 284, and 286.

A second conductivity type impurity ion (eg, P +) is simultaneously implanted into other regions of the P-type body 225, the deep well region 222, and the first conductivity type well 239 of the region B. Conductive impurity regions 276, 278, 273, 282, 285 and 287 are formed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view for describing breakdown voltage improvement between a drain and a source of the semiconductor device illustrated in FIG. 1A.

2A to 2K illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Claims (12)

A substrate defined by a first region in which a high voltage element is to be formed and a second region in which a low voltage element is to be formed: A first conductive buried layer formed in the substrate of the first region; A first conductivity type drift region formed in the substrate of the first region above the first conductivity type buried layer; A second conductive body spaced apart from the first conductive buried layer and formed in one region of the first conductive drift region; A trench poly gate pattern having a stepped structure extending through a portion of the first conductive type drift region and narrowing toward a lower portion thereof through the first conductive type body; And The first conductive type drift region spaced apart from the second conductive type body and formed in the first conductive type drift region and extending in a vertical direction from the substrate surface to the first conductive type buried layer so as to be in contact with the first conductive type buried layer; A semiconductor device comprising a first conductivity type deep well. delete The method of claim 1, wherein the semiconductor device, One regions of a second conductive body adjacent to the trench poly gate pattern, and first conductive impurity regions formed in the first conductive deep well region; And And second conductive impurity regions formed in other regions of the second conductive body. The method of claim 1, And the first conductivity type is N type, and the second conductivity type is P type. The trench poly gate pattern of claim 1, wherein the trench poly gate pattern includes: A stepped trench including a first trench penetrating the first conductive body and a second trench formed in the first conductive drift region and having a width narrower than the width of the first trench; A gate oxide film formed on an inner surface of the stepped trench; And And a poly gate filling the inside of the stepped trench in which the gate oxide layer is formed. The trench poly gate pattern of claim 1, wherein the trench poly gate pattern includes: A first trench formed through the first conductive body and partially extended to the first conductive drift region, and a second trench formed in the first conductive drift region and having a width smaller than the width of the first trench; A stepped trench comprising a; A gate oxide film formed on an inner surface of the stepped trench; And And a poly gate filling the inside of the stepped trench in which the gate oxide layer is formed. Forming an oxide film on a semiconductor substrate defining a first region in which a high voltage element is to be formed and a second region in which a low voltage element is to be formed; Selectively injecting a first conductivity type impurity into a semiconductor substrate having an oxide film to form an N-type buried layer in one region of the semiconductor substrate; Selectively implanting a first conductivity type impurity into the semiconductor substrate of the first region to form a deep well diffused to contact the first conductivity type buried layer from the surface of the semiconductor substrate; Implanting first conductivity type impurity ions into the entire surface of the semiconductor substrate in the first region to form a first conductivity type drift region in the semiconductor substrate on the N type buried layer; Selectively implanting second conductivity type impurity ions into the first conductivity type drift region to form a second conductivity type body; And Forming a trench poly gate pattern having a stepped structure extending through a portion of the first conductivity type drift region through the second conductivity type body and becoming narrower toward a lower portion of the semiconductor device; Manufacturing method. delete The method of claim 7, wherein the manufacturing method of the semiconductor device, Selectively implanting first conductivity type impurity ions into one region of the semiconductor substrate of the second region to form a first conductivity type well; And And injecting second conductivity type impurity ions selectively into another region of the semiconductor substrate in the second region to form a second conductivity type well. 10. The method of claim 9, Simultaneously implanting first conductivity type impurity ions into one regions of a second conductivity type body adjacent to the trench poly gate pattern and a second conductivity type well of the second region to form first conductivity type impurity regions; And And injecting second conductive impurity ions into other regions of the second conductive body and the first conductive well of the second region at the same time to form second conductive impurity regions. The manufacturing method of the semiconductor element. The method of claim 7, wherein forming the trench poly gate pattern of the stepped structure, Forming a stepped trench comprising a plurality of trenches that are narrower in width toward the bottom; Performing a thermal oxidation process to form a gate oxide film on the stepped trench inner surface; And And forming the trench poly gate pattern by filling a gate poly in a stepped trench in which the gate oxide layer is formed. The method of claim 7, wherein forming the trench poly gate pattern of the stepped structure, Forming a first trench penetrating through the first conductive body to expose the first conductive drift region; Forming a second trench below the first trench, the second trench having a width smaller than the first trench in the first conductive drift region so as not to expose the first conductive buried layer; Performing a thermal oxidation process to form a gate oxide layer on inner surfaces of the first trench and the second trench; And And forming a trench poly gate pattern by filling a poly gate in the first trench and the second trench in which the gate oxide layer is formed.

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