KR101011771B1 - Direct Modulation Frequency Synthesizer capable of controlling frequency deviation And Frequency Deviation Method thereof - Google Patents

Abstract

Disclosed are a direct modulated frequency synthesizer of the present invention and a method for adjusting the deviation thereof. The direct modulated frequency synthesizer of the present invention includes a phase sensing pump, a voltage controlled oscillator and a deviation modulator. At this time, the deviation modulator receives the transmission data signal and generates a data information signal for controlling the frequency deviation of the output transmission signal. The voltage level of the data information signal corresponds to the logic state of the transmission data signal, but is adjusted by the code value of the adjustment code. Therefore, according to the direct modulation frequency synthesizer of the present invention and the method for adjusting the deviation thereof, the difference between the 'upper frequency deviation' and the 'lower frequency deviation' can be easily adjusted to the standard frequency deviation.

Description

Direct Modulation Frequency Synthesizer capable of controlling frequency deviation And Frequency Deviation Method

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a direct modulated frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a deviation modulator of FIG. 1.

3 is a diagram illustrating the calculation logic of FIG. 2 in more detail.

FIG. 4 is a diagram illustrating the transform logic of FIG. 2 in detail.

5 is a flowchart illustrating a method of adjusting a deviation of a direct modulated frequency synthesizer according to an embodiment of the present invention.

6 is a view for explaining the effect of deviation alignment by the direct modulator frequency synthesizer of the present invention.

The present invention relates to a direct modulation frequency synthesizer, and more particularly, to a direct modulation frequency synthesizer for receiving an input base signal and a transmission data signal and generating an output transmission signal, and a method for adjusting the deviation thereof.

In recent years, the demand for real-time multimedia data service is increasing rapidly by users using wireless communication. At this time, users want to send and receive a large amount of data in real time at a high speed.

For such high-speed data transmission and reception, a frequency conversion method capable of fast frequency switching is required. For such a fast frequency conversion, one of the developed frequency synthesizers is a direct modulation frequency synthesizer.

Currently used direct modulated frequency synthesizer is using a phase locked loop (PLL), a voltage controlled oscillator (VCO) and a divider, and receives an input base signal and a division ratio control signal. Generate an output transmission signal. At this time, the base frequency of the output transmission signal is in accordance with the frequency of the input base signal. The frequency deviation direction of the output transmission signal is determined according to the division ratio of the divider controlled by the division ratio control signal.

In this specification, the frequency deviation in which the frequency of the output transmission signal is greater than the base frequency, that is, the frequency deviation in the positive direction is referred to as 'upper frequency deviation'.

In addition, a frequency deviation in which the frequency of the output transmission signal is smaller than the base frequency, that is, a frequency deviation in the negative direction may be referred to as a 'down frequency deviation'.

However, in such a conventional direct modulation frequency synthesizer, if the difference between the 'upper frequency deviation' and the 'lower frequency deviation' deviates from the intended 'standard frequency deviation', it has a problem that it is difficult to adjust it.

Accordingly, there is a need for a direct modulated frequency synthesizer that can easily adjust the difference between the upper frequency deviation and the lower frequency deviation to the standard frequency deviation.

An object of the present invention is to solve the problems of the conventional direct modulation frequency synthesizer as described above, and can directly adjust the difference between 'upper frequency deviation' and 'lower frequency deviation' to the intended 'standard frequency deviation'. The present invention provides a modulation frequency synthesizer and a method of adjusting a deviation thereof.

One aspect of the present invention for achieving the above technical problem is a direct modulation frequency synthesizer for generating an output transmission signal by receiving an input base signal and a transmission data signal, the output transmission signal corresponding to the frequency of the input base signal The direction of the frequency deviation with respect to the base frequency, having a base frequency, relates to the direct modulated frequency synthesizer corresponding to the logic state of the transmission data signal.

The direct modulated frequency synthesizer of the present invention detects a phase difference between a reference clock signal and a feedback clock signal, and generates a oscillation control signal having a voltage level corresponding to the phase difference, wherein the frequency of the reference clock signal is the input signal. A phase sensing pump corresponding to a frequency of a base signal, wherein a frequency of the feedback clock signal corresponds to a frequency of the output transmission signal; A voltage controlled oscillator controlled by the oscillation control signal to generate the output transmission signal, the output transmission signal having the base frequency corresponding to the voltage level of the oscillation control signal and controlled in response to a data information signal The voltage controlled oscillator having a deviation; And a deviation modulator for receiving the transmission data signal to generate the data information signal, wherein the voltage level of the data information signal corresponds to a logic state of the transmission data signal, wherein the deviation modulator is adjusted by a code value of an adjustment code. It is provided.

One aspect of the present invention for achieving the above technical problem is a method of adjusting the deviation of the direct modulated frequency synthesizer for receiving an input base signal and a transmission data signal to generate an output transmission signal, the output transmission signal is the The base frequency corresponding to the frequency, wherein the direction of the frequency deviation with respect to the base frequency relates to a method for adjusting the deviation of the direct modulated frequency synthesizer corresponding to the logic state of the transmission data signal. A method for adjusting a deviation of the direct modulated frequency synthesizer of the present invention includes the steps of: A) activating a control enable signal to control the direct modulated frequency synthesizer in a deviation adjust mode; Setting the adjustment code of the direct modulation frequency synthesizer to the maximum code value in the deviation adjustment mode; C) measuring the frequency of the output transmission signal by controlling the transmission data signal to a first logic value in order to confirm the 'upper frequency deviation' of the output transmission signal after performing steps A) and B). step; After performing steps A) and B), in order to confirm the 'down frequency deviation' of the output transmission signal, the output data is controlled by controlling the transmission data signal to a second logic value opposite to the first logic value. D) measuring the frequency of; And E) setting a code value of the adjustment code to set a difference between the upper frequency deviation and the lower frequency deviation identified in steps C) and D) as a standard frequency deviation.

For a better understanding of the present invention and its operational advantages, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the invention, and the accompanying drawings. In understanding each of the figures, it should be noted that like parts are denoted by the same reference numerals whenever possible. In addition, in the following description, numerous specific details, such as specific processing flows, are described to provide a more general understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention are omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a direct modulated frequency synthesizer according to an embodiment of the present invention. The direct modulated frequency synthesizer of the present invention receives the input base signal INBAS and the transmit data signal TXDAT and generates an output transmit signal TXOUT. The output transmission signal TXOUT has a base frequency F0 corresponding to the frequency of the input base signal INBAS. The direction of the frequency deviation of the output transmission signal TXOUT with respect to the base frequency F0 corresponds to the logic state of the transmission data signal TXDAT.

Referring to FIG. 1, the direct modulated frequency synthesizer of the present invention includes a phase sensing pump 100, a voltage controlled oscillator 200, and a deviation modulator 300.

The phase sensing pump 100 detects a phase difference between the reference clock signal RCLK and the feedback clock signal FCLK and generates an oscillation control signal XOC. In this case, the oscillation control signal XOC has a voltage level according to the phase difference between the reference clock signal RCLK and the feedback clock signal FCLK sensed by the phase detection pump 100. Here, the frequency of the reference clock signal RCLK corresponds to the frequency of the input base signal INBAS, and the frequency of the feedback clock signal FCLK corresponds to the frequency of the output transmission signal TXOUT.

According to a preferred embodiment, the phase sensing pump 100 includes a phase sensing unit 110, a charge pump 120 and a low pass filter 130.

The phase detector 110 detects the phase difference between the reference clock signal RCLK and the feedback clock signal FCLK. The charge pump 120 pumps charge in response to the output signal of the phase detector 110 to generate an output signal whose duty is controlled. The low pass filter 130 generates the oscillation control signal XOC by low pass filtering the output signal of the charge pump 120.

Since the configuration and operation of the phase detector 110, the charge pump 120, and the low pass filter 130 are well known to those skilled in the art, detailed descriptions thereof are omitted in the present specification for the sake of simplicity.

The voltage controlled oscillator 200 is controlled by the oscillation control signal XOC and generates the output transmission signal TXOUT that is oscillated. At this time, the base frequency of the output transmission signal TXOUT, that is, the frequency representing the information of the input base signal INBAS, mainly corresponds to the voltage level of the oscillation control signal XOC.

The frequency deviation of the output transmission signal TXOUT is controlled corresponding to the data information signal DCON.

Of course, the frequency deviation of the output transmission signal TXOUT may also be reflected by a change in the voltage level of the oscillation control signal XOC reflected by the adjustment of the division ratio in the feedback divider 500.

In addition, since the configuration and operation of the voltage controlled oscillator 200 are also well known to those skilled in the art, for the sake of simplicity, detailed description thereof will be omitted.

The deviation modulator 300 receives the transmission data signal TXDAT and generates the data information signal DCON. At this time, the voltage level of the data information signal DCON corresponds to the logic state of the transmission data signal TXDAT and is adjusted by the code value of the adjustment code CALCD.

2 is a diagram illustrating the deviation modulator 300. Referring to FIG. 2, the deviation modulator 300 includes a calculation logic 310 and a conversion logic 330.

The calculation logic 310 receives the transmission data signal TXDAT and the adjustment code CALCD and generates preliminary data PRDAT and preliminary code PRCD. At this time, the preliminary data PRDAT has the same logic state as the transmission data signal TXDAT in the normal mode. The preliminary data PRDAT has a logic state of "H" in the uplink frequency confirmation section in the deviation adjustment mode and a logic state of "L" in the downlink frequency confirmation section in the deviation adjustment mode.

In the present specification, the 'upper frequency deviation' means a deviation in which the frequency of the output transmission signal TXOUT is greater than the base frequency, that is, the direction of the frequency deviation is positive. The 'down frequency deviation' refers to a deviation in which the frequency of the output transmission signal TXOUT is smaller than the base frequency, that is, the direction of the frequency deviation is negative.

In addition, the code value of the preliminary code PRCD has the same code value as the control code CALCD in the normal mode. The code value of the preliminary code PRCD is controlled to the maximum code value (eg, 1111111) in the deviation adjustment mode.

3 is a diagram illustrating the calculation logic 310 of FIG. 2 in more detail. Referring to FIG. 3, the calculation logic 310 includes a code response unit 311, a first mixer 313, and a second mixer 315.

The code response unit 311 is enabled in response to the adjustment enable signal DMCEN activated in the deviation adjustment mode. The code response unit 311 generates an enable data ENDAT and an enable code ENCD. At this time, the enable data ENDAT is controlled by a logic " H " in the upper frequency confirmation section of the deviation adjustment mode, and controlled by a logic " L " in the lower frequency check section. The enable code ENCD is controlled to a maximum code value (eg, 1111111) during the deviation adjustment mode.

In addition, the muxing control signal MXCON provided from the code response unit 311 is activated as "H" in the deviation adjustment mode, and deactivated as "L" in the normal mode.

More specifically, the code response unit 311 includes a reference clock counter 311a, a feedback clock counter 311b, and a control means 311c.

The reference clock counter 311a is enabled in response to the activation of the reference counter enable signal RCEN provided by the control means 311c to " H ". The reference clock counter 311a counts a clock of the reference clock signal RCLK based on the set number of confirmation clocks CFNUM in each of the uplink frequency check period and the downlink frequency check period, thereby determining a clock confirmation signal ( CFC) and the order confirmation signal NFC are generated to the control means 311c.

In this case, the clock confirmation signal CFC includes information indicating whether both the uplink frequency check section and the downlink frequency check section in the deviation adjustment mode have elapsed. The order confirmation signal NFC includes information indicating the progress of each of the uplink frequency check section and the downlink frequency check section. In one embodiment of the present invention, the order confirmation signal NFC is controlled by a logic " H " in the uplink frequency check interval and a logic " L "

The feedback clock counter 311b is enabled in response to the activation of the feedback counter enable signal FCEN provided by the control means 311c to " H ". In addition, the feedback clock counter 311b may also perform up-counting and down counting with respect to the clock of the feedback clock signal FCLK according to the direction control signal XDP provided from the control means 311c. down-counting).

According to an embodiment of the present invention, in the upward frequency confirmation section in which the direction control signal XDP is activated as "H", the feedback clock counter 311b is up with respect to the clock of the feedback clock signal FCLK. Perform up-counting. The feedback clock counter 311b performs down-counting with respect to the clock of the feedback clock signal FCLK in the downward frequency confirmation period in which the direction control signal XDP is deactivated to “L”. To perform.

The control means 311c receives the adjustment enable signal DMCEN, the clock confirmation signal CFC, and the order confirmation signal NFC to receive the enable data ENDAT and the enable code. ENCD), the reference counter enable signal RCEN, the feedback counter enable signal FCEN, and the direction control signal XDP. In this case, the reference counter enable signal RCEN and the feedback counter enable signal FCEN are enabled in response to activation of the adjustment enable signal DMCEN to " H ". The direction control signal XDP is controlled in the same logic state as the order confirmation signal NFC.

Accordingly, in one embodiment of the present invention, the direction control signal XDP is controlled by a logic "H" in the uplink frequency confirmation section, and is controlled by a logic "L" in the downlink frequency confirmation section.

Meanwhile, in FIG. 3, the adjustment completion signal DMCDOME generated by the control means 311c is a signal indicating that the deviation adjustment mode is completed.

For reference, the result code RECD provided from the feedback clock counter 311b indicates a difference between counting values of the up counting and down counting.

In other words, the result code RECD is an upper frequency (i.e., maximum upper frequency) and a lower frequency (i.e., maximum down) in the deviation adjustment mode in which the enable code ENCD is controlled to a maximum code value. Information on the difference).

Referring to FIG. 3, the first muxer 313 muxes the transmission data signal TXDAT and the enable data ENDAT in response to the muxing control signal MXCON, and prepares a result of the muxing. Output as data PRDAT. Accordingly, the preliminary data PRDAT has the same logic state as the transmission data signal TXDAT in the normal mode, and has the same logic state as the enable data ENDAT in the deviation adjustment mode.

The second mixer 315 muxes the adjustment code CALCD and the enable code ENCD in response to the muxing control signal MXCON, and outputs the muxed result to the preliminary code PRCD. do. Accordingly, the preliminary code PRCD has the same code value as the adjustment code CALCD in the normal mode, and has the same code value as the enable code ENCD in the deviation adjustment mode.

Referring back to FIG. 2, the conversion logic 330 receives the code value of the preliminary code PRCD and the preliminary data PRDAT to generate the data information signal DCON. The data information signal DCON has a code value of the preliminary code PRCD and a voltage level according to a logic state of the preliminary data PRDAT. At this time, the magnitude of the deviation with respect to the reference level VCM of the data information signal DCON is controlled corresponding to the code value of the preliminary code PRCD. The sign of the deviation with respect to the reference level VCM of the data information signal DCON is controlled corresponding to the logical state of the preliminary data.

In the present specification, the 'reference level (VCM)' of the data information signal (DCON) according to the logic state of the transmission data signal (TXDAT) before the alignment mode is performed in the direct modulation frequency synthesizer of the present invention Refers to the reference level of the voltage level.

4 is a diagram illustrating in detail the conversion logic 330 of FIG. 2. Referring to FIG. 3, the transform logic 330 includes a coding response unit 331 and an amplification unit 333.

The coding response means 331 receives the preliminary code PRCD and the preliminary data PRDAT to generate the preliminary control signal PRCON. At this time, the preliminary control signal PRCON has a voltage level corresponding to a code value of the preliminary code PRCD and a logic state of the preliminary data PRDAT.

In the embodiment of the present invention, when the preliminary data PRDAT is "H", when the code value of the preliminary code PRCD is "1111111", the preliminary control signal PRCON has a maximum voltage level. . When the preliminary data PRDAT is "L", when the code value of the preliminary code PRCD is "1111111", the preliminary control signal PRCON has a maximum voltage level.

The amplifying means 333 compares the voltage level of the preliminary control signal PRCON with the 'reference level VCM', inverts and amplifies the difference, and generates the data information signal DCON.

As a result, the data information signal DCON provided from the deviation modulator 300 has a voltage level corresponding to the logic state of the transmission data signal TXDAT in the normal mode. The data information signal DCON is adjusted by adjusting the code value of the adjustment code CALCD such that the difference between the maximum uplink frequency and the maximum down frequency determined in the adjustment mode is a set standard frequency deviation. The voltage level of is adjusted.

Referring back to FIG. 1, the direct modulator frequency synthesizer of the present invention further includes an input divider 400, a feedback divider 500, and a divide modulator 600.

The input divider 400 divides the frequency of the input base signal INBAS into 1 / R to generate the reference clock signal RCLK.

The feedback divider 500 divides the frequency of the output transmission signal TXOUT into 1 / N to generate the feedback clock signal FCLK. In this case, N may be controlled by an external control signal (not shown) or itself. In addition, the N may be determined as a number less than or equal to the decimal point by the addition / subtraction control signal XASC.

The division modulator 600 generates the addition / subtraction control signal XASC corresponding to the division ratio control signal XFCN. Accordingly, it is also possible for N to have a small number of values, not integers.

Since the configuration and operation of the input divider 400, the feedback divider 500, and the divider modulator 600 are well known to those skilled in the art, detailed descriptions thereof will be omitted for the sake of brevity of description.

Subsequently, a method for adjusting the deviation of the direct modulated frequency synthesizer of the present invention is described.

5 is a flowchart illustrating a method of adjusting a deviation of a direct modulated frequency synthesizer according to an embodiment of the present invention.

Referring to FIG. 5 together with FIGS. 1 to 4, in step S510, the direct modulation frequency synthesizer of the present invention is controlled to the deviation adjustment mode by setting the adjustment enable signal DMCEN to “H”.

In operation S520, the control code CALCD sets the maximum code value, that is, '1111111'.

In operation S530, the frequency of the output transmission signal TXOUT is measured by controlling the transmission data signal to 'H' to confirm the 'maximum upward frequency' of the output transmission signal TXOUT (see F1 of FIG. 6). ).

In operation S540, the frequency of the output transmission signal TXOUT is measured by controlling the transmission data signal to 'L' to confirm the 'maximum downward frequency' of the output transmission signal TXOUT (see FIG. 6). See F2).

In operation S550, the maximum maximum frequency and the maximum lower frequency identified in steps S530 and S540 are calculated to set a code value of the new adjustment code CALCD.

Accordingly, the difference between the 'upper frequency' and the 'down frequency' is adjusted to the intended 'standard frequency deviation' (see Fa and Fb in FIG. 6).

Subsequently, a simple example of obtaining the code value of the adjustment code CALCD will be described.

First, the code value of the control code (CALCD) by the decimal method is obtained through Equation (1).

(Equation 1)

A = f * 2 ⁿ * (B / C)

here,

A: Code value of decimal control code (CALCD)

n: number of bits of the reserved code (PRCD)

B: standard frequency deviation

C: difference between the maximum upper frequency and the maximum lower frequency

f: correlation coefficient

Then, the code value of the control code (CALCD) by the binary method is obtained by converting the A obtained through Equation 1 into a binary value.

In addition, it will be apparent to those skilled in the art that the method of setting the code value of the new adjustment code CALCD by calculating the 'maximum upward frequency' and the 'maximum downward frequency' may vary widely. Therefore, in the present specification, for the sake of simplicity, a detailed description thereof will be omitted.

The direct modulated frequency synthesizer of the present invention as described above includes a phase sensing pump, a voltage controlled oscillator and a deviation modulator. At this time, the deviation modulator receives the transmission data signal and generates a data information signal for controlling the frequency deviation of the output transmission signal. The voltage level of the data information signal corresponds to the logic state of the transmission data signal, but is adjusted by the code value of the adjustment code.

Therefore, according to the direct modulation frequency synthesizer of the present invention and the method for adjusting the deviation thereof, the difference between the 'upper frequency deviation' and the 'lower frequency deviation' can be easily adjusted to the standard frequency deviation.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

A direct modulation frequency synthesizer for receiving an input base signal and a transmission data signal to generate an output transmission signal, the output transmission signal having a base frequency corresponding to the frequency of the input base signal, wherein In the direct modulation frequency synthesizer corresponding to a logic state of the transmission data signal, A phase sensing pump for sensing a phase difference between a reference clock signal and a feedback clock signal, and generating an oscillation control signal having a voltage level corresponding to the phase difference, wherein the frequency of the reference clock signal corresponds to the frequency of the input base signal. The phase sensing pumper whose frequency of the feedback clock signal corresponds to the frequency of the output transmission signal; A voltage controlled oscillator controlled by the oscillation control signal to generate the output transmission signal, the output transmission signal having the base frequency corresponding to the voltage level of the oscillation control signal and controlled in response to a data information signal The voltage controlled oscillator having a deviation; And A deviation modulator for receiving the transmission data signal and generating the data information signal, wherein the voltage level of the data information signal corresponds to a logic state of the transmission data signal, wherein the deviation modulator is adjusted by a code value of an adjustment code; Direct modulation frequency synthesizer characterized in that it comprises. The pump of claim 1, wherein the phase sensing pump A phase detector configured to detect a phase difference between the reference clock signal and the feedback clock signal; A charge pump generating an output signal whose duty is controlled in response to an output signal of the phase detector; And And a low pass filter filtering the output signal of the charge pump to generate the oscillation control signal. The method of claim 1, wherein the deviation modulator A calculation logic for receiving the transmission data signal and the adjustment code to generate the preliminary data and the preliminary code, wherein in the normal mode, the preliminary data has a logic state corresponding to the logic state of the transmission data signal, and in the deviation adjustment mode The preliminary data is the calculation logic having a logic state opposite between an uplink frequency check period and a downlink frequency check period, wherein a code value of the preliminary code corresponds to a code value in the normal code in the normal mode, and the deviation adjustment mode. The calculation logic controlled by the maximum code value; And A conversion logic for generating the data information signal having a code value of the preliminary code and a voltage level in accordance with a logic state of the preliminary data, wherein the magnitude of the deviation from the reference level of the data information signal is equal to the code value of the preliminary code. And a conversion logic which is correspondingly controlled and whose sign of the deviation to the reference level of the data information signal is controlled in correspondence to a logic state of the preliminary data. The method of claim 3, wherein the calculation logic is A code response unit that is enabled in response to the adjustment enable signal and generates enable data and an enable code, wherein in the deviation adjustment mode, the enable data is incompatible during the upper frequency confirmation period and the lower frequency confirmation period. The code response unit having a logic state, the enable code having a maximum code value in the deviation adjustment mode; A first feeder which muxes the transmit data signal and the enable data and outputs the spare data as the preliminary data, wherein the preliminary data has a logic state corresponding to a logic state of the transmit data signal in the normal mode, and adjusts the deviation In the mode, the first data source having a logic state corresponding to a logic state of the enable data; And A second feeder which muxes the adjustment code and the enable code and outputs the resultant code to the preliminary code, wherein the preliminary code has a code value corresponding to a code value of the adjustment code in the normal mode, and in the deviation adjustment mode And a second mixer having a code value corresponding to a code value of the enable code. The method of claim 4, wherein the code response unit A reference clock counter that is enabled in response to a reference counter enable signal, wherein the clock of the reference clock signal according to the set number of confirmation clocks is counted in each of the uplink frequency check section and the downlink frequency check section, and includes a clock confirmation signal and The reference clock counter for generating an order confirmation signal, wherein the clock confirmation signal includes information indicating whether both the uplink frequency check section and the downlink frequency check section have passed, and the order check signal includes the uplink frequency check section and the uplink frequency check section. The reference clock counter including information indicating an elapse of each of the lower frequency checking sections; A feedback clock counter that is enabled in response to a feedback counter enable signal and generates a result code by performing up counting and down counting on the clock of the feedback clock signal according to a direction control signal, wherein the result code is the direction control. The feedback clock counter having a code value for a difference between counting values of up counting and down counting according to a signal; And The control enable signal, the clock confirmation signal, and the order confirmation signal are received to generate the enable data, the enable code, the reference counter enable signal, the feedback counter enable signal, and the direction control signal. Wherein the reference counter enable signal and the feedback counter enable signal are enabled in response to the adjustment enable signal, and the direction control signal has a logic state corresponding to the order confirmation signal. Direct modulation frequency synthesizer characterized in that it comprises a. The method of claim 3, wherein the conversion logic is Coding response means for generating a preliminary control signal having a code value of said preliminary code and a voltage level corresponding to a logic state of said preliminary data; And And amplifying means for amplifying the difference by comparing the voltage level of the preliminary control signal with a reference level and generating the data information signal. The method of claim 1, wherein the direct modulation frequency synthesizer An input divider for dividing the frequency of the input base signal by 1 / R to generate the reference clock signal; A frequency divider generated by the feedback clock signal by dividing the frequency of the output transmission signal by 1 / N, wherein N is the feedback divider controlled by an additive subtraction control signal; And And a division modulator for generating the additive subtraction control signal in response to the division ratio control signal. A method of adjusting a deviation of a direct modulated frequency synthesizer that receives an input base signal and a transmission data signal and generates an output transmission signal, the output transmission signal having a base frequency corresponding to the frequency of the input base signal, In the method of adjusting the deviation of the direct modulation frequency synthesizer corresponding to the direction of the frequency deviation with respect to the logic state of the transmission data signal, A) activating a coarse enable signal to control the direct modulated frequency synthesizer in a deviation coordination mode; Setting the adjustment code of the direct modulation frequency synthesizer to the maximum code value in the deviation adjustment mode; C) measuring the frequency of the output transmission signal by controlling the transmission data signal to a first logic value in order to confirm the 'upper frequency deviation' of the output transmission signal after performing steps A) and B). step; After performing steps A) and B), in order to confirm the 'down frequency deviation' of the output transmission signal, the output data is controlled by controlling the transmission data signal to a second logic value opposite to the first logic value. D) measuring the frequency of; And And a step E) of setting a code value of the adjustment code to set a difference between the upper frequency deviation and the lower frequency deviation identified in the steps C) and D) as a standard frequency deviation. Deviation Modulation Method in Modulation Frequency Synthesizer.

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