KR101007562B1 - Resistive memory device and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistive memory element and a method of manufacturing the same, wherein the resistive memory element comprises: an insulating film on a substrate; A plurality of first electrode plugs penetrating the insulating film; A resistive layer on the insulating layer and connected to the plurality of first electrode plugs; And a second electrode on the resistive layer, wherein the resistive memory device and a method of manufacturing the same according to the present invention provide a sensing margin while improving switching characteristics of the device by forming a plurality of plug type lower electrodes under the resistive layer. It can be secured.

Resistive Memory Devices, ReRAM, Resistor Layers, Plugs

Description

RESISTIVE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a method of manufacturing the same, and more particularly, to a resistive memory device using a resistance change, such as a nonvolatile ReRAM (Resistive Random Access Memory) device, and a method of manufacturing the same.

Recently, research on next-generation memory devices that can replace DRAM and flash memory has been actively conducted.

One of these next-generation memory devices is a resistive memory device that uses a material, that is, a resistance layer, in which a resistance changes rapidly according to an applied bias to switch between at least two different resistance states. As the resistive layer material having such a property, a binary oxide containing a transition metal oxide or the like or a perovskite-based material such as PrCaMnO ₃ (PCMO) is used.

1 is a cross-sectional view illustrating a conventional resistive memory device.

As shown in FIG. 1, the conventional resistive memory device is positioned on the substrate 10, the substrate 10, the insulating film 11 including the contact plug 12, and the upper portion of the insulating film 11. The stacked structure of the lower electrode 13, the resistance layer 14, and the upper electrode 15 connected to the contact plug 12 is included. Here, the stacked structure of the lower electrode 13, the resistance layer 14, and the upper electrode 15 is referred to as a resistor 100.

In such a resistive memory device, the resistance layer 14 is switched between a low resistance state and a high resistance state according to a bias applied to the lower electrode 13 and the upper electrode 15, thereby corresponding to each resistance state. Data is stored.

Here, although the switching mechanism is not clearly identified, it is assumed that a low resistance filamentary current path is formed or the already formed filament current path disappears according to the bias applied.

However, such conventional resistive memory devices have limitations in providing excellent switching characteristics. This is because the area of the lower electrode 13 is greater than or equal to that of the resistive layer 14, so that the contact area between the lower electrode 13 and the resistive layer 14 depends entirely on the size of the resistive layer 14, and accordingly This is because the entire resistive layer 14 becomes a switching region when a predetermined bias is applied to the electrode 13 and the upper electrode 15. When the entire resistive layer 14 becomes the switching region, the position, size, and number of the filament current paths are not constant, so the distinction between the two resistance states is ambiguous, and the voltage / current distribution according to the set / reset of the device is uniform. There is a problem that could not be.

In response to this problem, IEEE's paper, "Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application," published in 2005, has a switching characteristic by reducing the contact area with the resistive layer by plugging the lower electrode. A technique for improving the speed is disclosed, which will be described in more detail with reference to FIG. 2 below.

2 is a cross-sectional view illustrating another conventional resistive memory device.

As shown in FIG. 2, another resistive memory device according to the related art is positioned on a substrate 20, an insulating film 21 disposed on the substrate 20, and having an contact plug 22, and an upper portion of the insulating film 21. And a stacked structure of the resistance layer 24 and the upper electrode 25 connected to the contact plug 22. Here, the resistor unit 200 includes a contact plug 22, a resistor layer 24, and an upper electrode 25. That is, instead of separately forming the lower electrode as shown in FIG. 1, the contact plug 22 is used as the lower electrode.

In this case, the entirety of the resistive layer is not the switching region as shown in FIG. 1, but only the portion of the resistive layer 24 in contact with the contact plug 22 becomes the switching region (see the shaded portion "A"). Therefore, in such an element, the position, size, number, and the like of the filament current path can be adjusted by adjusting the area and the position of the contact plug 22, so that the switching characteristics of the element are improved. The improvement in switching characteristics of such a device is well illustrated in the graph of FIG.

3A and 3B are diagrams for comparing the characteristics of the resistive memory device having the planar bottom electrode of FIG. 1 and the resistive memory device having the plug type bottom electrode of FIG.

Referring to FIG. 3A, it can be seen that the current distribution of the resistive memory element having the pluggable lower electrode (see "Plug BE") is more uniform than that of the resistive memory element having the planar lower electrode (see "Planar BE"). .

3B is a diagram illustrating a high resistance (R_off) / low resistance (R_on) state distribution of the resistive memory device. Referring to FIG. 3B, the resistive memory device having a planar type lower electrode (refer to the left drawing) is shown. It can be seen that the distinction between the two resistance states becomes clearer because the difference between the high resistance and low resistance states of the resistive memory element having the plug type lower electrode is larger than the resistance state difference.

That is, when the lower electrode is formed as a plug type, it can be seen that the switching characteristics of the resistive memory device are further improved as compared with the case where the lower electrode is a planar type.

However, the size of memory devices continues to decrease with the recent increase in the degree of integration of memory devices. Therefore, when the lower electrode is formed as a plug, the contact area between the lower electrode and the resistive layer may be excessively reduced. In this case, the filament current path may be too small, leading to a problem in that a sensing margin is reduced. Can be.

The present invention has been proposed to solve the above-mentioned problems of the prior art, by forming a plurality of plug-type lower electrodes below the resistive layer, thereby improving the switching characteristics of the device and ensuring a sensing margin, and a fabrication thereof To provide a method.

In the resistive memory device of the present invention for solving the above problems, a resistive memory device comprising a plurality of unit cells,
Each unit cell,
A plurality of first electrode plugs penetrating the insulating film on the substrate; A resistive layer on the insulating layer and connected to the plurality of first electrode plugs; And a second electrode on the resistive layer.

In addition, the method of manufacturing the resistive memory device of the present invention for solving the above problems, forming a plurality of first electrode plugs penetrating the insulating film; Forming a resistance layer on the insulating layer and connected to the plurality of first electrode plugs; And forming a second electrode on the resistor layer, wherein the plurality of first electrode plugs, the resistor layer, and the second electrode constitute a resistor unit of the unit cell.

In the resistive memory device and the method of manufacturing the same according to the present invention described above, a sensing margin can be secured while improving the switching characteristics of the device by forming a plurality of plug-type lower electrodes of the unit cell.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

4 is a cross-sectional view illustrating a unit cell of a resistive memory device according to example embodiments. Typically, a resistive memory device has a cell array, and each unit cell constituting the cell array includes a cell access device and a resistor. In FIG. 4, only the resistor of the unit cell is illustrated.

As shown in FIG. 4, a unit cell of a resistive memory device according to an exemplary embodiment may include a plurality of contact plugs 42 penetrating through an insulating film 41 on a substrate 40 and an upper portion of the insulating film 41. The resistive layer 43 is connected to the plurality of contact plugs 42 and the upper electrode 44 above the resistive layer 43.

Here, the plurality of contact plugs 42 are used as the lower electrode. Therefore, the resistor unit 400 of the unit cell includes a plurality of contact plugs 42, a resistor layer 43, and an upper electrode 44. In this case, the plurality of contact plugs 42 and the upper electrode 44 may be made of a material selected from Ti, Ni, Al, Au, Ag, Pt, Cu, Cr, or an alloy thereof, and in particular, a plurality of contact plugs. (42) preferably has a thickness of 80 to 4000 mm 3. The resistive layer 43 may be a binary oxide (eg, MgO, ZnO, TiO ₂ , NiO, SiO ₂ , Nb ₂ O ₅ , HfO _2, etc.) or a perovskite-based material including a transition metal oxide ( For example, it may consist of PCMO, LCMO (LaCaMnO ₃ ), and the like.

Referring to the operation of the resistive memory device, when a bias is applied to the plurality of contact plugs 42 and the upper electrode 44 which are the lower electrodes, the resistive layer 43 is switched between the low resistance state and the high resistance state so that each resistance is reduced. Data corresponding to the state is stored.

At this time, since the portion of the resistive layer 43 which contacts the plurality of contact plugs 42 becomes the switching region (see the shaded portion “B”), the resistive layer 43 has a plurality of switching regions. In the drawing, as an example, two contact plugs 42 are formed to have two switching regions. However, the present invention is not limited thereto, and the number of contact plugs 42 includes the size of the device and the sensing margin. Can be selected.

As described above, when the plurality of contact plugs 42 are formed, the filament current path increases, so that a sensing margin may be secured even if the area of the device decreases as the integration degree of the device increases. In addition, the switching characteristics of the resistive memory device may be improved by controlling the location, size, and number of the filament current paths by adjusting the area, position, and number of the contact plugs 42.
Hereinafter, a case in which a resistor unit including a plurality of pluggable lower electrodes, resistance layers, and upper electrodes is applied to a ReRAM device will be described. ReRAM devices are typical of resistive memory devices and include a unit cell including one transistor and one resistor unit.

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5A to 5C are cross-sectional views illustrating a ReRAM device and a method of manufacturing the same according to an embodiment of the present invention.

As shown in FIG. 5A, an isolation layer 501 is formed on the semiconductor substrate 500 to define an active region.

Subsequently, first and second transistors are formed in the active region of the semiconductor substrate 500. Hereinafter, the configuration of the first and second transistors will be described in more detail. First and second drain regions Da and Db, which are separated from each other, are disposed in an active region of the semiconductor substrate 500, and a common source region Cs is disposed between the first and second drain regions Da and Db. do. A first gate pattern 502a is disposed between the common source region Cs and the first drain region Da to cross the upper portion of the active region, and is active between the common source region Cs and the second drain region Db. A second gate pattern 502b crossing the upper portion of the region is disposed. The first and second gate patterns 502a and 502b may extend to serve as first and second word lines, respectively. As such, the first transistor includes a first gate pattern 502a, a common source region Cs, and a first drain region Da, and the second transistor includes a second gate pattern 502b and a common source region Cs. ) And the second drain region Db.

Subsequently, a first insulating film 503 is formed over the entire structure of the resultant product including the first and second transistors. The interlayer insulating films such as the first insulating film 503 and the subsequent second insulating film and the third insulating film are preferably made of an oxide film such as a Plasma Enhanced Eetra Ortho Silicate (PETOS) film or a Low Pressure Tetra Ethyl Ortho Silicate (LPTEOS) film.

Next, a source contact plug 504 connected to the common source region Cs in the first insulating layer 503, and first and second drain contact plugs connected to the first and second drain regions Da and Db are formed. 506a, 506b. The source contact plug 504 is electrically connected to the common source pad 505, and the first and second drain contact plugs 506a and 506b are electrically connected to the first and second drain pads 507a and 507b. .

Subsequently, after forming the second insulating film 508 on the first insulating film 503, a plurality of electrically connected to the first drain pad 507a through the second insulating film 508 in the second insulating film 508. First contact plugs 509a and a plurality of second contact plugs 509b that are electrically connected to the second drain pad 507b through the second insulating film 508. Here, the first and second contact plugs 509a and 509b constitute lower electrodes of the resistive memory element resistor, and may also be referred to as lower electrode plugs. The first and second contact plugs 509a and 509b may selectively etch the second insulating film 508 in the region where the first and second contact plugs 509a and 509b are to be formed to form a contact hole. It can be formed by embedding a conductive material in this contact hole.

As shown in FIG. 5B, on the second insulating film 508 having the first and second contact plugs 509a and 509b, the first resistance layer 510a and the first contact layer 510a connected to the first contact plug 509a are formed. The first upper electrode 511a, the second resistance layer 510b and the second upper electrode 511b connected to the second contact plug 509b are formed. The process of forming the first and second resistive layers 510a and 510b may be performed by deposition and patterning of a material (eg, a binary oxide or perovskite-based material) used as the resistive layer. The process of forming the second upper electrodes 511a and 511b may be performed by depositing and patterning a material (eg, a metal) used as the upper electrode.

As a result of the process of this figure, the 1st resistance part 50a comprised from the 1st contact plug 509a, the 1st resistance layer 510a, and the 1st upper electrode 511a, the 2nd contact plug 509b, the 1st The second resistor unit 50b including the second resistor layer 510b and the second upper electrode 511b is formed. Here, as described above, a plurality of first contact plugs 509a and second contact plugs 509b are formed.

As shown in Fig. 5C, a known subsequent process is performed. That is, the third insulating film 512 is formed on the entire structure of the resultant product including the first and second resistor parts 50a and 50b, and the third insulating film 512 penetrates into the third insulating film 512. After forming the first and second contacts 513a and 513b connected to the first and second upper electrodes 511a and 511b, respectively, the first and second contacts 513a and 513b are formed on the third insulating layer 512. Subsequently, a subsequent wiring forming process, such as forming a first metal wiring 514 to be connected to the first metal wiring 514 and forming a fourth insulating film 514 covering the first metal wiring 514, is performed.

In such a ReRAM device structure (see Fig. 5C), one end of each of the resistor portions 50a and 50b (e.g., the first and second contact plugs 509a and 509b used as the lower electrode) is provided with a first and a second one. The drain regions Da and Db of the second transistor are connected, and the other ends (eg, the first and second upper electrodes 511a and 511b) are connected to the first metal wire 514. The first and second gate patterns 502a and 502b of each transistor extend to form a word line.

Here, the common source region Cs is connected to the ground voltage, a bias voltage larger than the threshold voltage is applied to the word line, and an appropriate operating voltage is applied to the first metal wire 514, thereby reading a read operation in the resistive memory device. Or a switching operation is performed.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view for explaining a conventional resistive memory element.

2 is a cross-sectional view for explaining another conventional resistive memory element.

3A and 3B are diagrams for comparing the characteristics of the resistive memory element having the planar type bottom electrode of Fig. 1 and the resistive memory element having the plug type bottom electrode of Fig. 2;

4 is a cross-sectional view illustrating a resistive memory device according to an embodiment of the present invention.

5A to 5C are cross-sectional views illustrating a ReRAM device and a method of manufacturing the same according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

40: substrate 41: insulating film

42: a plurality of contact plugs 43: resistance layer

44: upper electrode

Claims (12)

In a resistive memory device including a plurality of unit cells, Each unit cell, A plurality of first electrode plugs penetrating the insulating film on the substrate; A resistive layer on the insulating layer and connected to the plurality of first electrode plugs; And A second electrode on the resistive layer Resistive Memory Device. The method of claim 1, The resistance layer, Composed of binary oxide or perovskite-based materials Resistive Memory Device. The method of claim 1, The plurality of first electrode plugs, Having a thickness of 80 ~ 4000Å Resistive Memory Device. The method of claim 1, The resistance layer is switched between a high resistance state or a low resistance state according to a bias applied to the plurality of first electrode plugs and the second electrode. Resistive Memory Device. The method of claim 1, A plurality of switching regions are provided in the resistive layer at portions respectively contacting the plurality of first electrode plugs. Resistive Memory Device. The method of claim 1, The resistive memory device is a ReRAM device. Resistive Memory Device. The method of claim 6, The plurality of first electrode plugs are connected to a source or drain region of a transistor of the substrate. Resistive Memory Device. Forming a plurality of first electrode plugs penetrating the insulating film; Forming a resistance layer on the insulating layer and connected to the plurality of first electrode plugs; And Forming a second electrode on the resistance layer; The plurality of first electrode plugs, the resistor layer, and the second electrode constitute a resistor unit of a unit cell. Method of manufacturing resistive memory device. The method of claim 8, The forming of the plurality of first electrode plugs may include: Selectively etching a region in which the first electrode plug of the insulating film is to be formed to form a plurality of contact holes in the insulating film; And Embedding a conductive material in the plurality of contact holes. Method of manufacturing resistive memory device. The method of claim 8, The plurality of first electrode plugs have a thickness of 80 to 4000 kPa Method of manufacturing resistive memory device. The method of claim 8, The resistance layer is made of a binary oxide or a perovskite-based material Method of manufacturing resistive memory device. The method of claim 8, The resistance layer forming step, Depositing a material forming the resistive layer on the insulating film including the plurality of first electrode plugs; And Patterning a material forming the resistive layer, wherein the patterning material covers the plurality of first electrode plugs;  Method of manufacturing resistive memory device.

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