KR101005156B1 - Delay circuit - Google Patents

Abstract

The present invention relates to a delay circuit, by controlling the current path of the input terminal of the inverter when the input signal is changed from the high level to reducing the degree of discharge of the charge accumulated in the input terminal, using a capacitor or a resistor Therefore, a delay circuit is disclosed which can sufficiently and stably delay an input signal while increasing the degree of integration, prevent noise generation while improving the reproducibility of the process, and at the same time improve the stability of the design.

Time delay, inverter, current pass, transistor, transfer gate

Description

Delay circuit             

1 is a circuit diagram illustrating a delay circuit according to a first embodiment of the present invention.

2 is a conceptual diagram illustrating a load capacitor of an inverter.

3 is a circuit diagram illustrating a delay circuit according to a second embodiment of the present invention.

4 is a circuit diagram illustrating a delay circuit according to a third embodiment of the present invention.

5 is a circuit diagram illustrating a delay circuit according to a fourth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: delay circuit 110: current path control means

The present invention relates to a delay circuit, and more particularly to a delay circuit consisting of an inverter and a transistor without a capacitor or a resistor.

In general, a CMOS inverter chain is used for short time delay circuits of more than 1 ns, but a resistor-capacitor (RC) delay circuit is used for long time delays of more than 1 ns. Use a lot. In the RC delay circuit, the resistor uses a diffusion sheet resistor applied with ion implantation, and a planar capacitor or a MOS capacitor is used as the capacitor.

Sheet resistor refers to a resistor that obtains a desired resistance value by fixing a resistance value per unit area by adjusting ion implantation concentration and dose amount and changing width and length. In general, the sheet resistance is controlled by changing the length while keeping the width constant. In the case of the fixed width, the sheet resistance should be above a certain value in consideration of the stability of the resistance value for the ion implantation process, and is usually set to 1 μm or more. .

On the other hand, the diffusion (Diffusion) resistance is affected by a variety of thermal processes throughout the entire process, the change range is large, in particular, it is very difficult to set the exact resistance value due to the severe change depending on the temperature.

In the case of capacitors, planar capacitors or multiple MOS capacitors are used. In this case, although the planar capacitor has a larger capacitance per unit area than the MOS capacitor, in both cases, a large area is required because the capacitance per unit area is very small at an absolute value.

RC delay is determined by the product of resistance and capacitance, so the delay is controlled by controlling the number of MOS capacitors rather than the variable diffusion resistor. That is, the number of MOS capacitors required for the fixed diffusion resistance value is set roughly, and additional capacitors are additionally made thereafter, and the number of MOS capacitors required for the chip F / A is checked and applied during mass production. .

However, the following problems exist in the current RC delay circuit.

First, in the case of diffusion resistors, the variation in process and temperature is so severe that it is difficult to obtain an accurate delay value, and this large delay variation fundamentally leads to a reduction in design margin.

Second, even if the chip size is increased by increasing the degree of integration, in order to obtain the same time delay, it is necessary to maintain the area of the diffusion resistor or the entire required capacitor, thereby reducing the efficiency of the chip size.

Third, in the case of the diffusion resistor, there is a problem that causes power consumption or various noises more severely than the transistor.

Fourth, inaccurate time delays can, in some cases, lead to severe development delays and degrade chip performance characteristics.

These problems are more significant in smaller size, low power, and high speed operation, which may increase future development / production costs, design difficulties, and degrade chip operation characteristics.

Accordingly, in order to solve the above problem, the present invention controls the current path of the input terminal of the inverter when the input signal is changed from the high level to the low level, thereby reducing the degree of discharge of the charge accumulated in the input terminal. The purpose of the present invention is to provide a delay circuit that can stably delay the input signal while increasing the degree of integration and prevent the occurrence of noise while ensuring the reproducibility of the process while increasing the degree of integration. .

A delay circuit according to an embodiment of the present invention is connected between a first inverter, a first node, which is an input terminal, and a second node, which is an input terminal of the first inverter, and the second node when the input signal changes from a high level to a low level. Current path control means for controlling the current path from the second node to the first node and for reducing the amount of charge discharged from the second node to delay the change of the output signal of the first inverter. Invert delay of changing input signal.

In the above, the current path control means, operating in accordance with the voltage of the second node, switching means for switching the output signal of the first inverter, and connected between the first node and the second node, and is transmitted through the switching means A signal is input to the first input terminal, and an output signal of the first inverter is directly input to the second input terminal. The switching means can be implemented with NMOS transistors.

The transfer gate consists of a PMOS transistor connected between a first node and a second node, and an NMOS transistor connected in parallel between the first node and a second node, the first input terminal being a gate terminal of the PMOS transistor and a second The input terminal is the gate terminal of the NMOS transistor.

Meanwhile, when an input signal is changed from a high level to a low level by additionally installing a second inverter at an output terminal of the first inverter, the input signal may be delayed from a high level to a low level.

In addition, by installing an additional second inverter so that the output terminal is connected to the first node, if the input signal is changed from the low level to the high level, the input signal may be delayed from the low level to the high level.

In addition, an additional second inverter is installed at the output terminal of the first inverter, and an additional third inverter is installed so that the output terminal is connected to the first node, so that when the input signal is changed from low level to high level, It is also possible to invert the input signal to a low level.

The delay level of the input signal may be controlled by the amount of charge accumulated in the gate of the transistor by the bulk voltage of the transistor in proportion to the channel width and the channel length of the transistor constituting the first inverter.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. This embodiment is provided only to make the disclosure of the present invention complete and to fully inform the person skilled in the art the scope of the present invention, the scope of the present invention should be understood by the claims of the present application.

1 is a circuit diagram illustrating a delay circuit according to a first embodiment of the present invention.

Referring to FIG. 1, a delay circuit 100 according to an embodiment of the present invention includes an inverter INV1 and a current path control means 110.

The current path control means 110 is connected between the first node N1, which is an input terminal of the delay circuit 100, and the second node N2, which is an input terminal of the inverter INV1. The current path control unit 110 controls the current path between the first node N1 and the second node N2 when the input signal IN changes from the high level to the low level, thereby removing the first path from the second node N2. The degree of discharge of charge to one node N1 is reduced. By reducing the degree of discharge, the change in the output signal of the inverter INV1 is delayed.

The current path control means 110 may be implemented by the switching means NT and the transmission gate TG. At this time, the switching means NT operates according to the voltage of the second node N2 and connects the output signal of the inverter INV1 to switch to the transmission gate TG. Such a switching means NT can be implemented with an NMOS transistor.

 The transfer gate TG may be implemented by connecting the PMOS transistor and the NMOS transistor in parallel, and are connected between the first node N1 and the second node N2. For convenience, the gate terminal of the PMOS transistor is referred to as a first input terminal of the transfer gate TG and the gate terminal of the NMOS transistor is defined as a second input terminal of the transfer gate TG for convenience. Subsequently, the signal output from the inverter INV1 is connected to the first and second input terminals. In this case, the first input terminal is connected to transmit the output signal of the inverter INV1 through the switching means NT.

Through the above configuration, the delay circuit 100 of the present invention controls the current path from the second node N2 to the first node N1 when the input signal IN changes from the high level to the low level, and the second The degree of discharge of charge from the node N2 is reduced to delay the change of the output signal of the inverter INV1. As a result, the delay circuit 100 of the present invention inverts the input signal changing from the high level to the low level.

The operation of inverting and delaying the input signal changing from the high level to the low level will be described in detail as follows.

Initial state

If the input signal IN is initially at a high level, the potential of the second node N2 is also at a high level, and the output signal of the inverter INV1 is at a low level. The switching means NT is turned on by the potential of the second node N2, and the output signal of the inverter INV1 is transmitted to the first input terminal of the transmission gate TG through the switching means NT. Meanwhile, the output signal of the inverter INV1 is also simultaneously transmitted to the second input terminal of the transmission gate TG. The NMOS transistor of the transfer gate TG is turned off by the output signal of the inverter INV1, but the PMOS transistor is turned on with Vgs becoming -Vcc.

Operation when input signal changes from high level to low level

When the input signal IN changes from the high level to the low level, the charges accumulated in the second node N2 start discharged toward the first node N1 through the PMOS transistor of the transfer gate TG in the on state. . At this time, as the input signal IN changes from a high level to a low level, the potential of the first node N1 is also lowered, and the Vgs of the PMOS transistor of the transfer gate TG is gradually increased at -Vcc. When the Vgs of the PMOS transistor rises and approaches the threshold voltage of -Vpth, the amount of current flowing through the PMOS transistor decreases rapidly, so that the amount of charge discharged to the first node N1 through the transfer gate TG increases. As it decreases, a time delay may occur until the output signal of the inverter INV1 changes.

When the potential of the second node N2 decreases and reaches the region Transition for changing the output signal even inside the inverter INV1, the output signal of the inverter INV1 rapidly changes from a low level to a high level.

As a result, when the input signal IN changes from the high level to the low level, the input signal is inverted and delayed from the low level to the high level while generating a constant time delay by the above operation.

On the other hand, while the potential of the second node N2 becomes completely low, the output signal of the inverter INV1 changes to a high level, and the switching means NT is turned off by the potential of the second node N2. Becomes For this reason, the gate of the PMOS transistor of the transfer gate TG becomes a floating state. Since the output signal of the high level inverter INV1 is applied to the second input terminal of the transfer gate TG, the NMOS transistor of the transfer gate TG is turned on. Therefore, the first node N1 and the second node N2 are continuously electrically connected through the transmission gate TG.

In the above description, the more the amount of charge accumulated in the second node N2, the longer the discharge time is. Therefore, increasing the amount of charge accumulated in the second node N2 may further delay the input signal IN. have. In this case, the amount of charge accumulated in the second node N2 when the input signal IN is at a high level depends on the load capacitor of the inverter INV1. The load capacitor of the inverter will be described with reference to FIG. 2 as follows.

2 is a conceptual diagram illustrating a load capacitor of an inverter.

Referring to FIG. 2, the inverter includes a PMOS transistor Tp and an NMOS transistor Tn connected in series between a power supply voltage terminal Vcc and a ground voltage terminal Vss, and the PMOS transistor Tp and the NMOS transistor. Respective bulk voltages Vbp and Vbn are applied to the bulk of (Tn). Meanwhile, a gate oxide film is formed between the gate terminal of the PMOS transistor Tp and the NMOS transistor Tn and the substrate. The gate oxide film serves as a dielectric film of the capacitor, and the bulk voltage and gate applied to the substrate on which the transistor is formed. Electric charges are accumulated in the gate electrode by the voltage applied to the terminal. As a result, the transistor operates in a capacitor, which is called a transistor capacitor. The 'load capacitor of the inverter' described above is such a transistor capacitor. The capacitance of these transistor capacitors is determined by the width and length of the gate terminal. As the width and length of the gate terminal increase, the area of the gate terminal increases, thereby increasing capacitance.

As a result, when the length and width of the gate terminal of the transistor constituting the inverter INV1 are increased in FIG. 1, the amount of charge accumulated in the second node N2 may be increased to further delay the input signal IN.

Operation when input signal changes from low level to high level

If the input signal IN is initially at the low level, the potential of the second node N2 is also at the low level, and the output signal of the inverter INV1 is at the high level. The switching means NT is turned off by the potential of the second node N2, and the gate of the PMOS transistor of the transfer gate TG is in a floating state. The output signal of the inverter INV1 is applied to the NMOS transistor of the transfer gate TG so that the NMOS transistor is turned on. As a result, the first node N1 and the second node N2 are electrically connected to each other.

In this state, when the input signal IN starts to change from the low level to the high level, the potential of the second node N2 also starts to rise. At this time, the inverter INV1 maintains the output signal of the high level until it reaches the region Transition for changing the output signal in the inverter INV1. Therefore, since the NMOS transistor of the transfer gate TG remains on by the output signal of the inverter INV1, the potential of the second node N2 increases without time delay according to the input signal IN.                     

When the input signal IN continues to increase and the potential of the second node N2 continues to increase equally, and reaches a high level, the inverter INV1 reaches an area where the output signal changes within the inverter INV1. Generate a low-level output signal with no time delay.
The rising edge of the input signal is reversed without delay, and the falling edge is reversed with a relatively delay.
When the state of the N2 node is high level, only the PMOS transistor of the transfer gate is turned on. That is, when the state of the N2 node is high level, the PMOS transistor of the transfer gate is turned on by the low level signal of the inverter INV1 transferred through the NMOS transistor NT, and the NMOS transistor of the transfer gate is the inverter INV1. It is turned off by the low level signal of. Therefore, when the input signal IN transitions to the low level (that is, when the N2 node falls from the high level to the low level), the charge of the N2 node is discharged only through the PMOS transistor of the transfer gate that is turned on. Lowers.
However, when the N2 node is low level, both the NMOS transistor and the PMOS transistor of the transfer gate are turned on. That is, when the N2 node is low level, the NMOS transistor of the transfer gate is naturally turned on by the high level signal of the inverter INV1. On the other hand, since the NMOS transistor NT is turned off in accordance with the potential of the N2 node, the gate of the PMOS transistor of the transfer gate is in a floating state by the NMOS transistor NT in a low level state. Therefore, even when the inverter INV1 outputs a high level signal, the NMOS transistor NT in the turn-off state maintains at least a weakly turned on state regardless of the output signal of the inverter INV1. The reason for this is described in more detail as follows.
When the N2 node is at the low level, the NMOS transistor NT is turned off, and the gate of the PMOS transistor of the transfer gate is in a floating state. However, when the N2 node was at the high level, the gate of the PMOS transistor of the transfer gate was low level due to the low level signal of the inverter INV1 applied through the NMOS transistor NT. In this state, when the N2 node goes low, the NMOS transistor NT is turned off and the gate of the PMOS transistor of the transfer gate is in a floating state. When a low level signal is applied to the gate of the PMOS transistor of the transfer gate and the gate of the PMOS transistor of the transfer gate floats, the gate of the PMOS transistor of the transfer gate remains low even in the floated state. This phenomenon is accepted as a phenomenon apparent to those skilled in the art.
Therefore, even if the inverter INV1 outputs a high level signal while the N2 node is at the low level, the gate of the PMOS transistor of the transfer gate is floating at the low level, regardless of the level of the output signal of the inverter INV1. Will remain turned on. For this reason, when the N2 node is at the low level, both the NMOS transistor and the PMOS transistor of the transfer gate are turned on.
However, if the inverter INV1 first outputs a high level signal before the NMOS transistor NT is turned off, the PMOS transistor of the transfer gate may be turned off. However, in order for the inverter INV1 to output a high level signal, the NMOS transistor included in the inverter INV1 must also be turned off before the NMOS transistor NT is turned off. Typically, since the NMOS transistors have the same threshold voltages unless they are divided into a high voltage device and a low voltage device, the NMOS transistor of the inverter INV1 cannot be turned off before the NMOS transistor NT is turned off, which is obvious to those skilled in the art. One is true. Therefore, it is also apparent to those skilled in the art that the high level signal of the inverter INV1 is difficult to transfer to the gate of the PMOS transistor of the transfer gate, and even if transferred, it is not sufficient to turn off the PMOS transistor of the transfer gate.
In summary, the PMOS transistor of the transfer gate is always turned on regardless of the voltage level of the N2 node (or the output signal level of the inverter INV1). Only the NMOS transistor of the transfer gate is turned on or off depending on the voltage level of the N2 node (or the output signal level of the inverter INV1).
Therefore, at the rising edge where the input signal IN changes from the low level to the high level, since the positive charge is transferred to the second node N2 through both the NMOS transistor and the PMOS transistor of the transfer gate, the second node N2 The potential of is rapidly increased so that the output signal of the inverter INV1 quickly changes from high level to low level.
However, at the falling edge at which the input signal IN changes from the high level to the low level, since the positive charge of the second node N2 moves only through the PMOS transistor of the transfer gate, the potential of the second node N2 is relatively low. Slowly lower, the output signal of the inverter INV1 changes from low level to high level relatively slowly.
Thus, assuming that the output signal OUT is inverted and output without a time delay when the input signal IN changes from the low level to the high level, the output signal when the input signal IN changes from the high level to the low level. Since (OUT) slowly changes from low level to high level, there is a relative time delay.

As a result, when the input signal IN changes from the low level to the high level, the input signal is inverted from the high level to the low level without being delayed and output.

On the other hand, the NMOS transistor of the transfer gate TG is turned off by the output signal of the inverter INV1, but the switching means NT is turned on by the potential of the second node N2 which is at a high level. Through the means NT, the low level signal of the inverter INV1 is applied to the PMOS transistor of the transfer gate TG so that the first node N1 and the second node N2 are electrically connected continuously.

Looking at the above, when the input signal is changed from the low level to the high level, the delay circuit according to an embodiment of the present invention outputs by inverting the input signal without time delay. However, only when the input signal changes from the high level to the low level, the input signal is delayed and outputted.

On the other hand, if the inverter is selectively added to the input terminal or the output terminal of the delay circuit described with reference to FIG. Only when the input signal is delayed and output, or when the input signal is changed from the low level to the high level, the input signal may be delayed and outputted.                     

3 is a circuit diagram illustrating a delay circuit according to a second embodiment of the present invention.

Referring to FIG. 3, when the second inverter INV2 is additionally installed at the output terminal of the delay circuit 100 illustrated in FIG. 1, the input signal is input from the high level to the low level only when the input signal is changed from the high level to the low level. You can delay the signal as it is. In the case of a pulse, the width of the pulse can be increased by delaying the falling edge.

4 is a circuit diagram illustrating a delay circuit according to a third embodiment of the present invention.

Referring to FIG. 4, when the second inverter INV2 is additionally installed at the input terminal of the delay circuit 100 illustrated in FIG. 1, the input signal is input from the low level to the high level only when the input signal is changed from the low level to the high level. You can delay the signal as it is. In addition, in the case of a pulse, the width of the pulse can be reduced by delaying a rising edge portion.

5 is a circuit diagram illustrating a delay circuit according to a fourth embodiment of the present invention.

Referring to FIG. 5, when the second inverter INV2 is additionally installed at the input terminal of the delay circuit 100 shown in FIG. 1 and the third inverter INV3 is additionally installed at the output terminal, the input signal is at a low level. Only when changing to the high level can the inversion delay of the input signal from a high level to a low level.

As described above, since the present invention delays an input signal without using a diffusion resistor, an accurate delay value can be obtained, and power consumption can be reduced and various noises can be prevented. In addition, the MOS capacitor used can be significantly reduced, thereby minimizing the area and reducing the size to the same level when reducing the chip size, thereby preventing the efficiency of the chip size from being reduced.

In addition, since the delay circuit proposed in the present invention can be used simply by making various types of pulses from one basic pulse, it is possible to replace the complicated circuits necessary to make various pulse circuits.

Claims (8)

A first inverter, Connected between a first node, which is an input terminal, and a second node, which is an input terminal of the first inverter, and charges from the second node to the first node according to a voltage of the second node and an output signal of the first inverter; Current path control means for delaying the change of the output signal of the first inverter by reducing the degree of discharge; A delay circuit that inverts and delays an input signal that changes from high level to low level. A first inverter, Switching means operating according to a voltage of a second node which is an input terminal of the first inverter, and switching an output signal of the first inverter; And A transmission gate connected between a first node, which is an input terminal, and the second node, and a signal transmitted through the switching means is input to a first input terminal, and an output signal of the first inverter is directly input to a second input terminal. Include, When the input signal input to the input terminal is changed from the high level to the low level, the current path from the second node to the first node is controlled, and the degree of discharge of charge from the second node is reduced, thereby increasing the high level. A delay circuit that inverts and delays an input signal that changes from low to low. The method of claim 2, And the switching means is an NMOS transistor. The method of claim 2, The transfer gate includes a PMOS transistor connected between the first node and the second node, and an NMOS transistor connected in parallel between the first node and the second node, and the first input terminal of the PMOS transistor. And a second input terminal is a gate terminal of the NMOS transistor. The method of claim 1, And a second inverter is further provided at an output terminal of the first inverter to delay the input signal when the input signal changes from a high level to a low level. The method according to claim 1 or 2, And a second inverter is further provided such that an output terminal is connected to the first node to delay an input signal changing from a low level to a high level. The method according to claim 1 or 2, A second inverter is additionally installed at an output terminal of the first inverter, and a third inverter is additionally installed such that an output terminal is connected to the first node, thereby delaying an input signal changing from a low level to a high level. Delay circuit. The method according to claim 1 or 2, The delay level of the input signal is controlled by the amount of charge accumulated in the gate of the transistor by the bulk voltage of the transistor in proportion to the channel width and the channel length of the transistor constituting the first inverter. .

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