KR101004549B1 - Method of fabricating semiconductor apparatus - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device that secures a process margin for forming a fin transistor when forming a unit cell in a highly integrated semiconductor device on a partially insulating substrate. A method of manufacturing a semiconductor device according to the present invention includes forming a partially insulated substrate including a silicon connection region having a width greater than that of a fin transistor of an upper silicon layer and a lower semiconductor substrate, and forming the fin region on the partially insulated substrate. Forming a transistor comprising;

Partially Insulated Boards, Pin Transistors

Description

Manufacturing method of semiconductor device {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a semiconductor device having a partially insulated field effect transistor and a method for manufacturing the same.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device, for example, a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the requesting device.

As the data storage capacity of the semiconductor memory device increases, the size of a plurality of unit cells becomes smaller and smaller, and the size of various components for read or write operations decreases. Therefore, it is important to minimize the area occupied by each element by integrating any unnecessary wiring or transistors inside the semiconductor memory device. In addition, reducing the size of the plurality of unit cells included in the semiconductor memory device also greatly increases the degree of integration.

As semiconductor devices become highly integrated, bulk silicon is reduced in size to field effect transistors (FETs), with short channel effects and leakage as is well known to those skilled in the art. Problems such as increase of a leakage current occur.

In order to overcome the aforementioned problems, a method of manufacturing a semiconductor device for implementing a transistor on a substrate having a silicon on insulator (SOI) structure has been proposed. Here, the SOI substrate includes an insulating film formed on the lower semiconductor substrate and a silicon film formed on the insulating film. When implementing the floating body transistor on the SOI substrate, the body of the transistor is formed on the silicon film formed on the insulating film, and the isolation current between the adjacent transistor body is completely isolated through the device isolation film in contact with the insulating film to reduce the leakage current. In addition, the source and drain regions are formed by using both sides of the three-dimensional structure of the transistor body, thereby increasing the channel length than the conventional two-dimensional planar structure.

However, when a transistor is implemented on a substrate having an SOI structure, a floating body effect occurs. In the substrate of the SOI structure, since the insulating film exists between the semiconductor substrate and the silicon film, the substrate itself of the SOI structure has the structure of a capacitor. Therefore, when charge repeatedly moves through the body of the transistor, charge is accumulated in the above-described capacitor through a process of bias and carrier generation and recombination, and consequently adversely affects the operation of the semiconductor device. This is because the threshold voltage of the transistor fluctuates due to the charge accumulated in the capacitor, and thermal energy is generated by repeating the process of accumulating and releasing the charge. The occurrence of leakage current due to electric field concentration is also referred to as Kink effect.

In order to prevent the operating characteristics of the semiconductor device from deteriorating due to the structural characteristics of the SOI substrate, a part of partially insulating the upper and lower portions of the SOI substrate by partially connecting the silicon film to the upper portion of the insulating film and the semiconductor substrate constituting the lower portion of the SOI substrate. Partially Insulated (PI) substrate structures have been proposed. Hereinafter, a method of manufacturing a semiconductor device on a partially insulating (PI) substrate will be described.

1A and 1B are plan views illustrating the structure of a mask for manufacturing a conventional semiconductor memory device. Specifically, FIG. 1A illustrates an ISO mask 102 for manufacturing a unit cell having a size of 8F ² including a fin transistor, a silicon connection mask 104 and a fin mask 106 defined by the same line widths, and a gate. 1B shows an ISO mask 112 for manufacturing a unit cell having a size of 6F ² , a silicon connection mask 114 and a fin mask 116 defined by the same line widths, and a gate. The mask 118 is shown.

Hereinafter, a method of implementing a pin transistor on a partially insulated (PI) substrate using a mask shown in FIGS. 1A and 1B will be described.

2A to 2H are perspective views illustrating a method of manufacturing a conventional semiconductor device using the mask pattern shown in FIG. 1A.

Referring to FIG. 2A, a sacrificial layer 204 is formed on a semiconductor (eg, Si or SiGe) substrate 202, and a first silicon layer 206 is formed on the sacrificial layer 204. A first hard mask film (not shown) is formed on the first silicon film 206. In this case, the sacrificial layer 204 is formed of a material having a selectivity different from that of the semiconductor substrate 202 and the first silicon layer 206 during wet etching. After applying the first photoresist film (not shown) on the first hard mask film, the photoresist film is patterned using the silicon connection mask 104 shown in FIG. 1A. The first hard mask layer is etched using the patterned second photoresist layer, and the first silicon layer 206 and the sacrificial layer 204 are etched as shown in FIG. 2B. Thereafter, the remaining first photoresist film and the first hard mask film are removed.

Referring to FIG. 2C, a second silicon layer 208 is formed on a structure including a patterned first silicon layer 206 and a sacrificial layer 204 to form a silicon connection portion in a partially insulated (PI) substrate structure. Complete

Referring to FIG. 2D, after forming the second hard mask layer 210 on the second silicon layer 208, an STI process of forming a trench through etching using an ISO mask defining an active region is performed. Thereafter, as shown in FIG. 2E, the exposed sacrificial layer 204 is selectively wet-etched. As an example of this selective wet etching, when the sacrificial film 204 is composed of Si _x Ge _1-x (x is 0.8), HNO ₃ (70 wt%): HF (49 wt%): CH ₃ COOH ( 99.9% by weight): H ₂ O = 40: 1: 2: 57 A mixed solution having a composition ratio of water (H ₂ 0) diluted to an appropriate concentration in the semiconductor substrate 202, the first using an etching solution The sacrificial layer 204 may be selectively wet etched except for the silicon layer 206 and the second silicon layer 208.

Referring to FIG. 2F, an empty space formed through trenches and selective wet etching formed through the STI process is filled with an insulating insulating film 212 to complete a partially insulating (PI) substrate structure. Subsequently, the planarization process may be performed by chemical mechanical polishing (CMP) to planarize the second hard mask film 210. The isolation insulating film 212 is etched by a predetermined depth through a wet etching process to adjust the height, and the exposed second hard mask film 210 is removed to expose the upper portion of the second silicon film 208 defined as the active region. do. In order to form the fin region, a third hard mask film (not shown) is deposited on the entire surface including the upper portion of the second silicon film 208 and then the second photoresist film (not shown) is formed on the third hard mask film (not shown). (Not shown). Afterwards, a trench is formed using the fin mask 106 to remove the second photoresist layer in the region where the fin region of the transistor is to be formed, and then removes the exposed third hard mask layer and the isolation insulating layer 212 to form the fin channel region. 209 is formed. After the formation of the fin channel region through the above-described process, the remaining second photoresist layer and the third hard mask layer are removed.

Referring to FIG. 2G, a gate insulating film (not shown) is formed on the first and second silicon films 206 and 208 and the semiconductor substrate 202 exposed through the trench 209, and the structure includes the gate insulating film. The gate lower electrode 216 and the gate upper electrode 218 are formed on the substrate. In this case, the trench 209 is filled with the gate lower electrode 216. Thereafter, a gate hard mask layer 220 is deposited on the gate upper electrode 218.

After the third photoresist layer (not shown) is coated on the gate hard mask layer 220, the gate hard mask layer 220 is patterned using a gate mask. Using the patterned third photoresist layer, as illustrated in FIG. 2H, the gate hard mask layer 220, the gate upper electrode 218, and the gate lower electrode 216 are sequentially etched. When the gate pattern is completed, the remaining third photoresist layer is removed.

Subsequently, the LDD region of the cell transistor is formed and the sidewall insulating film is formed on the sidewall of the gate pattern in the same manner as the process of manufacturing a unit cell of a conventional DRAM. Subsequently, a cell transistor formation process such as forming a cell contact plug, forming a bit line contact (BL contact) and a bit line (BL), forming a capacitor contact and a capacitor, and forming a metal wiring Through this process, a unit cell manufacturing process of a DRAM including a pin transistor is completed.

3 is a perspective view illustrating a problem of a conventional semiconductor device manufactured through FIGS. 2A to 2H. In particular, FIG. 3 shows a cross section of the perspective view shown in FIG. 2F.

As shown in the drawing, the cross section of the fin region after the isolation insulating film 212 is formed is a portion between the semiconductor substrate 202 and the first and second silicon films 206 and 208 is insulated through the isolation insulating film 212. It can be seen that. As described above with reference to FIG. 2B, the partially insulating substrate may include the sacrificial layer 204 except for the portions where the sacrificial layer 204 and the first silicon layer 206 are etched using the silicon connection mask defined by the same line width as the fin mask. The remaining portion is selectively removed by wet etching after the formation of the second silicon film 208 and filled with an insulating insulating film. In the process of FIG. 2F, a fin region is formed only in an uninsulated region between the semiconductor substrate 202 and the first and second silicon films 206 and 208 by using a fin mask defined with the same line width as the silicon connection mask. The width of the fin region and the width of the silicon connection portion of the partially insulating substrate become equal to each other.

Therefore, in the above-described conventional fin cell transistor, if an alignment error occurs between the silicon connection mask and the fin mask, the connection portion between the fin region and the silicon substrate of the fin channel is not exactly matched, and the fin region is partially shifted to the partially insulating region. Can be formed. A typical DRAM structure has a junction region connected to a bit line between two cell transistors formed on one active region, and a junction region connected to a storage node at both ends of the two cell transistors. If an alignment error occurs when the fin cell transistor is applied to the DRAM structure, the alignment error causes two pin cell transistors formed on one active region to have an asymmetric structure rather than symmetry. As a result, the operation characteristics between the source and the drain of the two pin cell transistors are changed, thereby causing a problem that the characteristics of the cell transistors connected to both sides of one bit line are different.

In addition, even when no alignment error occurs, since the fin region and the silicon connection region are almost the same, the saddle-type fin transistor formed by etching the insulating insulating layer deeper than the depth of the silicon film where the channel is formed is intended to be implemented in the partially insulating substrate. In this case, the depth of the channel should be smaller than the sum of the thicknesses of the first and second silicon films 206 and 208. If the depth of the channel is designed to be larger than the sum of the thicknesses of the first and second silicon films 206 and 208, the etched channel and the partial insulation region meet so that the source / drain of the transistor is separated by the partial insulating film. As a result, it cannot operate as a transistor. As a result, the process margin is insufficient when the pin transistor is implemented on the partially insulated substrate by the conventional method, and in particular, when the saddle-type pin cell transistor is implemented, the channel depth of the transistor is limited, which causes the saddle-type pin. There is a problem in that an operation characteristic of the cell transistor is generated.

In order to solve the above-mentioned conventional problems, the present invention can improve the process margin for alignment error occurring during the formation of the pin transistor when forming the unit cell in the highly integrated semiconductor device on the partially insulated substrate, in particular, saddle fin Provided is a method of manufacturing a semiconductor device capable of removing constraints on channel depth during fabrication of a transistor.

The present invention provides a method of forming a partially insulated substrate including a silicon connection region having an upper silicon layer and a lower semiconductor substrate having a width wider than that of a fin transistor, and forming a transistor including the fin region on the partially insulated substrate. It provides a method for manufacturing a semiconductor device comprising the step.

The forming of the partially insulating substrate may include forming a sacrificial layer on the lower semiconductor substrate, forming a first silicon layer on the sacrificial layer, and etching the first silicon layer and the sacrificial layer to form the sacrificial layer. Determining a silicon connection region, and forming a second silicon film on the first silicon film and the lower semiconductor substrate.

Preferably, the etching of the first silicon layer and the sacrificial layer to determine a silicon connection region comprises depositing a first hard mask layer on the first silicon layer, and applying a photoresist layer on the first hard mask layer. Patterning the photoresist layer using a silicon connection mask, etching the first hard mask layer using the patterned photoresist layer, and using the etched first hard mask layer to form the first silicon layer and the sacrificial layer. Etching, and removing the remaining photoresist film and the first hard mask film.

Preferably, the etching of the first silicon layer and the sacrificial layer to determine the silicon connection region further includes wet etching the side surfaces of the exposed sacrificial layer after etching the sacrificial layer.

Preferably, the region exposed by the silicon connection mask is the same as the region exposed by the fin mask for forming the fin region.

Preferably, the sacrificial film is composed of Si _x Ge _1-x (x is 0.8), and the wet etching is HNO 3 (70 wt%): HF (49 wt%): CH 3 COOH (99.9 wt%): H 2 O = 40: It is characterized by using a mixed solution having a composition ratio of 1: 2: 57 in water (H ₂ O) as an etching solution.

Preferably, the region exposed by the silicon connection mask is in a wider range including the region exposed by the fin mask to form the fin region.

Preferably, the silicon connection mask defines an exposed area in the form of a line.

Preferably, the silicon connection mask is characterized in that it defines a plurality of rectangular exposed areas isolated from each other.

Preferably, the silicon connection mask is characterized in that it exposes between two adjacent fin areas intersecting the active area.

Preferably, the silicon connection mask exposes a wider range of area than the fin mask only in an area crossing the active area.

Preferably, the forming of the transistor comprises forming a trench using an ISO mask defining an active region, wet etching a sacrificial layer exposed by the trench to form a partially insulating region, the trench and the Forming an insulating insulating film in a partial insulating region, etching the insulating insulating film using a fin mask, forming a gate oxide film on the exposed active region, and forming a gate electrode on the gate oxide film. Include.

Preferably, the sacrificial layer has a different etching selectivity from that of the upper silicon layer and the lower semiconductor substrate.

The forming of the trench may include forming a second hard mask layer on the partially insulating substrate, applying a photoresist layer and patterning the ISO mask, and etching the second hard mask layer using the patterned photoresist layer. And etching the upper silicon layer and the lower semiconductor substrate using the etched second hard mask layer.

According to the present invention, a channel of a saddle fin transistor designed in a semiconductor device due to the partial insulation region is formed by forming a width of a channel portion connected to the silicon substrate between the partial insulation regions included in the partial insulation substrate to be larger than the width defined in the mask. The advantage is that the depth is not limited.

In addition, even in the case of a fin transistor, even if an alignment error occurs to some extent due to a connection portion with a silicon substrate having a wider width than the fin region, the fin channel portion can be prevented from being formed on the partial insulating film, so that the alignment error can be prevented. The asymmetry of the channel characteristics between the source and the drain can be reduced, and the asymmetry of the operating characteristics between two adjacent pin cell transistors can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4B are plan views illustrating a structure of a mask for manufacturing a semiconductor memory device according to an embodiment of the present invention. Specifically, FIG. 4A illustrates an ISO mask 402 for fabricating a unit cell having a size of 8F ² including a fin transistor, a silicon connection mask 404 and a fin mask 406 defined as the same regions, and a gate. The mask 408 will be described. Here, the silicon connection region 404_1 is shown between the partial insulation regions in the partial insulation substrate. After etching the sacrificial layer through a photolithography process using the silicon connection mask 404, the side surface of the sacrificial layer is etched again through wet etching. It widens by

4B illustrates an ISO mask 412 for forming a unit cell having a size of 6F ² , a silicon connection mask 414 and a fin mask 416 defined by the same region, and a gate mask 418. . As shown in FIG. 4A, the silicon connection region 414_1 is shown between the partial insulation regions in the partially insulated substrate, and the side surface of the sacrificial layer is etched through wet etching after the sacrificial layer is etched through the photolithography process using the silicon connection mask 414. Widen by etching again.

Referring to FIG. 1A, a process of forming a fin cell transistor using a silicon connection mask 104 and a fin mask 106 having a linear shape has been described in the related art. However, in the exemplary embodiment of the present invention, a silicon connection having a rectangular shape is illustrated. A process of forming the fin cell transistor using the mask 404 and the fin mask 406 will be described. However, the shape of the silicon connection mask 404 and the fin mask 406 may vary depending on the embodiment, and it is important that the two masks define the same area.

Conventionally, due to the silicon connection mask 104 and the fin mask 106 defining the same area, an area connecting the lower semiconductor substrate and the upper silicon film in the partial insulation substrate formed by using the silicon connection mask 104. The problem arises when the width of the fin and the width of the fin region formed using the fin mask 106 are equally defined and an alignment error occurs. However, in an embodiment of the present invention, even when the silicon connection mask 404 and the fin mask 406 defining the same region are used, the width of the region connecting the lower semiconductor substrate and the upper silicon layer is larger than the width of the fin region. By forming, it is possible to improve the problems of the prior art.

Hereinafter, as shown in FIGS. 4A and 4B, a saddle-type fin transistor including a fin region is formed on a partially insulated substrate using a silicon connection mask 404 and a fin mask 406 defined as the same regions as each other. A manufacturing method of a semiconductor device will be described in detail.

5A to 5H are perspective views illustrating a method of manufacturing a semiconductor device using the mask pattern shown in FIG. 3A.

Referring to FIG. 5A, a sacrificial layer 504 is formed on a semiconductor (eg, Si or SiGe) substrate 502, and a first silicon layer 506 is formed on the sacrificial layer 504. A first hard mask film (not shown) is formed on the first silicon film 506. In this case, the sacrificial layer 504 is a material having a different selectivity during wet etching from the semiconductor substrate 502 and the first silicon layer 506, and is substantially larger than the lattice constant of the semiconductor substrate 502 and the first silicon layer 506. It is composed of materials with lattice constant values that do not differ.

After applying the first photoresist film (not shown) on the first hard mask film, a silicon connection mask 404 or 414 defined by the same area as the fin mask 406 or 416 shown in FIG. 4A or 4B is used. To pattern the photoresist. The first hard mask layer is etched using the patterned second photoresist layer, and as illustrated in FIG. 5B, the first silicon layer 506 and the sacrificial layer 504 are etched and the remaining photoresist layer is removed. Then, unlike the prior art, in one embodiment of the present invention selectively etching a predetermined amount of the side surface of the sacrificial film 504 exposed through a wet etching process. As an example of this selective wet etching, when the sacrificial film 504 is composed of Si _x Ge _1-x (x is 0.8), HNO ₃ (70 wt%): HF (49 wt%): CH ₃ COOH ( 99.9% by weight): H ₂ O = 40: 1: 2: 57 A mixed solution having a constituent ratio of (dilution) in water (H ₂ 0) to an appropriate concentration was used as an etching solution, the semiconductor substrate 502 and the Only the sacrificial film 504 except the one silicon film 506 is selectively etched. Thereafter, the remaining first hard mask film is removed.

Referring to FIG. 5C, a second silicon layer 508 is formed on the structure including the patterned first silicon layer 506 and the sacrificial layer 504. In this case, the second silicon film 508 may be formed using a silicon connection mask and a region formed by wet etching a predetermined amount of the sacrificial film 504 between the semiconductor substrate 502 and the first silicon film 506. The sacrificial layer 504 is etched to completely fill the formed region.

Referring to FIG. 5D, after forming the second hard mask layer 510 on the second silicon layer 208, an STI process of forming a trench through etching using an ISO mask defining an active region is performed. Thereafter, as shown in FIG. 5E, the exposed sacrificial layer 504 is selectively wet-etched. As an example of this selective wet etching, when the sacrificial film 504 is composed of Si _x Ge _1-x (x is 0.8), HNO ₃ (70 wt%): HF (49 wt%): CH ₃ COOH ( 99.9 _{wt.%): H 2 O = 40} : 1: 2: a semiconductor substrate (502, using the etching solution is diluted with a mixed solution having a composition ratio of 57 at appropriate concentrations in the water (H ₂ 0)), first The sacrificial layer 504 may be selectively wet etched except for the silicon layer 506 and the second silicon layer 508.

Referring to FIG. 5F, an empty space formed through trenches and selective wet etching formed through the STI process is filled with the insulating insulating layer 512. Subsequently, the planarization process is performed through chemical mechanical polishing (CMP) to planarize the second hard mask layer 510. The isolation insulating layer 512 is etched by a predetermined depth through a wet etching process to adjust the height, and the exposed second hard mask layer 510 is removed to expose the upper portion of the second silicon layer 508 defined as the active region. do. In order to form the fin region, a third hard mask film (not shown) is deposited on the entire surface including the upper portion of the second silicon film 508, and a second photoresist film (not shown) is formed on the third hard mask film (not shown). (Not shown). Thereafter, the second photoresist layer is removed in the region where the fin region of the transistor is to be formed using the fin mask 506, and then the exposed third hard mask layer, the second silicon layer 508, and the isolation insulating layer 512 are removed. As a result, a trench 509 is formed to form a channel region of the saddle-type fin cell transistor. After the formation of the fin channel region through the above-described process, the remaining second photoresist layer and the third hard mask layer are removed.

Referring to FIG. 5G, a gate insulating film (not shown) is formed on the first and second silicon films 506 and 508 and the semiconductor substrate 502 and the second silicon film 508 exposed by the trench 509. The gate lower electrode 516 and the gate upper electrode 518 are formed on the structure including the gate insulating layer. In this case, the trench 509 is filled by the gate lower electrode 516 or by the gate lower electrode 516 and the gate upper electrode 518. Thereafter, a gate hard mask layer 520 is deposited on the gate upper electrode 518.

After the third photoresist layer (not shown) is coated on the gate hard mask layer 520, the gate hard mask layer 520 is patterned using a gate mask. Using the patterned third photoresist layer, as illustrated in FIG. 5H, the gate hard mask layer 520, the gate upper electrode 518, and the gate lower electrode 516 are sequentially etched. When the gate pattern is completed, the remaining third photoresist layer is removed.

Subsequently, the LDD region of the cell transistor is formed and the sidewall insulating film is formed on the sidewall of the gate pattern in the same manner as the process of manufacturing a unit cell of a conventional DRAM. Subsequently, a cell transistor formation process such as forming a cell contact plug, forming a bit line contact (BL contact) and a bit line (BL), forming a capacitor contact and a capacitor, and forming a metal wiring Through this process, a unit cell manufacturing process of a DRAM including a pin transistor is completed.

FIG. 6 is a perspective view illustrating characteristics of a semiconductor device manufactured through FIGS. 5A to 5H. In particular, FIG. 6 shows a cross section of the perspective view shown in FIG. 5F.

As shown in the drawing, the cross section of the fin region after the isolation insulating film 512 is formed is a portion between the semiconductor substrate 502 and the first and second silicon films 506 and 508 is insulated through the isolation insulating film 512. It can be seen that. In the present invention, the silicon connection region between the insulating insulating layer 512 for the partial insulation wets the side surface of the sacrificial layer 504 exposed after etching the sacrificial layer 504 using the silicon connection mask as described in FIG. 5B. It was formed by sir. In this case, the portion of the insulating insulating film 512 for partial insulation is a portion in which the sacrificial layer 504 is not etched.

Therefore, the width of the partial insulation region in the present invention is reduced compared to the prior art, and as a result, the spacing between the fin region and the partial insulation region is more sufficiently isolated than the prior art.

As a result, when the fin transistor is manufactured according to the manufacturing method of the present invention, the height of the fin region included in the pin transistor designed in the semiconductor device is not limited due to the partially insulating region included in the partially insulating substrate. That is, even if the channel depth of the saddle-type fin transistor is formed deeper than the sum of the thicknesses of the first and second silicon films 506 and 508, the partial insulation region and the fin region are completely isolated, so that bit lines are formed on both sides of the transistor. Since the junction region and the storage node junction region are connected without disconnection by the partial insulation region, the transistor operates normally. In addition, in the case of fabricating a fin cell transistor, even if an alignment error of less than a degree of isolation between the fin region and the partial insulation region occurs, the bit channel region of the bit line is not located in the partial insulation region. The operating characteristics of two neighboring cell transistors located at both sides can be similarly maintained.

7A to 7H are plan views illustrating the structure of a mask for manufacturing a semiconductor memory device according to another embodiment of the present invention.

7A to 7D illustrate a silicon connection mask, an ISO mask, a fin mask, and a gate mask for manufacturing a unit cell having a size of 8F ² to replace the masks shown in FIG. 4A, and FIGS. 7E to 7H are shown in FIG. A silicon connection mask, an ISO mask, a fin mask, and a gate mask for manufacturing a unit cell having a size of 6F ² to replace the masks shown in 4b are described.

All of the silicon connection masks 704A-704D and 714A-714D shown in Figs. 7A-7H are characterized by exposing a wider range of width at the portion overlapping with the area exposed by the r fin mask. The silicon connection mask may define an exposed area in the form of a line as shown in FIGS. 7C and 7G, and may define a plurality of rectangular exposed areas isolated from each other as shown in FIGS. 7A, 7B, 7E, and 7F. have. In particular, the silicon connection mask shown in FIGS. 7B and 7F is characterized by exposing between two adjacent fin regions intersecting with the active region.

7D and 7H, the silicon connection mask may expose a wider area than the fin mask only in an area intersecting with the active area, and may expose the same area as the fin mask in other areas.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A and 1B are plan views illustrating the structure of a mask for manufacturing a conventional semiconductor memory device.

2A to 2H are perspective views for explaining a method of manufacturing a conventional semiconductor device using the mask pattern shown in FIG. 1A.

3 is a perspective view illustrating a problem of a conventional semiconductor device manufactured through FIGS. 2A to 2H.

4A to 4B are plan views illustrating the structure of a mask for manufacturing a semiconductor memory device according to one embodiment of the present invention;

5A to 5H are perspective views illustrating a method of manufacturing a semiconductor device using the mask pattern shown in FIG. 3A.

FIG. 6 is a perspective view illustrating characteristics of a semiconductor device manufactured through FIGS. 5A to 5H.

7A to 7H are plan views illustrating the structure of a mask for manufacturing a semiconductor memory device according to another embodiment of the present invention.

Claims (15)

delete Forming a partially insulating substrate including an upper silicon layer and a lower semiconductor substrate including a silicon connection region having a width wider than a fin region of a fin transistor; And Forming a transistor including the fin region on the partially insulating substrate Including, Forming the partially insulating substrate Forming a sacrificial layer on the lower semiconductor substrate; Forming a first silicon film on the sacrificial film; Etching the first silicon layer and the sacrificial layer to determine the silicon connection region; And Forming a second silicon film on the first silicon film and the lower semiconductor substrate. The method of claim 2, Determining the silicon connection region by etching the first silicon layer and the sacrificial layer Depositing a first hard mask film on the first silicon film; Applying a photosensitive film on the first hard mask film; Patterning the photoresist using a silicon connection mask; Etching the first hard mask layer using the patterned photoresist; Etching the first silicon layer and the sacrificial layer by using an etched first hard mask layer; And Removing the remaining first hard mask film. The method of claim 3, And etching the first silicon layer and the sacrificial layer to determine a silicon connection region, further comprising wet etching side surfaces of the exposed sacrificial layer after etching the sacrificial layer. The method of claim 4, wherein And a region exposed by the silicon connection mask is the same as a region exposed by a fin mask for forming the fin region. The method of claim 5, The sacrificial film was composed of Si _x Ge _1-x (where 0 ≦ x <1), and the wet etching HNO 3 (70 wt%): HF (49 wt%): CH 3 COOH (99.9 wt%): H 2 O = 40: A method of manufacturing a semiconductor device, comprising diluting a mixed solution having a composition ratio of 1: 2: 57 in water (H ₂ O) as an etching solution. The method of claim 3, And a region exposed by the silicon connection mask is in a wider range including an area exposed by a fin mask for forming the fin region. The method of claim 7, wherein The silicon connection mask defines a line-type exposed region. The method of claim 7, wherein And the silicon connection mask defines a plurality of rectangular exposed areas that are isolated from each other. 10. The method of claim 9, And the silicon connection mask exposes between two adjacent fin regions that intersect the active region. The method of claim 7, wherein And the silicon connection mask exposes a wider range of area than the fin mask only in an area crossing the active area. Forming a partially insulating substrate including an upper silicon film and a lower semiconductor substrate including a silicon connection region having a width wider than that of a fin transistor of the fin transistor; And Forming a transistor including the fin region on the partially insulating substrate Including, Forming the transistor Forming a trench using an ISO mask defining an active area; Wet etching the sacrificial layer exposed by the trench to form a partial insulation region; Forming an insulating insulating film in the trench and the partial insulating region; Etching the isolation insulating film using a fin mask; Forming a gate oxide film on the exposed active region; And Forming a gate electrode on the gate oxide film. The method of claim 12, And forming a saddle-shaped fin region by etching the isolation insulating layer and a portion of the active region together using the fin mask. The method of claim 12, And wherein the sacrificial film has an etching selectivity different from that of the upper silicon film and the lower semiconductor substrate, and the lattice constant is substantially the same as the lattice constant of silicon. The method of claim 13, Forming the trench Forming a second hard mask film on the partially insulating substrate; Applying a photoresist film and patterning with the ISO mask; Etching the second hard mask layer with a patterned photoresist; And And etching the upper silicon film and the lower semiconductor substrate by using an etched second hard mask film.

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