KR20090007978A - Semiconductor device and the method of forming the same - Google Patents

Abstract

A semiconductor device and a formation method thereof are provided to form a share contact plug of a dumbbell shape, thereby reducing damage of a spacer disposed in a side of a gate electrode in a share contact hole forming process. A gate insulating layer(120) and a gate electrode(130) are formed on a semiconductor substrate(100). A spacer(140) is formed in a side wall of the gate electrode. An interlayer insulating film(150) is formed on the front of the semiconductor substrate. A shared contact hole including a first part(180a) exposing the gate electrode by pattering the interlayer insulating film, a second part(180b) exposing the semiconductor substrate and a third part(180c) connecting the first part and the second part is formed. The first part, the second part and the third part are arranged along a first direction. The first and second parts respectively have maximum widths in a second direction orthogonal to the first direction. The third part has a width smaller than the maximum widths of the first and second parts in the second direction.

Description

Semiconductor device and method of forming the same {SEMICONDUCTOR DEVICE AND THE METHOD OF FORMING THE SAME}

1 is an equivalent circuit diagram of a general CMOS SRAM cell.

2 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.

3A and 3B are cross-sectional views taken along line II ′ of FIG. 2 and II-II ′ of FIG. 2 to illustrate a method of forming a semiconductor device according to example embodiments.

4A and 4B are cross-sectional views taken along the line II ′ of FIG. 2 and II-II ′ of FIG. 2, to illustrate a method of forming a semiconductor device according to example embodiments.

5A and 5B are cross-sectional views taken along the line II ′ of FIG. 2 and II-II ′ of FIG. 2, to illustrate a method of forming a semiconductor device according to example embodiments.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a shared contact plug.

Among the semiconductor memory devices, SRAM has lower power consumption and faster operating speed than DRAM.

1 is an equivalent circuit diagram of a general CMOS SRAM cell.

Referring to FIG. 1, the CMOS SRAM cell includes a pair of driving transistors TD1 and TD2, a pair of transfer transistors TA1 and TA2, and a pair of load transistors TL1 and TL2. . Here, the pair of driving transistors TD1 and TD2 and the pair of transfer transistors TA1 and TA2 are all NMOS transistors, while the pair of load transistors TL1 and TL2 are all PMOS transistors. admit.

The first driving transistor TD1 and the first transfer transistor TA1 are connected in series with each other. A source region of the first driving transistor TD1 is connected to a ground line Vss, and a drain region of the first transfer transistor TA1 is connected to a first bit line BL. Similarly, the second driving transistor TD2 and the second transfer transistor TA2 are also connected in series with each other. The source region of the second driving transistor TD2 is connected to the ground line Vss, and the drain region of the second transfer transistor TA2 is connected to the second bit line / BL.

The source region and the drain region of the first load transistor TL1 are connected to a power line Vcc and a drain region of the first driving transistor TD1, respectively. Similarly, the source region and the drain region of the second load transistor TL2 are connected to the power region Vcc and the drain region of the second driving transistor TD2, respectively. A drain region of the first load transistor TL1, a drain region of the first driving transistor TD1, and a source region of the first transfer transistor TA1 correspond to the first node N1. In addition, the drain region of the second load transistor TL2, the drain region of the second driving transistor TD2, and the source region of the second transfer transistor TA2 correspond to the second furnace N2. The gate electrode of the first driving transistor TD1 and the gate electrode of the first load transistor TL1 are connected to the second node N2, and the gate electrode and the second load transistor of the second driving transistor TD2. The gate electrode of TL2 is connected to the first node N1. In addition, gate electrodes of the first and second transfer transistors TA1 and TA2 are connected to a word line WL.

The equivalent circuit diagram of the CMOS SRAM cell shown in FIG. 1 may be implemented in a semiconductor substrate in various forms. The gate electrode of the second driving transistor TD2 and the gate electrode of the second load transistor TL2 are disposed at the first node N1, the drain region of the first load transistor TL1, and the first driving transistor ( The drain region of TD1 and the source region of the first transfer transistor TA1 are electrically connected to each other.

One object of the present invention is to provide a semiconductor device having a shared contact plug which improves the reliability of the semiconductor device and a method of forming the same.

In order to achieve the above technical problem, the present invention provides a method of forming a semiconductor device. The method includes forming a gate insulating film and a gate electrode on a semiconductor substrate, forming a spacer on a sidewall of the gate electrode, forming an interlayer insulating film on the front surface of the semiconductor substrate, and patterning the interlayer insulating film. Forming a shared contact hole comprising a first portion exposing a gate electrode, a second portion exposing the semiconductor substrate, and a third portion connecting the first portion and the second portion; The first portion, the second portion and the third portion are arranged along a first direction, the first and second portions each having maximum widths in a second direction orthogonal to the first direction, wherein the third portion is the first portion. It has a smaller width than the maximum widths of the first and second portions in two directions.

In order to achieve the above technical problem, the present invention provides a semiconductor device. The device includes a gate insulating film and a gate electrode formed on a semiconductor substrate, a spacer formed on sidewalls of the gate electrode, an interlayer insulating film formed on a front surface of the semiconductor substrate, a first portion disposed on the gate electrode, and a semiconductor substrate disposed on the semiconductor substrate. A shared contact plug comprising a second portion and a third portion connecting the first portion and the second portion, wherein the first portion, the second portion and the third portion are arranged along a first direction, and The first and second portions each have maximum widths in a second direction orthogonal to the first direction, and the third portion has a smaller width than the maximum widths of the first and second portions in the second direction. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

Referring to FIG. 1, in order to implement a CMOS SRAM cell, a drain of the first driving transistor TD1 and a source of the first transfer transistor TA1 may be formed and shared on the same active region. In addition, the gate electrode of the second driving transistor TD2 and the gate electrode of the second load transistor TL2 are connected to one common gate electrode, and the drain region of the common gate electrode and the first load transistor TL1 is formed. You can connect using one shared contact plug. On the other hand, the drain region of the first load transistor TL1 may exist in the active region of the semiconductor substrate, so that the shared contact plug has a height difference depending on a position.

The shared contact plug may form a shared contact hole, and may be formed by filling a conductive material in the shared contact hole. In the case of etching to form the shared contact hole, the spacer disposed on the sidewall of the shared gate electrode is overetched by the height difference between the common gate electrode and the semiconductor substrate, and the spacer is damaged. do. Damage to the spacer may worsen the defect and reliability of the device. Therefore, a technique for preventing damage to the spacer is needed.

2 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention. Here, the plan view shows two unit cells. Two unit cells neighboring each other along the X axis (first direction) are arranged to be mirror symmetric about the Y axis (second direction). In addition, two unit cells neighboring along the Y axis may be arranged to be mirror symmetric with respect to the X axis (not shown).

Referring to FIG. 2, first, second, third, and fourth active regions 105a, 105b, 105c, and 105d spaced apart from each other in the Y-axis direction are disposed on the semiconductor substrate 100. The active regions 105 are disposed to be parallel to the X axis. The active region 105 is defined by the device isolation layer 110. The length of the first active region 105a and the fourth active region 105d may be greater than the length of the second active region 105b and the third active region 105c. The second active region 105b may be aligned to the left of the unit cell region, and the third active region 105c may be aligned to the right of the unit cell region.

The first gate electrode 130a may be disposed to cross the upper portions of the first active region 105a and the second active region 105b and to cover a portion of the edge of the third active region 105c. Can be. The second gate electrode 130b is disposed to cross the upper portion of the fourth active region 105d. The third gate electrode 130c is disposed to cross the upper portion of the first active region 105a. The fourth gate electrode 130d is disposed to cross the upper portions of the third active region 105c and the fourth active region 105d, and is disposed to cover a portion of the edge of the second active region 105b. .

The transistor is defined by the gate electrode 130 and the active region 150. Specifically, the second driving transistor TD2 is defined by the first active region 105a and the first gate electrode 130a, and the second load transistor TL2 is defined by the second active region 105b. And the first gate electrode 130a, the first transfer transistor TA1 is defined by the fourth active region 105d and the second gate electrode 130b, and the second transfer transistor. TA2 is defined by the first active region 105a and the third gate electrode 130c, and the first load transistor TL1 includes the third active region 105c and the fourth gate electrode. 130d), and the first driving transistor TD1 is defined by the fourth active region 105d and the fourth gate electrode 130d. The first load transistor TL1 and the second load transistor TL2 are PMOS, and the other transistors are NMOS. Accordingly, the second and third active regions 105b and 105c may be N-type doped to form N wells, and the first and fourth active regions 105a and 150d may be formed to form NMOS / PMOS. It is doped with P well.

The gate electrodes 130 have spacers 140 on sidewalls.

The first gate electrode 130a, which is a gate electrode of the second driving transistor TD2 and the second load transistor TL2, has a drain region of the first driving transistor TD1 and the first load transistor TL1, and It is electrically connected to the source region of the first transfer transistor TA1. For this electrical connection, the first gate electrode 130a of the second load transistor TL2 is connected to the drain of the first load transistor TL1 through the shared contact plug 180. Since the first transfer transistor TA1 and the first driving transistor TD1 are disposed in the fourth active region 105d, the source of the first transfer transistor TA1 and the first driving transistor TD1 are separated from each other. The drains are shared with each other. Therefore, a wiring (not shown) may be formed to electrically connect the source of the first transfer transistor TA1 and the drain of the first driving transistor TD1 with the shared contact plug 180. That is, the contact plug 175 is formed on the source of the first transfer transistor TA1 and the drain of the first driving transistor TD1, and the shared contact plug 180 and the contact plug 175 are mutually connected. Metal wires (not shown) are formed to be electrically connected.

In addition, the fourth gate electrode 130d, which is a gate electrode of the first driving transistor TD1 and the first load transistor TL1, drains the second driving transistor TD2 and the second load transistor TL2. And a source region of the second transfer transistor TA2. For this electrical connection, the fourth gate electrode 130d of the first load transistor TL1 is connected to the drain of the second load transistor TL2 through a shared contact plug 180. Since the second transfer transistor TA2 and the second driving transistor TD2 are disposed in the first active region 105a, the source of the second transfer transistor TA2 and the first driving transistor TD2 are disposed. The drain of is shared. Therefore, a wiring (not shown) may be formed to electrically connect the source of the second transfer transistor TA2 and the drain of the second driving transistor TD2 with the shared contact plug 180. That is, the contact plug 175 is formed on the source of the second transfer transistor TA2 and the drain of the second driving transistor TD2, and the shared contact plug 180 and the contact plug 175 are mutually connected. Metal wires (not shown) may be formed to be electrically connected.

The shared contact plugs 180 electrically connect the first gate electrode 130a and the third active region 105c and connect the fourth gate electrode 130d and the second active region 105b. It is electrically conductive part.

Specifically, the shared contact plug 180 may include a first portion 180a disposed on the first gate electrode 130a, a second portion 180b disposed on the third active region 105c, and And a third portion 180c connecting the first portion 180a and the second portion 180b, wherein the first portion 180a, the second portion 180b, and the third portion 180c are formed of a third portion 180c. Arranged along one direction, the first and second portions 180a and 180b each have a maximum width a in a second direction orthogonal to the first direction, and the third portion 180c is The width b is smaller than the maximum widths a of the first and second portions 180a and 180b in the second direction. An interval c of the first portion 180a and the second portion 180b may be greater than an interval d of the spacer 140.

According to a modified embodiment of the present invention, the widths of the first portion 180a and the second portion 180b may be different from each other. In addition, the first portion 180a and the second portion 180b may be deformed into a circle, an ellipse, a rectangle, or the like in the plan view.

3A and 3B are cross-sectional views taken along line II ′ of FIG. 2 and II-II ′ of FIG. 2 to illustrate a method of forming a semiconductor device according to example embodiments.

Referring to FIG. 3A, a plurality of device isolation layers 110 and active regions 105 may be formed on the semiconductor substrate 100. The active regions 105 are arranged to be parallel to the X axis, as described with reference to FIG. 2.

A gate insulating layer 120 is formed on the semiconductor substrate 100 on which the active region 105 is formed. The gate insulating layer 120 is a silicon oxide film and may be formed by a thermal oxide film manufacturing process.

A gate conductive layer may be formed on the semiconductor substrate 100 on which the gate insulating layer 120 is formed. The gate conductive layer may be doped polysilicon. The gate conductive layer may be patterned to form the gate electrode 130. A spacer layer may be formed on the semiconductor substrate 100 on which the gate electrode 130 is formed, and the spacer layer may be formed by anisotropic etching of the spacer layer. An interlayer insulating layer 150 may be formed on the semiconductor substrate 100 on which the spacer 140 is formed. Subsequently, the interlayer insulating layer 150 may be planarized by performing a planarization process.

A first portion 170a exposing the gate electrode 130 by patterning the interlayer insulating layer 150, a second portion 170b exposing the semiconductor substrate 100, and the first portion 170a and The method may include forming a shared contact hole 170 including a third portion 170c connecting the second portion 170b. In the shared contact hole 170, the first portion 170a, the second portion 170b, and the third portion 170c are arranged along a first direction, and the first and second portions 170a and 170b are disposed in the first direction. ) Have maximum widths in a second direction orthogonal to the first direction, and the third portion 170c is larger than the maximum widths of the first and second portions 170a and 170b in the second direction. Have a small width.

In detail, the forming of the shared contact hole 170 may include forming a shared contact mask pattern 160, and etching the interlayer insulating layer 150 using the shared contact mask pattern 160 as an etching mask. The method may include forming a contact hole 170.

In the forming of the shared contact mask pattern, a photoresist may be coated and exposed using photolithography exposure equipment to form the shared contact mask pattern 160. The shared contact mask pattern 160 may remove the photoresist to form a dumbbell shape. The portion 190 from which the photoresist is removed from the shared contact mask pattern 160 may be composed of a first portion 190a, a second portion 190b, and a third portion 190c. When the interlayer insulating layer 150 is etched using the shared contact mask pattern 160 as an etch mask, the first portion 170a, the second portion 170b, and the third portion 170c of the shared contact hole 170 are etched. ), Respectively.

The third portion, which is the central portion of the portion 190 in which the photoresist is removed from the shared contact mask pattern 160, may be disposed on the spacer 140. The third portion 190c may be formed by arranging two contact mask patterns adjacent to each other, or may be formed by providing a connection portion connecting the two contact mask patterns and the two contact mask patterns. The photoresist may be partially removed from the third portion 190c, but photoresist may remain in some portions in the Y-axis direction. That is, the thickness of the remaining photoresist may vary depending on the location. That is, the photoresist of the third portion may have a different thickness in the Y-axis direction due to a known optical proximity effect.

4A and 4B are cross-sectional views taken along the line II ′ of FIG. 2 and II-II ′ of FIG. 2, to illustrate a method of forming a semiconductor device according to example embodiments.

The forming of the shared contact hole 170 by etching the interlayer insulating layer 150 may be performed by etching the shared contact mask pattern 190 with an etching mask until the semiconductor substrate 100 is exposed. 170 can be formed. The shared contact hole 170 may include a first region 170a through which the gate electrode 130 is exposed, a second region 170b through which the semiconductor substrate 100 is exposed, and the first region and the second region. It may be divided into a third region 170c connecting the.

 In the etching step, the interlayer insulating layer 150 and the spacer 140 may have an etching selectivity. That is, the etching rate of the spacer 140 may be smaller than the etching rate of the interlayer insulating layer 150.

Since the thickness of the photoresist may vary depending on the location of the shared contact mask pattern 190, when the interlayer insulating layer 150 is etched using the shared contact mask 190 as an etch mask, the interlayer insulating layer 150 may be disposed according to a location. Recess degrees of the insulating layer 150 and the spacer 140 may be different. In addition, in the etching process, a conventional contact hole 175 exposing the semiconductor substrate 100 or exposing the gate electrode 130 may be formed.

According to an embodiment of the present disclosure, the method may further include forming a plurality of device isolation layers 110 and active regions 105 in the semiconductor substrate 100, wherein the gate electrode having the first portion may be formed. The active region of the transistor formed by 130 and the active region 105 where the second portion is formed may be different active regions.

According to a modified embodiment of the present invention, the method may further include forming a plurality of device isolation layers 110 and active regions 105 in the semiconductor substrate 100, wherein the gate electrode on which the first portion is formed is formed. The active region of the transistor formed by 130 and the active region 105 in which the second portion is formed may be the same active region.

5A and 5B are cross-sectional views taken along line II ′ of FIG. 2 and II-II ′ of FIG. 2 to illustrate a method of forming a semiconductor device, according to an embodiment of the inventive concept.

The shared contact hole 170 may be filled with a conductive material. The conductive material may include at least one selected from doped polysilicon, a metal, or a metal alloy. The shared contact plug 180 and the contact plug 185 may be formed by planarizing the semiconductor substrate 100 on which the conductive material filling the shared contact hole 170 is formed.

In addition, the contact hole 185 may be formed by filling the normal contact hole 175 with a conductive material.

The planarization may be a chemical mechanical polishing technique or an etch back technique. The planarization may be performed until the interlayer insulating layer 150 is exposed.

Subsequently, a wiring process for connecting the shared contact plug 180 and / or the contact plug 185 may be performed.

Referring again to FIGS. 5A and 5B, the semiconductor device of the present invention may include a gate insulating layer 120 and a gate electrode 130 formed on the semiconductor substrate 100, and spacers formed on sidewalls of the gate electrode 130. 140, an interlayer insulating layer 150 formed on the entire surface of the semiconductor substrate 100, a first portion 180a disposed on the gate electrode 130, and a second portion disposed on the semiconductor substrate 100. A shared contact plug 180 including a 180b and a third portion 180c connecting the first and second portions. The first portion 180a, the second portion 180b, and the third portion 180c are arranged along a first direction, and the first and second portions 180a and 180b are orthogonal to the first direction. Each of the maximum widths in one second direction, and the third portion 180c has a smaller width than the maximum widths a of the first and second portions 180a and 180b in the second direction. The shared contact plug 180 may have a dumbbell shape in plan view.

The semiconductor substrate 100 may include one of a silicon substrate, a germanium substrate, and a silicon on insulator (SOI) substrate. The device isolation layer 110 may include at least one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. As described with reference to FIG. 2A, an active region 105 is disposed by the device isolation layer 110.

The gate insulating layer 120 may include at least one of a silicon oxide layer and a silicon oxynitride layer. The gate electrode 130 is a conductive material and may include at least one of metal, metal alloy, and doped polysilicon.

The spacer 140 formed on the sidewall of the gate electrode 130 may include at least one of a silicon nitride film and a silicon oxide film.

The interlayer insulating layer 150 formed on the entire surface of the semiconductor substrate 100 may be a silicon oxide layer. The interlayer insulating layer 150 may be planarized so that an upper surface of the interlayer insulating layer 150 may be maintained at a constant height.

When the spacer 140 is cut in the X-axis direction at the center of the shared contact plug 180, the spacer 140 may be damaged, and a part of the spacer 140 may be lost at the upper side of the gate electrode 130.

Referring back to FIG. 5A, when the cutoff is slightly off the center of the shared contact plug 180 and cut in the X-axis direction, the interlayer insulating layer 150 is formed under the third portion 180c of the shared contact plug 180. It can remain without being removed. The shape of the remaining interlayer insulating layer 150 may be variously modified. The remaining interlayer insulating layer 150 prevents the spacer 140 from being damaged. However, the first portion 180a and the second portion 180b of the shared contact plug 180 are electrically connected through the third portion 180c. As a result, damage to the spacer 140 may be reduced by forming the shared contact plug 180.

Referring back to FIG. 5B, when cut in the Y-axis direction from the center of the shared contact plug 180, the third portion 180c is positioned at the portion in contact with the spacer 140 and the interlayer insulating layer 150. There may be a change in the slope. Specifically, since the third portion 180c is determined by the shape of the shared contact hole 170, the third portion 170c of the shared contact hole 170 is formed along the Y axis of the spacer 140. The thickness of the interlayer insulating layer 150 may be different. Therefore, the third portion may have a change in inclination along the Y axis.

If the third portion 180c of the shared contact plug 180 is not present, some or all of the interlayer insulating layer 150 on the active region 105 may be removed, and thus the spacer 140 may be damaged. have.

Therefore, in order to minimize the damage of the spacer 140, the shape of the shared contact plug 180 is deformed into a dumbbell shape to protect the spacer 140.

According to the present invention as described above, a dumbbell-shaped shared contact plug is formed. In the process of forming the shared contact hole, damage to the spacer disposed on the side of the gate electrode can be reduced. As a result, the damage prevention of the spacer can improve the reliability of the device.

Claims (8)

Forming a gate insulating film and a gate electrode on the semiconductor substrate; Forming a spacer on sidewalls of the gate electrode; Forming an interlayer insulating film on the entire surface of the semiconductor substrate; And Patterning the interlayer insulating film to form a shared contact hole including a first portion exposing the gate electrode, a second portion exposing the semiconductor substrate, and a third portion connecting the first portion and the second portion Including steps, The first portion, the second portion and the third portion are arranged along a first direction, the first and second portions each having maximum widths in a second direction orthogonal to the first direction, And the third portion has a smaller width than the maximum widths of the first and second portions in the second direction. The method of claim 1, The forming of the shared contact hole may include Forming a shared contact mask pattern on the interlayer insulating film, and Etching the interlayer insulating layer using the shared contact mask pattern as an etch mask, And wherein the shared contact mask pattern on the third portion has a different thickness along the second direction due to an optical proximity effect. The method of claim 2, The etching of the interlayer insulating layer may include forming spacers on the third portion having different thicknesses in a second direction. The method of claim 1, The method may further include forming a plurality of device isolation layers and active regions in the semiconductor substrate. The active region of the transistor formed by the gate electrode on which the first portion is formed and the active region on which the second portion is formed are different active regions. The method of claim 1, The method may further include forming a plurality of device isolation layers and active regions in the semiconductor substrate. The active region of the transistor formed by the gate electrode on which the first portion is formed and the active region on which the second portion is formed are the same active region. The method of claim 1, Wherein a gap between the first portion and the second portion is greater than a gap between the spacers. A gate insulating film and a gate electrode formed on the semiconductor substrate; A spacer formed on sidewalls of the gate electrode; An interlayer insulating film formed on the entire surface of the semiconductor substrate; A shared contact plug including a first portion disposed on the gate electrode, a second portion disposed on the semiconductor substrate, and a third portion connecting the first portion and the second portion, The first portion, the second portion and the third portion are arranged along a first direction, the first and second portions each having maximum widths in a second direction orthogonal to the first direction, And the third portion has a smaller width than the maximum widths of the first and second portions in the second direction. The method of claim 7, wherein Wherein a gap between the first portion and the second portion is greater than a gap between the spacers.

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