KR101003120B1 - Digital temperature information generator of semiconductor integrated circuit - Google Patents

Abstract

The present invention provides a multiple frequency division signal generation unit configured to generate the multiple frequency division signal using a second periodic signal; A control unit configured to activate a latch control signal by determining whether a transition of the multi-division signal is completed at a timing of generating a pulse of a first periodic signal; A periodic latch unit configured to latch the multiple frequency division signal in response to activation of the latch control signal; And a decoding unit for decoding the multiple divided signals latched by the period latch unit to generate temperature information.

LTCSR, EMRS

Description

DIGITAL TEMPERATURE INFORMATION GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a digital temperature information generating device of a semiconductor integrated circuit.

As a representative example of a semiconductor integrated circuit, a semiconductor memory device is a device that writes data in a memory cell or outputs data written in the memory cell to the outside.

The semiconductor memory device has an operation mode called refresh which must be performed in order to prevent loss of data written in the memory cell.

The refresh may be classified into a self refresh performed in the semiconductor memory device itself and an auto refresh performed according to a command external to the semiconductor memory device.

The self refresh is periodically performed inside the semiconductor memory device.

Therefore, the semiconductor memory device needs a periodic signal for determining the timing of the self refresh operation.

The periodic signal is called a self refresh signal and is generated and used in the semiconductor memory device.

In order to increase the efficiency of the self refresh operation, a technique of varying a period of the self refresh signal according to an ambient temperature is applied.

The auto refresh operation also requires temperature information around the semiconductor memory device in order to apply the technology of varying the cycle of the auto refresh signal according to the ambient temperature.The JEDEC (Joint Electron Device Engineering Council) standard related to mobile DRAM requires DRAM pads. The refresh rate according to the temperature information output through the DQ8 to DQ10 is defined.

However, the development of hardware and software for providing the temperature information on the semiconductor integrated circuit side has not been made until now.

An object of the present invention is to provide an apparatus for generating digital temperature information of a semiconductor integrated circuit capable of detecting accurate temperature information in response to an error and providing the detected temperature information in the form of a digital code.

In accordance with another aspect of the present invention, an apparatus for generating digital temperature information of a semiconductor integrated circuit may include: a multiple frequency division signal generation unit configured to generate the multiple frequency division signal using a second periodic signal; A control unit configured to activate a latch control signal by determining whether a transition of the multi-division signal is completed at a timing of generating a pulse of a first periodic signal; A periodic latch unit configured to latch the multiple frequency division signal in response to activation of the latch control signal; And a decoding unit for decoding the multiple divided signals latched by the period latch unit to generate temperature information.

The digital temperature information generating apparatus of the semiconductor integrated circuit according to the present invention can generate the digital temperature information by itself and output it in a format that can be used externally, so that the semiconductor integrated circuit can be quickly used in response to technological changes related to the semiconductor integrated circuit. In addition, the range may be expanded, and the reliability of the temperature information may be improved by minimizing an error that may occur when the temperature information is detected.

Hereinafter, a preferred embodiment of a digital temperature information generating device of a semiconductor integrated circuit according to the present invention will be described.

1 is a block diagram of a digital temperature information generating device of a semiconductor integrated circuit according to the present invention.

As shown in FIG. 1, the apparatus for generating digital temperature information of a semiconductor integrated circuit according to the present invention includes a multi-division signal generating unit 510, a control unit 520, a period latch unit 530, a first decoder 540 and A second decoder 550 is provided.

The multiple frequency division signal generation unit 510 receives the second period signal OSC2 and sequentially divides the plurality of frequency division periods 511 to sequentially divide the frequency division ratio X2 and output the multiple frequency division signals S1 to S64. Equipped. The plurality of dividers 511 may be configured in the same manner.

The controller 520 may be configured to generate pulse timings of the first divided period signal X2OSC1 dividing the first period signal OSC1 by two or the second divided period signal X8OSC2 by dividing the second periodic signal OSC2 by eight. The latch control signals A and B are generated in accordance with the multiple frequency division signals S1 to S64.

As the first periodic signal OSC1, a signal output from a linear temperature compensated self refresh oscillator may be used.

As the second periodic signal OSC2, an EMRS signal output from an extended mode register set (EMRS) oscillator may be used.

When the transition of the multiple frequency division signals S1 to S64 is not completed at the time when the pulse of the first frequency division signal X2OSC1 or the second frequency division signal X8OSC2 is generated, the controller 520 may perform a multiple frequency division signal. The latch control signals A and B are activated after the transition of S1 to S64 is completed.

When the transition of the multiple division signals S1 to S64 is completed at the time when the pulse of the first division period signal X2OSC1 or the second division period signal X8OSC2 is generated, the controller 520 immediately controls the latch control signal. Configured to activate (A, B).

The control unit 520 is configured to deactivate the latch control signals A and B in response to a reset signal RST and to activate the latch control signals A and B in response to a power-up signal PWRUP. do.

The controller 520 may operate with only one first division period signal X2OSC1. The reason why the second frequency division signal X8OSC2 is additionally used is as follows. When the first periodic signal OSC1 is used as a reference for determining a self refresh rate, the first periodic signal OSC1 increases indefinitely at a temperature lower than a certain temperature (for example, 37 ° C.) to cause a refresh failure. In order to prevent this, a cycle according to the EMRS divided by 4 minutes compared to the basic period is used instead of the first period signal OSC1 by a function called a cold stopper. Therefore, the second frequency division signal X8OSC2 is used to prepare for the case where the temperature is lower than 37 ° C. In addition, the reason why the first division period signal (X2OSC1) dividing the oscillation signal output from the LTCSR oscillator (Linear Temperature Compensated Self Refresh Oscillator) is divided into two parts is because the temperature sensing performance is improved as the division ratio is increased. It is for the same reason to use the second frequency division signal X8OSC2.

The cycle latch unit 530 is configured to output the latched multiple frequency division signals S1_LAT to S64_LAT by latching the multiple frequency division signals S1 to S64 when the latch control signals A and B are activated. . The period latch unit 530 is configured to receive the multiple division signals S1 to S64 in response to the deactivation of the latch control signals A and B. FIG. The cycle latch unit 530 receives the latch control signals A and B in common and receives a plurality of latch circuits 531 that receive the multiple division signals S1 to S64 output from the plurality of dividers 511. ). The plurality of latch circuit units 531 may be configured in the same manner.

The first decoder 540 is configured to decode the multiple divided signals S1_LAT to S64_LAT latched in the period latch unit into first digital codes Temp100 to Temp55L defining a temperature.

The second decoder 550 decodes the first digital code Temp100 to Temp55L, that is, a 3 bit second digital code DTI0 to DTI2 that conforms to the semiconductor memory standard, that is, the JEDEC standard. Is configured to output

FIG. 2 is a circuit diagram of the controller of FIG. 1.

As illustrated in FIG. 2, the controller 520 includes a first activation unit 521, a second activation unit 522, a latch 523, an initial activation unit 524, and a reset unit 525. .

The first activator 521 is configured to perform the multi-dividing signal S1 at the time when the pulse of the first division period signal X2OSC1 or the second division period signal X8OSC2 is generated during the activation period of the refresh pulse signal PSRF. Is configured to block activation of the latch control signals (A, B) when a falling edge is detected. The first activator 521 is configured to perform the multi-dividing signal S1 at the time when the pulse of the first division period signal X2OSC1 or the second division period signal X8OSC2 occurs during the activation period of the refresh pulse signal PSRF. Is configured to activate the latch control signals (A, B) if no polling edge is detected. The first activator 521 may include first and second NOR gates NR1 and NR2, NAND gates ND1, first and second inverters IV1 and IV2, and a falling pulse generator (FPG). And the first transistor M1. The falling pulse generator FPG may be implemented by a seventh inverter IV7, a second delay element DLY2, and a third NOR gate NR3.

The second activator 522 activates the latch control signals A and B after a set time from the time when the pulse of the first division period signal X2OSC1 or the second division period signal X8OSC2 occurs. It is configured to. The second activation unit 522 may be implemented with a first delay element DLY1 and a second transistor M2.

The latch 523 is configured to latch the latch control signals A and B and may be implemented by the fourth and fifth inverters IV4 and IV5.

The initial activation unit 524 is configured to activate the latch control signals A and B according to a power up signal PWRUP. The initial activation unit 524 may be implemented with a third inverter IV3 and a third transistor M3.

The reset unit 525 is configured to deactivate the latch control signals A and B according to the reset signal RST, and may be implemented by the fourth transistor M4.

2 illustrates an example in which a circuit is configured by setting the latch control signals A and B to be activated when A is a low level and B is a high level.

3 is a circuit diagram of a latch circuit of FIG. 1.

As shown in FIG. 3, the latch circuit unit 531 includes a plurality of tree state inverters TIV11 and TIV12, a plurality of latches 51-1 and 531-2, and an inverter IV15. The tree state inverter TIV11 is configured to pass the multiple frequency division signal S1 when the latch control signals A and B are deactivated (A = high level, B = low level). The tree state inverter TIV12 is configured to pass the output of the latch 531-1 when the latch control signals A and B are activated (A = low level, B = high level). The latch 531-2 and the inverter IV15 are configured to latch the output of the tree state inverter TIV12 to output the latched multiple division signal S1_LAT.

4 is a waveform diagram illustrating an example of occurrence of temperature information detection error.

As shown in FIG. 4, when the latch point DP of the multiple frequency division signals S1 to S64 is wrong, that is, when the transition of the multiple frequency division signals S1 to S64 is not completed at the latch point DP. The digital temperature information generated by latching is likely to be different from the target information. In this case, the latch point DP refers to an activation timing of the latch control signals A and B.

5 is a waveform diagram illustrating a method of detecting temperature information according to the present invention.

Therefore, in the present invention, the latch control after the set time, that is, after the transition of the multi-dividing signals S1 to S64 is completed, from the time point at which the pulse of the first division period signal X2OSC1 or the second division period signal X8OSC2 occurs. The signals A and B are activated, and as shown in FIG. 5, the latch point DP is positioned after the transition of the multiple frequency division signals S1 to S64 is completed.

The operation of the digital temperature information generating device of the semiconductor integrated circuit according to the present invention configured as described above is as follows.

FIG. 6 is a graph comparing periods of a first period signal and a second period signal according to temperature, and FIG. 7 is a diagram illustrating a method of decoding temperature information according to the present invention.

First, the operation principle of the present invention will be described with reference to FIGS. 6 and 7.

Since the period of the first periodic signal OSC1 is different for each temperature, a pulse generation timing is also different. FIG. 6 illustrates a timing of generating a pulse of the first periodic signal OSC1 with multiple divided signals S1 to S64 that divide the second periodic signal OSC2 for each temperature section. Since the multiple divided signals S1 to S64 have a constant period regardless of the temperature, the multiple divided signals S1 to S64 are latched at the pulse generation timing of the first periodic signal OSC1 to read the value. It will have the same value as 7. The present invention latches the multiple frequency division signals S1 to S64 at the timing of the pulse generation of the first frequency division signal X2OSC1 in which the first period signal OSC1 is divided, and decodes the latched value. As shown in FIG. 7, the digital temperature information conforming to the JEDEC standard is output. In FIG. 7, the temperature range is not a JEDEC standard, and shows an example as a value that can be arbitrarily set by the manufacturer.

Hereinafter, the operation of the digital temperature information generating device of the semiconductor integrated circuit according to the present invention will be described.

Each divider 511 of FIG. 2 divides the second periodic signal OSC2 according to a reset signal RST to generate multiple divided signals S1 to S64.

When the power-up signal PWRUP is activated, the controller 520 of FIG. 2 activates the latch control signals A and B so that the multi-dividing signal 530 may be transmitted to the periodic latch unit 530 until the reset signal RST is activated. Do not enter S1 to S64).

When the reset signal RST is activated, the controller 520 inactivates the latch control signals A and B to block the output of the latched multiple frequency division signals S1_LAT to S64_LAT, and the cycle latch unit All latch circuits 531 of 530 receive the multi-division signals S1 to S64.

When the falling edge of the multi-dividing signal S1 is detected at a timing at which the pulse of the first division period signal X2OSC1 or the pulse of the second division period signal X8OSC2 is generated, the controller 520 detects the falling edge of the multi-division signal S1. The polling pulse P1 is generated through the polling pulse generator FPG.

Activation of the latch control signals A and B by the first transistor M1 is blocked by the falling pulse P1.

At this time, when the pulse of the first division period signal X2OSC1 or the pulse of the second division period signal X8OSC2 is generated, the falling edge of the multiple division signal S1 is detected. This means that the transition is not complete. Therefore, it is determined whether the transition is completed by using the multiple division signal S1 having the most advanced timing among the multiple division signals S1 to S64. In addition, the time for completing the transition of the entire multi-dispense signals S1 to S64 from the falling edge generation timing of the multi-dispense signal S1 is constant, for example, may be 20 ns. Therefore, when the falling edge of the multi-dividing signal S1 is detected at the timing when the pulse of the first division period signal X2OSC1 or the pulse of the second division period signal X8OSC2 is generated, the falling pulse P1 having a pulse width of 20 ns. Is generated to block the activation of the latch control signals (A, B).

The generated pulse of the first division period signal X2OSC1 or the pulse of the second division period signal X8OSC2 is a pulse P2 delayed by a predetermined time (for example, 30 ns) through the first delay element DLY1. The latch control signals A and B are activated by the second transistor M2 which is output and receives the delayed pulse P2.

On the other hand, if the falling edge of the multiple frequency division signal S1 is not detected at the timing at which the pulse of the first division period signal X2OSC1 or the pulse of the second division period signal X8OSC2 is generated, the falling pulse P1 is not generated. Therefore, the latch control signals A and B are activated by the first transistor M1.

Referring to FIG. 3, all of the latch circuit units 531 of the period latch unit 530 may have multiple division signals S1 to S64 latched to the latches 531-1 when the latch control signals A and B are activated. Is passed through the tree state inverter TIV12 and output as multiple divided signals S1_LAT to S64_LAT latched through the latch 531-2 and the inverter IV15.

The first decoder 540 of FIG. 1 decodes the latched multiple divided signals S1_LAT to S64_LAT and outputs the first digital codes Temp100 to Temp55L. The first digital codes Temp100 to Temp55L decode only the codes of the temperature range corresponding to the latched multiple frequency division signals S1_LAT to S64_LAT to a high level. For example, the multi-dividing signal (S1 ~ S64) value is X / X / X / L / L / L / L, X / X / L / H / L / L / L or L / L / H / H If one of / L / L / L, the temperature is more than 100 ℃ decode only Temp100 of the first digital code (Temp100 ~ Temp55L) to a high level and the rest of the value to a low level. Among the values of the multiple divided signals S1 to S64, X means don 'care, L means low level, and H means high level.

The second decoder 550 of FIG. 1 decodes the first digital codes Temp100 to Temp55L into second digital codes DTI0 to DTI2 in accordance with the JEDEC standard. As shown in FIG. 7, for example, if only Temp85 is decoded at a high level among the first digital codes Temp100 to Temp55L, the second digital codes DTI0 to DTI2 are decoded as '101'. As another example, if only Temp75 is decoded at a high level among the first digital codes Temp100 to Temp55L, the second digital codes DTI0 to DTI2 are decoded as '001'.

8 and 9 are waveform diagrams showing the results of the temperature information decoding simulation at the specific temperature of FIG. 7, respectively.

The actual simulation results at 100 ° C. temperature are shown in FIG. 8. Referring to FIG. 8, after the reset signal RST is activated, a value of latching the multi-dividing signals S1 to S64 at the time when a pulse of the first division period signal X2OSC1 is generated is L / L / H. It is / H / L / L / L, and it can be seen that it is equal to the value of the multi-dividing signals S1 to S64 defined in the temperature range of 100 ° C. of FIG. 7.

The simulation results at 70 ° C. temperature are also shown in FIG. 9. Referring to FIG. 9, after the reset signal RST is activated, a value of latching the multi-dividing signals S1 to S64 at the time when a pulse of the first division period signal X2OSC1 is generated is L / H / L. It is / H / H / L / L, and it can be seen that it corresponds to X / X / X / H / H / L / L, which is the value of the multi-dividing signals S1 to S64 defined in the temperature range of 55 ° C. or higher in FIG. 7.

When the value of the second digital codes DTI0 to DTI2 generated as described above is output to the outside of the semiconductor integrated circuit as digital temperature information through the pads DQ8 to DQ10, a memory controller, for example, a graphics processing unit (GPU) The digital temperature information may be used to determine an auto refresh rate.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a digital temperature information generating device of a semiconductor integrated circuit according to the present invention;

2 is a circuit diagram of the controller of FIG. 1;

3 is a circuit diagram of a latch circuit of FIG. 1;

4 is a waveform diagram showing an example of occurrence of temperature information detection error;

5 is a waveform diagram showing a temperature information detection method according to the present invention;

6 is a period comparison graph of a first periodic signal and a second periodic signal according to temperature;

7 is a view showing a method for decoding temperature information according to the present invention;

8 and 9 are waveform diagrams showing the results of the temperature information decoding simulation at the specific temperature of FIG. 7, respectively.

Description of the main parts of the drawing

510: multiple dispenser 520: control unit

530: cycle latch portion 531: latch circuit portion

540: first decoder 550: second decoder

Claims (16)

A multiple divided signal generator configured to generate a multiple divided signal using the second periodic signal, A control unit configured to activate a latch control signal by determining whether the multi-dividing signal has completed transition at a pulse generation timing of a first periodic signal; A periodic latch unit configured to latch the multiple frequency division signal in response to activation of the latch control signal; And a decoding unit configured to generate temperature information by decoding the multiple divided signals latched by the period latch unit. The method of claim 1, And the first periodic signal is an oscillation signal generated by an LTCSR oscillator (Linear Temperature Compensated Self Refresh Oscillator). The method of claim 2, The second periodic signal is Extended Mode Register Set (EMRS) Digital temperature information generating device of a semiconductor integrated circuit, characterized in that the oscillator generated oscillation signal. The method of claim 3, wherein The multi-division signal generator And a plurality of dividers for sequentially dividing and outputting the second periodic signals at respective division ratios. The method of claim 4, wherein The division ratio of the plurality of frequency dividers is the same as each other, the digital temperature information generating device of a semiconductor integrated circuit. The method of claim 3, wherein The control unit And generating the digital temperature information of the semiconductor integrated circuit, in response to the pulse of the first periodic signal, when the transition of the multi-division signal is completed at the timing of generating the pulse of the first periodic signal. Device. The method of claim 6, The control unit And if the transition of the multi-dividing signal is not completed at the pulse generation timing of the first period signal, activating the latch control signal after a set time from the pulse generation timing of the first period signal. Digital temperature information generation device. The method of claim 7, wherein The control unit A first activation unit configured to block activation of the latch control signal when a falling edge of any one of the multiple frequency division signals is detected at the time when the pulse of the first periodic signal is generated; A second activation unit configured to activate the latch control signal after a set time from a time point when the pulse of the first periodic signal is generated; and And a reset unit configured to deactivate the latch control signal according to a reset signal. The method of claim 8, And an initial activation unit configured to activate the latch control signal in response to a power-up signal. The method of claim 7, wherein The control unit When a falling edge of any one of the multiple frequency division signals is detected at the time when a pulse of the first frequency division frequency signal that divides the first period signal or the second frequency division frequency signal that divides the second period signal is generated, the A first activator configured to block activation of the latch control signal, A second activator configured to activate the latch control signal after a set time from a time point when the pulse of the first division period signal or the second division period signal is generated, and And a reset unit configured to deactivate the latch control signal according to a reset signal. The method of claim 10, And an initial activation unit configured to activate the latch control signal in response to a power-up signal. The method of claim 3, wherein The cycle latch unit And outputting a latched signal at the same time as blocking the input of the multi-division signal in response to the activation of the latch control signal. 13. The method of claim 12, The cycle latch unit And receiving the multi-division signal in response to deactivation of the latch control signal. The method of claim 13, The cycle latch unit And a plurality of latch circuits configured to receive the latch control signal in common and to receive the multiple divided signals. The method of claim 14, The latch circuit portion A first switching element configured to pass the multiple frequency division signal in response to the latch control signal, A first latch for latching an output of the first switching element, A second switching element for passing the output of said first latch in response to said latch control signal of opposite logic; and And a second latch for latching an output of the second switching element. The method of claim 1, The decoding unit A first decoder for decoding the multiple divided signal latched in the period latch unit into a first digital code form defining a temperature; and And a second decoder for decoding the first digital code output from the first decoder into a second digital code conforming to a semiconductor memory standard.

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