KR100920842B1 - Refresh period signal generator with digital temperature information generation - Google Patents

Abstract

PURPOSE: A refresh period signal generator having a digital temperature information generating function is provided to expand an application range of a semiconductor integrated circuit by rapidly coping with a technology change related to a semiconductor integrated circuit. CONSTITUTION: A refresh period signal generator includes a temperature information generating part(500), a refresh period signal generating part(600), and an operation timing control part(700). The temperature information generating part generates temperature information using a first period signal and a second period signal. The refresh period signal generating part compares the first period signal with the second period signal. The refresh period signal generating part selects and outputs a signal having a short period as a period signal. The operation timing control part operates the temperature information generating part and the refresh period signal generating part during a predetermined timing.

Description

Refresh cycle signal generator with digital temperature information generation {REFRESH PERIOD SIGNAL GENERATOR WITH DIGITAL TEMPERATURE INFORMATION GENERATION}

The present invention relates to a periodic signal generator, and more particularly, to a refresh periodic signal generator having a digital temperature information generating function.

As a representative example of a semiconductor integrated circuit, a semiconductor memory device is a device that writes data in a memory cell or outputs data written in the memory cell to the outside.

The semiconductor memory device has an operation mode called refresh which must be performed in order to prevent loss of data written in the memory cell.

The refresh may be classified into a self refresh performed in the semiconductor memory device itself and an auto refresh performed according to a command external to the semiconductor memory device.

The auto refresh is performed only when a command is input from the outside of the semiconductor memory device, while the self refresh is periodically performed inside the semiconductor memory device.

Therefore, the semiconductor memory device needs a periodic signal for determining the timing of the self refresh operation.

The periodic signal is called a refresh signal and is generated and used in the semiconductor memory device.

In order to increase the efficiency of the self-refresh operation, a technique of varying the period of the refresh signal according to the ambient temperature is applied. To this end, a device called a TCSR oscillator (Temperature Compensated Self Refresh Oscillator) is used.

1 is a temperature / cycle output graph of a self refresh signal according to the related art.

As shown in FIG. 1, the TCSR oscillator increases the period of the pulse signal as the temperature decreases, and the semiconductor memory device uses the generated pulse signal as the refresh signal.

The TCSR oscillator has an advantage of enabling efficient self refresh operation by varying the period of the refresh signal.

However, as shown in Fig. 1, the TCSR oscillator is a refresh signal with an excessively increased period at a certain temperature, for example, 37 ° C. or lower (commonly referred to as room temperature or cold temperature in semiconductor circuit technology). This can cause a serious error that prevents the self-refresh operation itself.

The auto refresh operation also requires temperature information around the semiconductor memory device in order to apply the technology of varying the cycle of the auto refresh signal according to the ambient temperature.The JEDEC (Joint Electron Device Engineering Council) standard related to mobile DRAM requires DRAM pads. The refresh rate according to the temperature information output through the DQ8 to DQ10 is defined.

However, the development of hardware and software for providing the temperature information on the semiconductor integrated circuit side has not been made until now.

The present invention provides a refresh cycle having a digital temperature information generation function capable of controlling the cycle of the refresh signal for efficient and stable refresh operation, and generating digital temperature information and outputting it to the outside of the semiconductor integrated circuit. The object is to provide a signal generator.

A refresh cycle signal generator having a digital temperature information generation function according to the present invention comprises: a temperature information generator for generating temperature information using a first cycle signal and a second cycle signal; A refresh period signal generator for comparing the first period signal with the second period signal, selecting a signal having a short period among them, and outputting the selected signal as a refresh period signal; And an operation timing controller configured to operate the temperature information generator and the refresh cycle signal generator to match a predetermined timing.

A refresh cycle signal generator having a digital temperature information generation function according to the present invention comprises: a first cycle signal generator for generating a first cycle signal whose cycle varies according to temperature; A second periodic signal generator for generating a second periodic signal having a constant period regardless of temperature; A divider which divides the first period signal and the second period signal at a plurality of predetermined division ratios and outputs first to fourth division period signals; A temperature information generator configured to generate temperature information by using the first frequency division signal and the second frequency division signal; A refresh period signal generator which selects a signal having a short period from among the third division period signal and the fourth division period signal and outputs it as a refresh period signal; And an operation timing controller for operating the temperature information generator and the refresh cycle signal generator at different timings.

The refresh cycle signal generator having the digital temperature information generating function according to the present invention has the following effects.

First, since digital temperature information can be generated by itself and output in a format that can be used externally, it is possible to rapidly respond to technological changes related to semiconductor integrated circuits and to expand the scope of use of semiconductor integrated circuits. In addition, the circuit configuration inside the device can prevent the generation of wrong temperature information, thereby improving the reliability of the temperature information, and minimize the current consumption by ensuring that the temperature information decoding operation is performed for a minimum time.

Second, the period can be varied according to the temperature condition, and the cycle can be prevented from being excessively increased below a certain temperature, thereby enabling efficient and stable self-refreshing operation and further improving the reliability of the semiconductor integrated circuit. have.

Hereinafter, a preferred embodiment of a refresh cycle signal generator having a digital temperature information generation function according to the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a refresh cycle signal generator having a digital temperature information generating function according to the present invention.

As shown in FIG. 2, the refresh cycle signal generator having the digital temperature information generating function according to the present invention includes a first cycle signal generator 100, a second cycle signal generator 300, and a divider 400. And a temperature information generator 500, a refresh cycle signal generator 600, and an operation timing controller 700.

The first periodic signal generator 100 receives a first reset signal RST, an enable signal LTCSR_EN, and an operation section signal SERF_TDET, and receives a first periodic signal OSC1 whose period varies depending on temperature. Configured to occur. The first periodic signal generator 100 may be configured as a TCSR oscillator (Temperature Compensated Self Refresh Oscillator).

The second periodic signal generator 300 is configured to receive the first reset signal RST and the operation section signal SERF_TDET and generate a second periodic signal OSC2 having a constant period regardless of temperature. . The second periodic signal generator 300 may be configured as an extended mode register set (EMRS) oscillator.

The division unit 400 divides the first period signal OSC1 and the second period signal OSC2 into a plurality of preset division ratios (for example, two divisions, four divisions, eight divisions, ..., 4096 divisions). Is divided into a division ratio selected from the plurality of to output the first to fifth division period signal (DIV1 ~ DIV5). The first division period signal DIV1 is generated by dividing the first period signal OSC1 and may have, for example, a period of 40 ms. The second divided period signal DIV2 is generated by dividing the second period signal OSC2, and may have a period of 160 ms, for example. The third divided period signal DIV3 is generated by dividing the first period signal OSC1 and may have, for example, a period of 20 ms. The fourth divided period signal DIV4 is generated by dividing the second period signal OSC2 and may have, for example, a period of 80 ms. The fifth divided period signal DIV5 may be generated by dividing the second divided signal OSC2 or the fourth divided period signal DIV4, and may have a period of 320 ms, for example.

3 is a block diagram illustrating a configuration of the temperature information generator of FIG. 2.

As shown in FIG. 3, the temperature information generator 500 includes a multi-division signal generator 510, an output controller 520, a divided signal latch unit 530, a first decoder 540, and a second decoder. 550 and a temperature code latch portion 560.

The multiple divided signal generator 510 generates temperature information by latching and decoding the multiple divided signals S1 to S64 multi-divided with the second periodic signal OSC2 according to the transition timing of the first periodic signal OSC1. It is configured to.

The multiple frequency division generator 510 includes a plurality of frequency division units 511 that receive the second period signal OSC2 and sequentially divide and output the second frequency signal OSC2 at a predetermined division ratio X2. The plurality of dividers 511 may be configured in the same manner.

The output controller 520 may generate a first transfer control signal according to the first divided cycle signal DIV1, the second divided cycle signal DIV2, the power up signal PWRUP, and the second reset signal TI_RST. A1, A1B and second transfer control signals A3, A3B.

The divided signal latch unit 530 is configured to latch the multiple divided signals S1 to S64 according to the first transfer control signals A1 and A1B. The divided signal latch unit 530 receives the first transfer control signals A1 and A1B in common and receives a plurality of divided signals S1 to S64 output from the plurality of dividers 511. One latch circuit portion 531 is provided. The plurality of first latch circuits 531 may be configured in the same manner.

The first decoder 540 is configured to decode the multiple divided signals S1 to S64 latched in the divided signal latch unit into preliminary codes Temp100 to Temp55L of a digital type defining temperature.

The second decoder 550 is configured to decode and output the preliminary codes Temp100 to Temp55L into three-bit temperature codes DTI0 to DTI2 that conform to the semiconductor memory standard, that is, the digital format according to the JEDEC standard.

The temperature code latch unit 560 is configured to latch the temperature codes DTI0 to DTI2 according to the second transfer control signals A3 and A3B and output them to the pads DQ8 to DQ10. The temperature code latch unit 560 includes a plurality of second latch circuit units 561 that receive the second transfer control signals A3 and A3B in common and receive the temperature codes DTI0 to DTI2. The plurality of second latch circuit units 561 may be configured in the same manner.

4 is a circuit diagram of an output control unit of FIG. 3.

As illustrated in FIG. 4, the output control unit 520 includes a temperature sensing section signal generator 521, a first transfer control signal generator 522, and a second transfer control signal generator 523.

The temperature sensing section signal generator 521 may sense the temperature sensing section according to the first division period signal DIV1, the second division period signal DIV2, a power up signal PWRUP, and a second reset signal TI_RST. And generate signal A.

The temperature sensing section signal generator 521 includes a plurality of inverters IVI to IV3, a plurality of transistors M1 to M4, and a latch 521-1. The transistor M1 is configured to activate the temperature sensing section signal A to a high level in response to the second reset signal TI_RST. The inverter IV1 and the transistor M2 are configured to initialize the temperature sensing section signal A to a low level in response to a power up signal PWRUP. The inverter IV2 and the transistor M3 are configured to deactivate the temperature sensing period signal A in response to a first division period signal DIV1. The inverter IV3 and the transistor M4 are configured to deactivate the temperature sensing section signal A in response to the second division period signal DIV2. The latch 521-1 is configured to be commonly connected to drains of the plurality of transistors M1 to M4 to maintain the level of the temperature sensing section signal A.

The temperature sensing period signal generator 521 may operate with only one first division period signal DIV1 without the second division period signal DIV2. The reason why the second divided period signal DIV2 is additionally used is as follows. When using the first division period signal DIV1 in which the first period signal OSC1 is divided as a reference for determining a self refresh period, the first period signal OSC1 is below a specific temperature (for example, 37 ° C.). ) May increase to infinity, resulting in a refresh failure. Accordingly, in order to prepare for the case where the temperature is lower than 37 ° C, a cold stopper function is implemented by adding a circuit configuration that receives the second division period signal DIV2 in which the second period signal OSC2 is divided. In addition, the reason why the first division period signal DIV1 in which the first period signal OSC1 is divided and the second division period signal DIV2 in which the second period signal OSC2 is divided is used. This is because performance is improved.

The first transfer control signal generator 522 is configured to generate the first transfer control signals A1 and A1B according to the temperature sensing interval signal A.

The first transfer control signal generator 522 includes a pulse generation circuit including a plurality of inverters IV6 to IV8, a delay element DLY1, and a noah gate NR1, so that the temperature sensing section signal A is It is configured to generate the first transfer control signals A1 and A1B having a pulse width corresponding to the delay time of the delay element DLY1 at the time of deactivation.

The second transfer control signal generator 523 is configured to generate the second transfer control signals A3 and A3B according to the temperature sensing section signal A and the delayed temperature sensing section signal A_D.

The second transfer control signal generator 523 includes a delay element DLY2, a NOR gate NR2, and a plurality of inverters IV9 and IV10, and the temperature sensing section signal A and the delayed temperature sensing section signal ( And A_D) to generate the second transfer control signals A3 and A3B.

FIG. 5 is a circuit diagram of the first latch circuit of FIG. 3.

As illustrated in FIG. 5, the first latch circuit unit 531 includes a plurality of tree state inverters TIV11 and TIV12 and an inverter IV11. The tree state inverter TIV12 and the inverter IV11 form a latch structure. The tree state inverter TIV11 is configured to pass the multiple frequency division signal S1 in accordance with the first transfer control signals A1 and A1B. The tree state inverter TIV12 determines whether to operate the latch according to the first transfer control signals A1 and A1B.

6 is a circuit diagram of a second latch circuit of FIG. 3.

As illustrated in FIG. 6, the second latch circuit unit 561 includes a plurality of tree state inverters TIV21 and TIV22 and an inverter IV21. The tree state inverter TIV22 and the inverter IV21 form a latch structure. The tree state inverter TIV21 is configured to pass the temperature code DTI0 according to the second transfer control signals A3 and A3B. The tree state inverter TIV22 determines whether the latch is operated according to the second transfer control signals A3 and A3B.

FIG. 7 is a block diagram illustrating a configuration of the refresh signal generator of FIG. 2.

The refresh period signal generator 600 selects and refreshes the third division period signal DIV3 when the period of the third division period signal DIV3 is not longer than the period of the fourth division period signal DIV4. And output as the periodic signal PSRF.

As illustrated in FIG. 7, the refresh cycle signal generator 600 includes a cycle comparator 610 and a cycle signal selector 630.

The period comparator 610 compares the pulse generation timing of the third divided period signal DIV3 and the fourth divided period signal DIV4 to compare the third divided period signal DIV3 with the fourth divided period signal. And outputs control signals COLD_EN and COLD_ENB for selecting one of the (DIV4).

The period comparator 610 includes a first logic circuit 611 and a second logic circuit 612.

8 is a circuit diagram of a period comparator of FIG. 7.

As illustrated in FIG. 8, the first logic circuit unit 611 initializes the comparison signals C and D according to the first reset signal RST, and has a predetermined time difference. And the level of the comparison signals C and D in response to the fourth division period signal DIV4.

The first logic circuit unit 611 may include first to third inverters IV31 to IV33, first and second delay elements DLY31 and DLY32, first to third transistors M31 to M33, and a latch 611. -1). The first delay element DLY31 is configured to receive the first reset signal RST. The first transistor M31 is configured to have a source connected to the ground terminal VSS and to receive an output of the first delay element DLY31 from a gate. The first inverter IV31 is configured to receive the third division period signal DIV3. The second transistor M32 is configured such that a source is connected to a power supply terminal VPERI and receives an output of the first inverter IV31 at a gate thereof. The second inverter IV32 is configured to receive the fourth division period signal DIV4. The second delay element DLY32 is configured to receive an output of the second inverter IV32. The third transistor M33 is configured to have a source connected to the power supply terminal VPERI and to receive an output of the second delay element DLY32 from a gate. The drains of the first to third transistors M31 to M33 are commonly connected. The latch 611-1 is configured such that an input terminal is connected to a drain of the third transistor M33. The third inverter IV33 is configured such that an input terminal is connected to an output terminal of the latch 611-1. The delay time of the first delay element DLY31 and the delay time of the second delay element DLY32 may be set to be the same.

As illustrated in FIG. 8, the second logic circuit unit 612 corresponds to the pre-control signal COLD_EN_PRE and the fourth division period signal DIV4 having a level corresponding to the first reset signal RST. And output one of the pre-control signals COLD_EN_PRE having a level as the control signals COLD_EN and COLD_ENB according to the transition timing of the comparison signals C and D.

The second logic circuit unit 612 includes fourth and fifth inverters IV34 and IV35, fourth and fifth transistors M34 and M35, second to fourth latches 621 to 623, and first and second electrodes. Three state inverters TSIV31 and TSIV32 are provided. The fourth transistor M34 is configured to have a source connected to the ground terminal VSS and to receive the first reset signal RST to a gate thereof. The fourth inverter IV34 is configured to receive the fourth division period signal DIV4. The fifth transistor M35 has a source connected to a power supply terminal VPERI and configured to receive an output of the fourth inverter IV34 from a gate. The first latch 621 is configured such that an input terminal is connected to drains of the fourth and fifth transistors M34 and M35. The first tree state inverter TSIV31 is configured such that an input terminal is connected to an output terminal of the first latch 621 and receives the comparison signals D and C from a control terminal. The second latch 622 is configured such that an input terminal is connected to an output terminal of the first tree state inverter TSIV31. The second tree state inverter TSIV32 is configured such that an input terminal is connected to an output terminal of the second latch 622 and receives the comparison signals C and D from a control terminal. The third latch 623 is configured such that an input terminal is connected to an output terminal of the second tree state inverter TSIV32. The fifth inverter IV35 is configured such that an input terminal is connected to an output terminal of the third latch 623.

FIG. 9 is a circuit diagram of the periodic signal selector of FIG. 7.

The periodic signal selector 630 selects one of the third divided cycle signal DIV3 and the fourth divided cycle signal DIV4 according to the control signals COLD_EN and COLD_ENB to refresh the cycle signal PSRF. It is configured to output as.

As illustrated in FIG. 9, the periodic signal selector 630 includes third and fourth tree state inverters TSIV33 and TSIV34. The third tree state inverter TSIV33 is configured to receive the fourth division period signal DIV4 at an input terminal and to receive the control signals COLD_ENB and COLD_EN at a control terminal. The fourth tree state inverter TSIV34 receives the third frequency division period signal DIV3 at an input terminal, receives the control signals COLD_EN and COLD_ENB at a control terminal, and an output terminal of the fourth tree state inverter TSIV33. It is configured to be connected in common with the output terminal of.

10 is a circuit diagram of an operation timing controller of FIG. 2.

The operation timing controller 700 may generate timing signals, that is, a first reset signal RST according to a power-up signal PWRUP, a self refresh signal SREF, a fifth division period signal DIV5 and a refresh period signal PSRF. ), The second reset signal TI_RST, the enable signal LTCSR_EN, and the operation section signal SERF_TDET.

As shown in FIG. 10, the operation timing controller 700 includes a shifter 710 and a timing signal generator 720.

The shifter 710 is configured to shift the refresh period signal PSRF by a different time to generate the first shift signal PSRF_6 and the second shift signal PSRF_10.

The timing signal generator 720 is configured to generate the first signal according to the power-up signal PWRUP, the fifth division period signal DIV5, the self refresh signal SREF, the first shift signal PSRF_6, and the second shift signal PSRF_10. And a first reset signal RST, a second reset signal TI_RST, an enable signal LTCSR_EN, and an operation section signal SERF_TDET.

The timing signal generator 720 includes first to tenth inverters IV41 to IV50, NAND gates ND41, first to sixth NOR gates NR41 to NR46, a rising pulse generator RPG, and a falling pulse generator. (FPG) and first to fourth transistors M41 to M44. The rising pulse generator (RPG) is configured to detect the rising edge of the input signal to generate a pulse having a predetermined width. The falling pulse generator FPG is configured to detect a falling edge of the input signal and generate a pulse having a predetermined width.

The operation section signal SERF_TDET is used as a signal defining a temperature detection section. The operation section signal SERF_TDET has an activation section identical to the activation section of the self-refresh signal SREF or corresponds to a section in which the second shift signal PSRF_10 is generated from the time when the power-up signal PWRUP is generated. It is created to have an activation interval. The activation section of the operation section signal SERF_TDET corresponds to a section of a constant multiple (for example, 9 times) of the period of the refresh cycle signal PSRF.

The enable signal LTCSR_EN is a signal used to initialize a reference generation block inside the first periodic signal generator 100 and is generated in a pulse form. The reference generation block is turned off to reduce current and is initialized by the enable signal LTCSR_EN to start an operation. The enable signal LTCSR_EN is generated at the start of activation of the operation section signal SERF_TDET.

The first reset signal RST is a signal used to initialize the first periodic signal generator 100, the second periodic signal generator 300, the divider 400, and the refresh periodic signal generator 600. to be. The first reset signal RST is a pulse signal that is generated every time when the power-up signal PWRUP is generated, when the fifth frequency division signal DIV5 is generated, or when the first shift signal PSRF_6 is generated.

The second reset signal TI_RST is a signal used to initialize the temperature information generator 500. The second reset signal TI_RST is a pulse signal generated according to the first shift signal PSRF_6. The reason for generating the second reset signal TI_RST according to the first shift signal PSRF_6 may be due to the start of the temperature detection section, that is, the activation time of the operation section signal SERF_TDET. This is because the first reference signal OSC1 is abnormal because the reference generation block of the first reference block is not stably initialized. Accordingly, the temperature information generator 500 starts the operation after the first shift signal PSRF_6 is generated to stabilize the first periodic signal OSC1.

The operation timing controller 700 has a circuit configuration such that the operation section signal SERF_TDET, the enable signal LTCSR_EN, the first reset signal RST, and the second reset signal TI_RST are generated in accordance with the above-described timing.

Hereinafter, the digital temperature information generating method of the refresh cycle signal generator having the digital temperature information generating function according to the present invention will be described.

FIG. 11 is a graph comparing periods of a first periodic signal and a second periodic signal according to temperature, and FIG. 12 is a diagram illustrating a method of decoding a temperature code according to the present invention.

First, the digital temperature information generation principle of the present invention will be described.

Since the period of the first periodic signal OSC1 is different for each temperature, a pulse generation timing is also different. FIG. 11 illustrates a timing of generating a pulse of the first period signal OSC1 with multiple division signals S1 to S64 dividing the second period signal OSC2 for each temperature section. Since the multiple divided signals S1 to S64 have a constant period regardless of temperature, the multiple divided signals S1 to S64 are latched at the pulse generation timing of the first periodic signal OSC1 to read the value. It will have the same value as The present invention latches the multiple frequency division signals S1 to S64 at the timing of the pulse generation of the first frequency division signal DIV1 in which the first period signal OSC1 is divided, and decodes the latched value. As shown in FIG. 12, the digital temperature information is output as digital temperature information conforming to the JEDEC standard. In FIG. 12, the temperature range is not a JEDEC standard, and shows an example as a value that can be arbitrarily set by the manufacturer.

FIG. 13 is a timing diagram for describing an operation of the output controller of FIG. 3.

When the first reset signal RST is generated, the first periodic signal generator 100 of FIG. 2 operates to output the first periodic signal OSC1, and the second periodic signal generator 300 operates to generate the second. The periodic signal OSC2 is output.

When the first reset signal RST is generated, the division unit 400 divides the first period signal OSC1 and the second period signal OSC2 to generate a third division period signal DIV3 and a fourth division period. Output the signal DIV4.

The temperature sensing section signal generator 521 of FIG. 4 generates the temperature sensing section signal A according to the power-up signal PWRUP generated during the initial operation of the semiconductor integrated circuit before the second reset signal TI_RST is generated. Reset to low level.

During the period in which the temperature sensing section signal A is initialized to a low level, the first transmission control signal generator 522 of FIG. 4 generates a first transmission control signal A1 = low level, A1B = high level, The second transfer control signal generator 522 generates a second transfer control signal A3 = low level, A3B = high level.

In response to the first transfer control signal A1 = low level and A1B = high level, the first latch circuit unit 531 of FIG. 5 is cut off to receive the multiple division signals S1 to S64. While the input of the first latch circuit portion 531 is blocked, the latches IV11 and TIV12 continue to operate to maintain the previous output signal level.

According to the second transfer control signal A3 = low level, A3B = high level, the second latch circuit unit 561 of FIG. 6 receives the temperature codes DTI0 to DTI2 output from the second decoder 550 of FIG. 3. The latches are output to the pads DQ8 to DQ10.

As the second reset signal TI_RST is generated, each of the frequency divider 511 of the multiple frequency division signal generator 510 of FIG. 3 generates the multiple frequency division signals S1 to S64 using the second period signal OSC2. The operation is started.

As the second reset signal TI_RST is generated, the temperature sensing section signal generator 521 of FIG. 4 activates the temperature sensing section signal A to a high level.

The first transmission control signal generator 522 of FIG. 4 generates a first transmission control signal A1 = low level, A1B = high level while the temperature sensing section signal A is activated to a high level. The second transfer control signal generator 522 generates a second transfer control signal A3 = high level, A3B = low level.

According to the first transfer control signal A1 = low level, A1B = high level, the first latch circuit unit 531 of FIG. 5 is continuously blocked so that the multiple division signals S1 to S64 are not received. While the input of the first latch circuit portion 531 is blocked, the latches IV11 and TIV12 continue to operate to maintain the previous output signal level.

According to the second transfer control signal (A3 = high level, A3B = low level), the second latch circuit unit 561 of FIG. 6 is blocked from input and currently outputs the temperature codes DTI0 to DTI2 output from the second decoder 550. ) Is not input, and the operation of the latches IV21 and TIV22 is also stopped.

After the operation of generating the first division period signal DIV1 and the second division period signal DIV2 starts, the first first division period signal DIV1 pulse or the first second division period signal DIV2 pulse is generated. Accordingly, the temperature sensing section signal generator 521 of FIG. 4 deactivates the temperature sensing section signal A to a low level.

When the temperature sensing section signal A is deactivated to a low level, the first transfer control signal generator 522 of FIG. 4 may have the first transfer control signals A1 and A1B having a pulse width corresponding to the delay element DLY1. The second transfer control signal generator 522 generates a second transfer control signal A3 = low level and A3B = high level at a timing at which the delayed temperature sensing interval signal A_D is inactivated.

During the pulse width section of the first transmission control signals A1 and A1B having the pulse width corresponding to the delay element DLY1, the first latch circuit unit 531 of FIG. 5 receives the multiple division signals S1 to S64. Output to the first decoder 540 of FIG. After the input of the first latch circuit unit 531 is cut off, the latches IV11 and TIV12 of FIG. 5 operate to maintain the previous output signal level.

The first decoder 540 of FIG. 3 decodes the multiple divided signals S1 to S64 and outputs the preliminary codes Temp100 to Temp55L. The preliminary codes Temp100 to Temp55L decode only the codes of the temperature range corresponding to the values of the multiple frequency division signals S1 to S64 to a high level. For example, the multi-dividing signal (S1 ~ S64) value is X / X / X / L / L / L / L, X / X / L / H / L / L / L or L / L / H / H If one of / L / L / L, the temperature is more than 100 ℃ decode only Temp100 of the preliminary code (Temp100 ~ Temp55L) to a high level and the rest of the value to a low level. Among the values of the multiple divided signals S1 to S64, X means don't care, L means low level, and H means high level.

The second decoder 550 of FIG. 3 decodes the preliminary codes Temp100 to Temp55L into temperature codes DTI0 to DTI2 so as to conform to the JEDEC standard. As shown in FIG. 12, if only Temp85 is decoded at a high level among the preliminary codes Temp100 to Temp55L, the temperature codes DTI0 to DTI2 are decoded as '101'. As another example, if only Temp75 of the preliminary codes Temp100 to Temp55L is decoded to a high level, the temperature codes DTI0 to DTI2 are decoded to '001'.

While the first latch circuit unit 531 of FIG. 5 receives the multiple division signals S1 to S64, that is, while the level of the first transfer control signal A1 = high level and A1B = low level is maintained, FIG. The decoding operation is performed through the first decoder 540 and the second decoder 550 of 3, and the temperature codes DTI0 to DTI2 are output accordingly.

As the second transfer control signal (A3 = low level, A3B = high level) is generated, the second latch circuit 561 of FIG. 6 outputs the temperature codes DTI0 to DTI2 output from the second decoder 550 of FIG. 3. ) Is output to the pads DQ8 to DQ10. The input and output level transitions of the first decoder 540 and the second decoder 550 of FIG. 3 do not occur during the period in which the input of the first latch circuit 531 of FIG. 5 is blocked, thereby minimizing current consumption. can do.

14 and 15 are waveform diagrams showing the results of the temperature code decoding simulation;

The actual simulation results at 100 ° C. are shown in FIG. 14. After the second reset signal TI_RST is activated, the value of latching the multiple division signals S1 to S64 at the time when the first division period signal DIV1 is pulsed is L / L / H / H / L. It is / L / L, it can be seen that the same as the value of the multi-dividing signal (S1 ~ S64) defined in the 100 ℃ temperature section of FIG.

And the simulation result at 70 degreeC temperature is shown in FIG. After the second reset signal TI_RST is activated, the value of latching the multiple division signals S1 to S64 at the time when the first division period signal DIV1 is pulsed is L / H / L / H / H. It is / L / L, it can be seen that it corresponds to the X / X / X / H / H / L / L of the multi-dividing signal (S1 ~ S64) value defined in the temperature range of 55 ℃ or higher of FIG.

When the temperature code DTI0 to DTI2 is output to the outside of the semiconductor integrated circuit as digital temperature information through the pads DQ8 to DQ10, a memory controller, for example, a GPU (Graphic Processing Unit) may integrate the digital temperature information into the semiconductor integrated circuit. It can be used to set the auto refresh rate of the circuit.

According to the present invention, the input of the first and second decoders 540 and 550 is blocked by blocking the input of the divided signal latching unit 530 of FIG. 3 during the temperature sensing section, that is, the temperature sensing section signal A is activated. The first and second decoders 540 and 550 are operated by opening the input of the divided signal latch unit 530 only for a predetermined time after the temperature sensing is completed and preventing the level from being shifted. In addition, the input of the temperature code latch unit 560 of FIG. In this way, noise components such as glitches due to instantaneous transitions of the input signal are included in the digital temperature information generation process so that incorrect digital temperature information is not output.

16 is a temperature / cycle graph of a self refresh signal according to the present invention.

Hereinafter, a method of generating a refresh cycle signal of a refresh cycle signal generator having a digital temperature information generation function according to the present invention will be described.

The operating mode of the embodiment of the present invention is such that the period of the refresh period signal PSRF is too high at a specific temperature, for example, 37 ° C. or less (commonly referred to as room temperature or cold temperature in semiconductor circuit technology). It is a priority to prevent the elongation and to change the period of the refresh cycle signal PSRF for efficient self refresh operation at a temperature of 38 ° C. or higher.

First, the operation of the present invention when the temperature is higher than 37 ° C., for example, at 90 ° C., that is, commonly referred to as hot temperature in semiconductor circuit technology, will be described.

When the first reset signal RST is generated, the first logic circuit 611 of FIG. 8 outputs the comparison signals C and D at a high level and a low level, respectively. The second logic circuit unit 612 outputs the pre-control signal COLD_EN_PRE at a low level as the first reset signal RST is generated. Since the comparison signals C and D are high and low, respectively, the pre-control signal COLD_EN_PRE having the low level passes through the first tree state inverter TSIV31 and is latched in the second latch 622.

Since the current temperature is 90 ° C., as shown in FIG. 16, the period of the third division period signal DIV3 is shorter than the period of the fourth division period signal DIV4. That is, the pulse of the third division period signal DIV3 is generated before the fourth division period signal DIV4.

Therefore, after the first reset signal RST is generated, the second transistor M32 of the first logic circuit unit 611 is turned on so that the comparison signals C and D transition to the low level and the high level, respectively. .

Since the comparison signals C and D transition to the low level and the high level, respectively, the pre-control signal COLD_EN_PRE of the second logic circuit unit 612 passes through the second tree state inverter TSIV32 to form a third latch 623. ) And the control signals COLD_EN and COLD_ENB are output at low and high levels, respectively.

Since the control signals COLD_EN and COLD_ENB are output at a low level and a high level, respectively, the periodic signal selector 630 of FIG. 9 passes the third divided period signal DIV3 and outputs the refresh period signal PSRF. .

On the other hand, the operation of the present invention in the case where the temperature is a cold temperature condition lower than 37 ° C, for example, 30 ° C will be described.

When the first reset signal RST is generated, the first logic circuit 611 of FIG. 8 outputs the comparison signals C and D at a high level and a low level, respectively.

As the current temperature is 30 ° C., as shown in FIG. 16, the period of the fourth division period signal DIV4 is shorter than the period of the third division period signal DIV3. That is, the pulse of the fourth division period signal DIV4 is generated before the third division period signal DIV3.

Accordingly, the fifth transistor M35 of the second logic circuit unit 612 is turned on so that the pre-control signal COLD_EN_PRE transitions to a high level. Since the comparison signals C and D are at the high level and the low level, respectively, the pre-control signal COLD_EN_PRE having the high level passes through the first tree state inverter TSIV31 and is latched in the second latch 622.

The pre-control signal COLD_EN_PRE transitions to a high level, and after the delay time of the second delay element DLY32 of the first logic circuit unit 611 passes, the third transistor M33 is turned on so that the comparison signal C, D) is transitioned to the low level and the high level, respectively.

Since the comparison signals C and D transition to the low level and the high level, respectively, the high level pre-control signal COLD_EN_PRE is passed through the second tree state inverter TSIV32 to be latched to the third latch 623 and controlled. The signals COLD_EN and COLD_ENB are output at high and low levels, respectively.

Since the control signals COLD_EN and COLD_ENB are output at a high level and a low level, respectively, the periodic signal selector 630 of FIG. 9 passes the fourth divided period signal DIV4 and outputs the refresh period signal PSRF. .

As shown in FIG. 16, the third division period signal DIV3 is divided into a high temperature condition (when the temperature is higher than 37 ° C.) and a low temperature condition (when the temperature is lower than 37 ° C.) based on a specific temperature (37 ° C.). And the fourth divided period signal DIV4 are output as the refresh period signal PSRF.

Therefore, the present invention enables efficient self-refresh operation by using the third frequency division signal DIV3 whose period varies with temperature in the high temperature condition as the refresh period signal PSRF, and has a fixed period in the low temperature condition. By using the four-division cycle signal DIV4 as the refresh cycle signal PSRF, the self-refresh cycle is prevented from becoming too long, thereby enabling stable self-refresh operation.

17 is a timing diagram of an output signal of the operation timing controller of FIG. 2 when the self refresh signal SREF is not activated, and FIG. 18 is a timing diagram of the operation timing controller of FIG. 2 when the self refresh signal SREF is activated. This is a timing chart of the output signal.

Hereinafter, a method of generating timing signals, that is, a first reset signal RST, a second reset signal TI_RST, an enable signal LTCSR_EN, and an operation interval signal SERF_TDET in the operation timing controller 700 according to the present invention. This is as follows.

First, when the self refresh signal SREF is not activated, as shown in FIG. 17, the activation period corresponding to the period in which the second shift signal PSRF_10 is generated from the time when the power-up signal PWRUP is generated is shown. The operation section signal SERF_TDET is generated.

An enable signal LTCSR_EN is generated at the start of activation of the operation section signal SERF_TDET.

The first reset signal RST is generated every time when the power-up signal PWRUP is generated, when the fifth frequency division signal DIV5 is generated, or when the first shift signal PSRF_6 is generated.

The second reset signal TI_RST is generated when the first shift signal PSRF_6 is generated.

Next, when the self-refresh signal SREF is activated after the temperature detection is started, as shown in FIG. 18, the operation section signal SERF_TDET is maintained in a pre-activated state.

An enable signal LTCSR_EN is generated at the start of activation of the self refresh signal SREF.

The first reset signal RST is generated every time the start of activation of the self-refresh signal SREF, the generation time of the fifth frequency division signal DIV5, or the generation time of the first shift signal PSRF_6.

The second reset signal TI_RST is generated when the first shift signal PSRF_6 is generated.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a temperature / cycle output graph of a self-refresh signal according to the prior art,

2 is a block diagram of a refresh cycle signal generator having a digital temperature information generating function according to the present invention;

3 is a block diagram illustrating a configuration of a temperature information generation unit of FIG. 2;

4 is a circuit diagram of an output control unit of FIG. 3;

5 is a circuit diagram of a first latch circuit of FIG. 3;

6 is a circuit diagram of a first latch circuit of FIG. 3;

7 is a block diagram illustrating a configuration of a refresh signal generation unit of FIG. 2;

8 is a circuit diagram of a period comparator of FIG. 7;

9 is a circuit diagram of a periodic signal selector of FIG. 7;

10 is a circuit diagram of an operation timing controller of FIG. 2;

11 is a graph comparing periods between a first period signal and a second period signal according to temperature;

12 is a view showing a temperature code decoding method according to the present invention;

FIG. 13 is a timing diagram for describing an operation of an output controller of FIG. 3.

14 and 15 are waveform diagrams showing the results of the temperature code decoding simulation;

16 is a temperature / period graph of a self refresh signal according to the present invention;

17 and 18 are timing diagrams of output signals of the operation timing controller of FIG. 2.

Claims (41)

A temperature information generator configured to generate temperature information using the first period signal and the second period signal; A refresh period signal generator for comparing the first period signal with the second period signal, selecting a signal having a short period among them, and outputting the selected signal as a refresh period signal; And An operation timing controller configured to operate the temperature information generator and the refresh cycle signal generator in accordance with a predetermined timing; The operation timing controller And a refresh temperature signal generation function configured to operate the refresh cycle signal generator and the temperature information generator with a predetermined time difference. The method of claim 1, The refresh cycle signal generator A period comparator configured to compare pulse generation timings of the first period signal and the second period signal to output a control signal for selecting one of the first period signal and the second period signal; and And a periodic signal selector configured to select and output one of the first periodic signal and the second periodic signal according to the control signal. The method of claim 2, The period comparison unit A first logic circuit unit configured to initialize a comparison signal according to a first reset signal and to shift a level of the comparison signal in response to the first period signal and the second period signal with a predetermined time difference, and Second logic configured to output one of a pre-control signal having a level corresponding to the first reset signal and a pre-control signal having a level corresponding to the second periodic signal as the control signal according to the transition timing of the comparison signal A refresh cycle signal generator having a digital temperature information generating function, comprising a circuit section. The method of claim 3, wherein The first logic circuit portion A first switching element configured to initialize the comparison signal in response to the first reset signal with a time difference by a first set time; A second switching element configured to transition a level of the initialized comparison signal in response to the first periodic signal, and And a third switching element configured to shift the level of the initialized comparison signal in response to the second periodic signal with a time difference by a second set time. Generation device. The method of claim 3, wherein The second logic circuit portion A first switching element configured to initialize the pre-control signal in response to the first reset signal, A second switching element configured to shift the level of the pre-control signal in response to the second periodic signal; A third switching element for passing the pre-control signal in response to the initialized comparison signal, and And a fourth switching element for passing the output of said third switching element and outputting it as said control signal when the level of said comparison signal changes. The method of claim 2, The periodic signal selector A first switching element configured to pass the second periodic signal in response to the control signal, and And a second switching element for passing the first periodic signal in response to the control signal. The method of claim 1, The temperature information generation unit An output control unit configured to generate a first transmission control signal and a second transmission control signal according to the pulse generation timing of the first periodic signal; A multi-division signal generator for generating a multi-division signal using the second periodic signal; A division signal latch unit for latching the multiple division signal according to the first transfer control signal; A decoding unit for decoding a multiple division signal latched by the division signal latch unit and outputting a temperature code; And And a temperature code latch unit for latching the temperature code according to the second transfer control signal. The method of claim 7, wherein The multi-division signal generator And a plurality of dividers which sequentially divide and output the second periodic signals at respective division ratios, wherein the refresh cycle signal generator has a digital temperature information generating function. The method of claim 8, And a division ratio of the plurality of frequency dividers is the same. The method of claim 7, wherein The output control unit Generating the first transfer control signal to allow the divided signal latch unit to receive the multi-divided signal for a first time from the end of the temperature sensing period; And generate the second transfer control signal to prevent the temperature code latch unit from receiving an output of the decoding unit for a second time elapsed from the start point of the temperature detection section to the end point of the temperature detection section. A refresh cycle signal generator having a digital temperature information generation function. The method of claim 10, The output control unit And a second temperature control signal for generating the second transmission control signal to allow the temperature code latch unit to receive the output of the decoding unit before a start point of the temperature sensing section. The method of claim 10, And wherein the second time is longer than the first time. The method of claim 7, wherein The output control unit A temperature sensing section signal generator configured to generate a temperature sensing section signal for defining a temperature sensing section using the first periodic signal, the second periodic signal, a power up signal, and a second reset signal; A first transfer control signal generator configured to generate the first transfer control signal using the temperature sensing interval signal, and And a second transmission control signal generator configured to generate the second transmission control signal by using the temperature sensing interval signal. The method of claim 13, The temperature sensing section signal generator Initialize the temperature sensing section signal in response to the power up signal, activate the temperature sensing section signal in response to the second reset signal, and deactivate the temperature sensing section signal in response to the first periodic signal. And a refresh cycle signal generator having a digital temperature information generating function. The method of claim 14, The temperature sensing section signal generator And the temperature sensing section signal is deactivated in response to the first periodic signal or the second periodic signal. The method of claim 13, The temperature sensing section signal generator A first switching element configured to transition the temperature sensing section signal to an initialization level in response to the power up signal; A second switching element configured to transition the temperature sensing interval signal to an activation level in response to the second reset signal; A third switching element configured to transition the temperature sensing interval signal to an inactive level in response to the first periodic signal, and And a fourth switching element configured to transition the temperature sensing section signal to the deactivation level in response to the second periodic signal. The method of claim 13, The first transfer control signal generator is And a pulse generating circuit for generating the first transfer control signal having a pulse width for a first time from the end of the temperature sensing section by using the temperature sensing section signal. Refresh cycle signal generator having a. The method of claim 13, The second transfer control signal generator And generating the second transfer control signal by combining the temperature sensing section signal and the signal delayed by the temperature sensing section signal by a second time period. The method of claim 7, wherein The divided signal latch unit Is configured to receive and output the multi-dispense signal when the first transfer control signal is activated; A refresh cycle signal generator having a digital temperature information generation function, characterized in that. The method of claim 7, wherein The divided signal latch unit A first switching element configured to receive the multiple divided signal in response to the first transfer control signal; And a latch for latching an output signal of the first switching element in response to the first transfer control signal. The method of claim 7, wherein The decoding unit A first decoder which decodes the multiple frequency division signal latched in the frequency division latch unit with a preliminary code defining a temperature; And a second decoder for decoding the preliminary code output from the first decoder into a temperature code conforming to a semiconductor memory standard. The method of claim 7, wherein The temperature code latch unit And the latching and outputting the temperature code when the second transfer control signal is activated, and when the second transfer control signal is inactivated, the latch operation is stopped while the input of the temperature code is blocked. A refresh cycle signal generator having a temperature information generating function. The method of claim 7, wherein The temperature code latch unit A first switching element receiving the temperature code in response to the second transfer control signal, And a latch for latching an output signal of the first switching element in response to the second transfer control signal. delete The method of claim 1, The operation timing controller And operating the refresh period signal generator and operating the temperature information generator after a set time. The method of claim 1, A first periodic signal generator which generates the first periodic signal whose period varies with temperature, A second periodic signal generator which generates the second periodic signal having a constant period irrespective of temperature, and And a dividing unit for dividing at least one of an output of the first periodic signal generator or an output of the second periodic signal generator. The method of claim 26, And the first periodic signal generator comprises a linear temperature compensated self refresh oscillator (LCTSR). The method of claim 26, And the second periodic signal generator comprises an extended mode register set (EMRS) oscillator. The method of claim 26, The dispensing part And a plurality of divided signals which divide the first period signal and the second period signal at different division ratios to the temperature information generator and the refresh period signal generator. Refresh cycle signal generator. The method of claim 26, The operation timing controller Simultaneously initialize the first periodic signal generator, the second periodic signal generator, the frequency divider, and the refresh periodic signal generator using a first reset signal, and use the second reset signal after a set time to reset the temperature information. And a refresh cycle signal generator having a digital temperature information generating function, configured to initialize the generator. The method of claim 30, The operation timing controller And generating a first reset signal and a second reset signal by using a power-up signal, a self refresh signal, and the refresh cycle signal. A first periodic signal generator for generating a first periodic signal whose period varies with temperature; A second periodic signal generator for generating a second periodic signal having a constant period regardless of temperature; A divider which divides the first period signal and the second period signal at a plurality of predetermined division ratios and outputs first to fourth division period signals; A temperature information generator configured to generate temperature information by using the first frequency division signal and the second frequency division signal; A refresh cycle signal generator for selecting a signal having a short cycle from among the third divided cycle signal and the fourth divided cycle signal and outputting the selected refresh cycle signal as a refresh cycle signal; And An operation timing controller configured to operate the temperature information generator and the refresh cycle signal generator at different timings; The operation timing controller And a digital temperature information generating function configured to simultaneously initialize the first periodic signal generator, the second periodic signal generator, the frequency divider, and the refresh period signal generator, and initialize the temperature information generator after a set time. Refresh cycle signal generator. The method of claim 32, The refresh cycle signal generator A period comparator configured to compare pulse generation timings of the third divided period signal and the fourth divided period signal to output a control signal for selecting one of the third divided period signal and the fourth divided period signal; and And a periodic signal selector configured to select and output one of the third divided cycle signal and the fourth divided cycle signal in accordance with the control signal. The method of claim 32, The temperature information generation unit An output control unit configured to generate a first transfer control signal and a second transfer control signal according to a pulse generation timing of the first division period signal; A multiple division signal generator for generating a multiple division signal using the second division period signal; A division signal latch unit for latching the multiple division signal according to the first transfer control signal; A decoding unit for decoding a multiple division signal latched by the division signal latch unit and outputting a temperature code; And And a temperature code latch unit for latching the temperature code according to the second transfer control signal. The method of claim 34, wherein The output control unit Generating the first transfer control signal to allow the divided signal latch unit to receive the multi-divided signal for a first time from the end of the temperature sensing period; Generating the second transfer control signal to prevent the temperature code latch unit from receiving an output of the decoding unit for a second time elapsed from the start point of the temperature detection section to the end point of the temperature detection section, And a second temperature control signal for generating the second transmission control signal to allow the temperature code latch unit to receive the output of the decoding unit before a start point of the temperature sensing section. The method of claim 34, wherein The divided signal latch unit Is configured to receive and output the multi-dispense signal when the first transfer control signal is activated; A refresh cycle signal generator having a digital temperature information generation function, characterized in that. The method of claim 34, wherein The decoding unit A first decoder which decodes the multiple frequency division signal latched in the frequency division latch unit with a preliminary code defining a temperature; And a second decoder for decoding the preliminary code output from the first decoder into a temperature code conforming to a semiconductor memory standard. The method of claim 34, wherein The temperature code latch unit And the latching and outputting the temperature code when the second transfer control signal is activated, and when the second transfer control signal is inactivated, the latch operation is stopped while the input of the temperature code is blocked. A refresh cycle signal generator having a temperature information generating function. The method of claim 32, And the first periodic signal generator comprises a linear temperature compensated self refresh oscillator (LCTSR). The method of claim 32, And the second periodic signal generator comprises an extended mode register set (EMRS) oscillator. delete

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