KR100997431B1 - Decoupling capacitor of semiconductor memory device and method for forming the same - Google Patents

Abstract

The present invention relates to a decoupling capacitor and a method of forming the semiconductor memory device, the lower electrode; An upper electrode formed on the lower electrode and spaced apart from each other by a predetermined interval, and at least a portion of the upper electrode overlapping the lower electrode; And a dielectric film patterned in an overlapping region between the lower electrode and the upper electrode, thereby providing a decoupling capacitor, which significantly reduces the leakage current of the decoupling capacitor.

Description

Decoupling Capacitor of Semiconductor Memory Device and Forming Method Thereof {DECOUPLING CAPACITOR OF SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly, to a decoupling capacitor and a method of forming the semiconductor memory device.

In general, a semiconductor memory device includes a large number of decoupling capacitors to prevent the influence of external noise flowing into a power source.

Conventionally, as a decoupling capacitor, as shown in FIG. 1A, a gate G is connected to a power supply voltage line, and a source S, a drain D, and a bulk B are commonly connected to a ground voltage line. MOS transistor type capacitors are mainly used.

At this time, the MOS transistor type capacitor, in theory, when the voltage Vgs level applied between the gate and the source is lower than the threshold voltage Vt level, the current is not turned on.

However, in an actual MOS transistor type capacitor, as shown in Fig. 1B, the leakage current I1 by the voltage Vgs between the gate and the source, the leakage current I2 by the voltage Vgd between the gate and the drain, and The leakage current I3 is generated by the voltage Vgb across the gate and bulk.

At this time, the leakage current I3 is not a problem because the amount is not large, but since the amount of leakage currents I1 and I2 is inversely proportional to the thickness of the gate oxide, a thinner gate oxide may cause a problem in terms of current consumption. have.

In other words, as the technology develops, many decoupling capacitors are used to improve performance due to power fluctuations. As the decoupling capacitors, MOS transistor type capacitors are conventionally used.

However, as the semiconductor memory device becomes faster and more highly integrated, the gate oxide becomes thinner, and the thin gate oxide causes the leakage current I1 due to the voltage Vgs between the gate and the source, and the voltage Vgd between the gate and the drain. Leakage current I2 may increase.

In particular, since the leakage current by the conventional decoupling capacitor occupies about 10% or more of the total leakage current of the semiconductor memory device, a problem that may be a big problem in a semiconductor memory device requiring low power operation such as mobile DRAM is required. have.

The present invention provides a decoupling capacitor of a semiconductor memory device capable of reducing leakage current.

The present invention provides a method of forming a decoupling capacitor of a semiconductor memory device capable of reducing leakage current.

In an embodiment, a decoupling capacitor of a semiconductor memory device may include a lower electrode; An upper electrode formed on the lower electrode and spaced apart from each other by a predetermined interval, and at least a portion of the upper electrode overlapping the lower electrode; And a dielectric film patterned in an overlapping region between the lower electrode and the upper electrode.

In the above configuration, the dielectric layer is preferably formed in a via structure between the upper electrode and the lower electrode.

In an overlapping region between the lower electrode and the upper electrode, an insulating film may be further included between the patterned dielectric layer.

In addition, it is preferable that a different voltage is applied to the upper electrode and the lower electrode so that a predetermined voltage difference is formed between the upper electrode and the lower electrode.

According to another aspect of the present invention, a decoupling capacitor of a semiconductor memory device may include a lower electrode having one or more recesses; A dielectric film formed on a surface of the recess of the lower electrode; And an upper electrode formed on the lower electrode to be spaced apart from each other by a predetermined interval and having irregularities in contact with the dielectric film.

In the above configuration, it is preferable that the lower electrode includes two or more recesses, and an insulating layer for insulating the lower electrode and the upper electrode is further included in the region between the recesses.

In addition, different levels of voltage may be applied to the upper electrode and the lower electrode to form a predetermined voltage difference between the upper electrode and the lower electrode.

According to one or more exemplary embodiments, a method of forming a decoupling capacitor of a semiconductor memory device includes: forming a lower electrode; Patterning an insulating film on the lower electrode; Forming a dielectric film between the patterned insulating film; And forming an upper electrode on the insulating film and the dielectric film.

In the method, the dielectric layer is preferably formed in a via structure between the upper electrode and the lower electrode.

The patterning of the insulating layer may include forming an insulating layer on the lower electrode; Forming a mask pattern having openings spaced apart from each other on the insulating layer; Etching the insulating layer using the mask pattern to form a plurality of holes; And removing the mask pattern.

In addition, the dielectric film is preferably formed in a plurality of holes of the insulating film.

According to another aspect of the present invention, a method of forming a decoupling capacitor of a semiconductor memory device includes: forming a lower electrode; Forming one or more recesses in the lower electrode; Forming a dielectric film on a recessed surface of the lower electrode; Forming an insulating film on a surface of the lower electrode except for the portion where the dielectric film is formed; And forming an upper electrode on the insulating film and the dielectric film.

In the method, forming a recess in the lower electrode may include forming a mask pattern having at least one opening on the lower electrode; Etching the lower electrode corresponding to the opening of the mask pattern to form the recessed portion; And removing the mask pattern.

The present invention provides an effect of significantly reducing the leakage current of the decoupling capacitor by providing a decoupling capacitor of a semiconductor memory device having a structure in which a dielectric film is interposed between two electrodes.

The present invention provides a method of forming a decoupling capacitor of a semiconductor memory device having a structure in which a dielectric film is interposed between two electrodes, thereby reducing the leakage current of the decoupling capacitor.

The present invention can effectively reduce the leakage current of the capacitor by providing a decoupling capacitor of a semiconductor memory device having a dielectric film interposed between two electrodes.

Specifically, the decoupling capacitor of the semiconductor memory device according to the present invention may be interposed between the lower electrode 10, the upper electrode 30, and the two electrodes 10 and 30, as shown in FIG. 2A. A dielectric film 20.

Here, the lower electrode 10 and the upper electrode 30 are disposed to be spaced apart from each other and at least some regions overlap with each other. The dielectric layer 20 is patterned in a region where the lower electrode 10 and the upper electrode 30 overlap.

Referring to FIG. 2B, the lower electrode 10 is formed, and the dielectric film 20 is formed on the lower electrode 10 in a pattern. The upper electrode 30 is formed on the dielectric layer 20. In this case, the dielectric film 20 may be formed in a via structure between the lower electrode 10 and the upper electrode 30.

In the above structure, the lower electrode 10 and the upper electrode 30 are electrically separated from each other. For this purpose, an insulating film 15 may be further formed between the dielectric layers 20. Here, the insulating film 15 is preferably made of an insulating material different from the dielectric film 20.

Referring to the process of forming the decoupling capacitor of the semiconductor memory device having the above structure, first, the lower electrode 10 is formed, and the insulating film 15 is formed on the lower electrode 10.

Then, a mask pattern (not shown) having openings spaced apart from each other is formed on the insulating layer 15, and portions corresponding to the openings in the insulating layer 15 are etched through the mask pattern to form holes. ) Is formed.

Thereafter, the mask pattern is removed, and a dielectric film 20 is formed in the hole. Then, the upper electrode 30 is formed on the insulating film 15 and the dielectric film 20.

The decoupling capacitor of the semiconductor memory device according to the embodiment of the present invention formed through the above process may be formed on the lower electrode 10, the upper electrode 30, and the dielectric film 20 having a via structure between the two electrodes 10 and 30. Charge or discharge voltage.

That is, when a predetermined potential difference occurs between the lower electrode 10 and the upper electrode 30 due to different voltages applied to the lower electrode 10 and the upper electrode 30, a capacitor is formed by the dielectric film 20.

As described above, the decoupling capacitor of the semiconductor memory device according to an exemplary embodiment of the present invention has a structure including two electrodes and a dielectric film interposed between the two electrodes, not the MOS capacitor structure.

Therefore, in the MOS capacitor structure, no leakage current is generated due to the voltage Vgs between the gate and the source in question, the voltage Vgd between the gate and the drain, and the voltage Vgb between the gate and the bulk, so that the current consumption is remarkable. There is an effect that can be reduced.

In addition, unlike the MOS capacitor structure, the decoupling capacitor of the semiconductor memory device according to an embodiment of the present invention may use a region where the two electrodes 10 and 30 cross each other, and thus, the density may be improved. have.

In another embodiment, the decoupling capacitor of the semiconductor memory device may have a structure as shown in FIGS. 3A and 3B.

First, referring to FIG. 3A, a decoupling capacitor of a semiconductor memory device according to another exemplary embodiment of the present invention may include a lower electrode 100, an upper electrode 300, and two electrodes 100 and 300, as in an exemplary embodiment. It may be configured to include a dielectric film 200 interposed therebetween.

Here, the lower electrode 100 has at least one recess, and the upper electrode 300 has at least one recess corresponding to the recess of the lower electrode 100. The dielectric film 200 is disposed at an interface between the recessed portion of the lower electrode 100 and the irregularities of the upper electrode 300.

Referring to FIG. 3B, the lower electrode 100 having one or more recesses is formed, and the dielectric film 200 is formed to contact the surface of the recesses. The upper electrode 300 is formed on the lower electrode 100 and the dielectric layer 200.

Here, the upper electrode 300 has a concave-convex structure in contact with the dielectric film 200. The lower electrode 100 and the upper electrode 300 are formed to be spaced apart from each other by a predetermined interval except for a portion where the dielectric film 200 is in contact with each other, and an insulating film 250 is preferably formed at the spaced portion for electrical separation.

Looking at the process of forming the decoupling capacitor of the semiconductor memory device according to another embodiment of the present invention having such a structure, first, the lower electrode 100 having a flat surface is formed.

One or more recesses are formed in the lower electrode 100, and a process of forming the recesses may be performed as follows, for example.

First, a mask pattern (not shown) having one or more openings is formed on the lower electrode 100. A portion of the lower electrode 100 corresponding to the opening of the mask pattern is etched to form the recessed portion. Then, the mask pattern is removed to form the lower electrode 100 having one or more recesses.

Thereafter, the dielectric film 200 is formed on the recessed surface of the lower electrode 100, and the insulating film 250 is formed on the lower electrode 100 and the dielectric film 200. In this case, the main portion of the lower electrode 100, that is, the insulating film 250 formed on the insulating film 250 is preferably removed through a mask pattern.

Then, the upper electrode 300 is formed on the insulating film 250 and the dielectric film 200. Here, the upper electrode 300 has an unevenness corresponding to the uneven portion of the lower electrode 100, and the unevenness is preferably formed in contact with the dielectric layer 200.

The decoupling capacitor of the semiconductor memory device according to another embodiment of the present invention formed through such a process has the same effect that no leakage current is generated as in the embodiment of the present invention.

In addition, since the step difference between the lower substrate 100 and the upper substrate 300 is large in the decoupling capacitor of the semiconductor memory device according to another exemplary embodiment, the decoupling capacitor capacity may be significantly increased.

1A and 1B show a conventional MOS transistor type decoupling capacitor.

2A and 2B are plan and side views illustrating a decoupling capacitor of a semiconductor memory device according to an embodiment of the present invention.

3A and 3B are plan and side views illustrating a decoupling capacitor of a semiconductor memory device according to another embodiment of the present invention.

Claims (13)

delete Lower electrode; An upper electrode formed on the lower electrode and spaced apart from each other by a predetermined interval, and at least a portion of the upper electrode overlapping the lower electrode; And And a dielectric layer having a via structure in an overlapping region between the lower electrode and the upper electrode. The method of claim 2, And an insulating layer disposed between the lower electrode and the upper electrode in an area around the dielectric layer to insulate the lower electrode and the upper electrode. The method of claim 2, A decoupling capacitor of a semiconductor memory device in which different voltages are applied to the upper electrode and the lower electrode to form a predetermined voltage difference between the upper electrode and the lower electrode. delete A lower electrode having two or more recesses; A dielectric film formed on a surface of the recess of the lower electrode; An upper electrode formed on the lower electrode and spaced apart from each other by a predetermined interval and having irregularities in contact with the dielectric film; And An insulating film insulating the lower electrode from the upper electrode in an area between the recesses A decoupling capacitor of a semiconductor memory device having a. The method of claim 6, A decoupling capacitor of a semiconductor memory device in which different voltages are applied to the upper electrode and the lower electrode to form a predetermined voltage difference between the upper electrode and the lower electrode. delete Forming a lower electrode; Patterning an insulating film on the lower electrode; Forming a dielectric film between the patterned insulating film; And Forming an upper electrode on the insulating film and the dielectric film; And the dielectric layer has a via structure between the upper electrode and the lower electrode. The method of claim 9, Patterning the insulating film, Forming an insulating film on the lower electrode; Forming a mask pattern having openings spaced apart from each other on the insulating layer; Etching the insulating layer using the mask pattern to form a plurality of holes; And Removing the mask pattern; and forming a decoupling capacitor of the semiconductor memory device. The method of claim 10, And the dielectric film is formed in a plurality of holes of the insulating film. Forming a lower electrode; Forming one or more recesses in the lower electrode; Forming a dielectric film on a recessed surface of the lower electrode; Forming an insulating film on a surface of the lower electrode except for the portion where the dielectric film is formed; And And forming an upper electrode on the insulating layer and the dielectric layer. 13. The method of claim 12, Forming a recess in the lower electrode, Forming a mask pattern having at least one opening on the lower electrode; Etching the lower electrode corresponding to the opening of the mask pattern to form the recessed portion; And Removing the mask pattern; and forming a decoupling capacitor of the semiconductor memory device.

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