KR100996150B1 - Align Plate and Electric Conduction Plate of Probe pin, method of manufacturing the Align Plate and Electric conduction Plate - Google Patents

Abstract

The present invention relates to a method for manufacturing a through-opening shape on a substrate used as an alignment plate and a conduction plate of a probe pin by etching at a single surface, and to a block, a block joint, and a joining, specifically, a first conduction plate and a second conduction Depositing a notched layer for vertical through opening on the bottom surface of the silicon substrate used as a plate, applying photoresist on the upper surface, patterning the through opening shape on the upper surface, etching the through opening at once on the upper surface by Deep RIE or Bosch process The step of proceeding, removing the photoresist used during patterning, cleaning the remaining organic matter, depositing an insulating film on the front and through-opening wall, filling the through-opening conductive material, overfilled conductive material Flattening and polishing, processing an antireflection film on an upper surface of the first conductive plate, and depositing an insulating film on the upper surface of the first conductive plate Step, adding a horizontal conducting wiring film to the second conducting plate, and manufacturing the first conducting plate and the second conducting plate bonding step. By etching through openings in one direction from the upper surface to the lower surface as described above, the steps of patterning and etching processes on the lower surface are reduced. Accordingly, the process progress step is reduced, thereby reducing the process cost and also causing stepping and notch phenomenon on the through opening wall. It is possible to improve the process yield.

Alignment plate, support plate, first conducting plate, second conducting plate, stepped part, notch part, notch prevention layer, antireflection film

Description

Align Plate and Electric Conduction Plate of Probe pin, method of manufacturing the Align Plate and Electric conduction Plate

The present invention relates to a manufacturing method on the alignment plate and the energizing plate for assembling the LCD panel inspection probe unit and the semiconductor chip inspection probe pin, and in detail, by arranging the probe pin at the designated position of the manufactured alignment plate or the energizing plate To assemble.

The probe pin of the probe card is assembled to a space transformer called a space transformer, or the probe pin is assembled to the alignment plate in which the through pin of the probe pin is formed on the silicon substrate, or the through hole is formed on the silicon substrate to fill the through hole with a conductive material. The probe pin is bonded to the conductive material on the plate and used as the probe head. The main heat exchanger plate and the sub heat exchanger plate, the first conduction plate and the second conduction plate are subjected to CVD process, lithography process, etching process, plating process, planarization process (CMP), separation and residue cleaning process, which are MEMS (Mirco Electric Mechanical System) processes. It is to make fine and uniform using.

The problem to be solved by the present invention is that the through-opening etching on the silicon substrate is slightly inclined due to the difference in the etching width of the upper surface and the etching width of the lower surface.

As shown in FIG. 1A, the bidirectional etching through-opening etching is performed by bidirectional etching in which the through opening is etched at a predetermined depth on the upper surface and then turned over and etched at a predetermined depth on the lower surface to reduce the difference in the etching width of the upper surface and the lower surface. There is a problem that the step 15 is generated at the intersection point at the time of etching on the over and under surface.

Another problem to be solved by the present invention is a problem of notch 18 generated at the end of etching when etching to the silicon substrate as shown in FIG.

Another problem to be solved by the present invention is that a leakage current is generated in the through opening wall of the silicon substrate and the outer side wall of the block unit.

Another problem of the present invention is to manufacture a current-carrying plate with a silicon substrate, which is difficult to realize a large size due to thermal deformation and shrinkage problems of a multilayer space transformer made of ceramic.

1.The silicon substrate is etched to a certain depth on the upper surface, flipped and etched to a certain depth on the lower surface to etch through openings in both directions, so that a step difference phenomenon 15 occurs in the through opening wall at the point where the upper surface and the lower surface intersect during etching. In addition, in order to solve the problem of notch phenomenon 18 occurring at the end of the through opening during etching, a notch prevention layer is deposited on the bottom surface of the silicon substrate for etching the through opening in one direction from the top surface to the bottom surface. The lower surface notched layer is etched through at once without the difference in the etching width between the start etching width of the upper surface and the last etching width of the lower surface, and the notch phenomenon generated at the end of the lower surface is not generated.

2. The problem that leakage current is generated in the through opening wall of the silicon substrate and the outer side wall of the block unit is to coat the insulating polymer.

3.Since the problem of heat deformation and shrinkage of ceramic multi-layered space transformers, it is difficult to realize a large size, and the conductive plate is manufactured by silicon substrate and the horizontal conduction is applied on the upper surface of the second conducting plate connected to the through hole of the first conducting plate. By attaching a wiring film and laminating the first conducting plate and the second conducting plate to each other, the manufacturing of the multilayer space transformer is simplified.

The present invention solves the notch problem caused by dry etching by depositing a notch prevention layer on the lower surface of the silicon substrate, and the through-opening wall step problem of the cross point generated in the bidirectional etching by etching the through opening in one direction from the upper surface to the end of the lower surface. It also eliminates the two-way patterning and etching steps, thereby reducing process steps and costs and improving process yield.

Embodiments of the present invention and the specific effects obtained from the method of manufacturing the main heat exchanger plate 10 and the sub heat exchanger plate 30, the first current transfer plate 20, and the second current transfer plate 25 are described in detail with reference to the accompanying drawings. It is as follows.

Example 1

As shown in FIG. 2, the main heat alignment plate 10 made of a silicon substrate is etched through the opening 13 without any difference in the etching width from the upper surface to the lower surface in one direction from the top surface to the bottom surface. When the notch prevention layer 55 is deposited on the lower surface of the silicon substrate for one-way etching at a time, the through opening wall from the upper surface to the lower surface etches the through opening 13 without notching and spreading at the end of the through opening of the lower surface. To do.

In addition, the sub-arrangement plate 30 is bonded to the main alignment plate 10 to increase the support strength of the main alignment plate 10. It is.

5A to 5M are flowcharts illustrating the embodiment of the main alignment plate and the sub alignment plate in detail.

As shown in FIG. 5A, the manufacturing of the main heating plate uses a MEMS process, and is made of a single-crystal silicon substrate having a good etching property, and the silicon substrate is polished and cleaned with flatness on the upper and lower surfaces to improve adhesion and coating performance. do.

The silicon substrate is used as the main alignment plate to proceed to the next step.

A photoresist is uniformly and evenly coated on the upper surface of the alignment plate as shown in FIG. 5B using a spin coater.

As shown in FIG. 5C, a photoresist mask having a through opening pattern is prepared, and the desired through opening shape is patterned by exposing and developing the photoresist mask on the upper surface of the columnar heat treatment plate to which the photoresist is applied.

As shown in FIG. 5D, the notch preventing layer is deposited on the lower surface of the main heat alignment plate by sputtering.

The notch prevention layer is any one of Cu, Al, Cr, Ti / Au, and all of the metal for the notch prevention layer can be used.

As shown in FIG. 5E, the through opening is performed by the Deep RIE on the upper surface of the alignment plate.

As shown in FIG. 5F, the notch prevention layer is separated on the lower surface of the alignment plate and the photoresist remaining on the upper surface is removed.

As shown in FIG. 5G, an antireflection image is formed on the upper surface of the alignment plate and the front surface is cleaned.

The anti-reflection image may be processed by selecting any one of sandblast processing, texture processing, non-conductive polymer resin deposition, and laser processing. The texture processing is a chemical liquid mixed with alkali and acid.

As shown in FIG. 5H, an insulating film is deposited on the through opening wall formed on the alignment plate and the entire surface of the alignment column.

The insulating film of the main heat exchanger plate is formed by depositing any one of an oxide film, a nitride film, and a TEOS film.

As shown in FIG. 5I, a recognition code for starting and inserting a probe pin into a through opening at one end of an upper surface of the alignment plate is formed on an upper surface of a dirt unit, a block unit, or a single plate unit.

The recognition code is formed of a code or a groove that can recognize the start area.

As shown in FIG. 5J, the front surface of the alignment plate in which the through opening and the recognition code are formed is cleaned.

Next, the sub-arrangement plate process is performed.

As shown in FIG. 5K, the sub-alignment plate is patterned with a dry film (DFR) as a mask in the through opening of the semiconductor chip unit.

Through opening of the patterned sub-alignment plate as shown in step 5l is to use any one of dry etching processing, sandblast processing, ultrasonic processing, laser processing.

The sub-arrangement plate is manufactured by selecting any one of a glass plate, a quartz glass plate, and a pyrex glass plate.

A relay element and a condenser element are added to the sub-arrangement plate.

The purpose of adding the relay element and the condenser element to the sub-arrangement plate is to relay the semiconductor chip inspection formed on the wafer, and the condenser element to control the noise and bypass current generated during the inspection.

After the sub-arrangement plate opened through the cleaning step as shown in step 5m, it is bonded to each other with the lower surface of the main alignment plate.

In the bonding method of the main alignment plate and the sub-alignment plate, a polymer adhesive or a photoresist is applied between the anodic bond or the main alignment plate and the sub-alignment plate butt, and the main alignment plate and the sub-alignment plate are baked and bonded together.

As shown in FIG. 3A, the number of through openings 13a of the alignment plate 10 is formed by the number of inspection probe pins of one semiconductor chip, and one semiconductor chip is referred to as one dirt 35.

The sub-alignment plate 30 has one through opening 34 formed in one semiconductor chip unit.

As shown in FIG. 3B, the quantity of the through opening 13b of the alignment plate 10 is formed in one whole unit 35 of one semiconductor chip, and the unit 35 of each semiconductor chip is an individual dirt 35. The number of probe pins is etched into the groove 13c by a part of the depth of the number of probe pins at the both ends of the through opening 13b, and the center portion is the through opening 13b.

The through opening wall and the partial depth groove 13c of the main heat alignment plate 10 have an insulating film deposited thereon and a polymer elastic body coated on the insulating film.

The size of the through opening of the sub-alignment plate 30 is one unit 35 of one semiconductor chip or one unit 36 of a plurality of semiconductor chips.

The main alignment plate 10 and the sub-alignment plate 30 are bonded to each other by selecting one of a silicon substrate / silicon substrate, a silicon substrate / glass plate, and a silicon substrate / polymer resin.

The size and the combination of the main alignment plate 10 and the sub-alignment plate 30 can be selected from one of the block / block, block / bout, bout / bout. Block 37 consists of a plurality of dirts 35.

As shown in FIG. 3D, the block 37 unit of the main alignment plate 10 and the sub alignment plate 30 may include a plurality of units of the dirt 35 of the semiconductor chip in a row, or the dirt 38 of the semiconductor chip in two rows. It can be in multiple units.

As shown in FIG. 3E, an insulating material 49 is coated on the side surfaces of the block 37 in four directions for insulation when the block 37 and the block 37 unit of the columnar heat plate 10 are butt-coupled 33. In addition, when the butt joint 33 of the dirt 35 and the dirt 35, the insulating material 49 is applied to the four sides of the dirt 35 for insulation.

The insulating material 49 is used among insulating polymer and photoresist.

In addition, when the probe pin is automatically inserted into the through opening of the main heat exchanger plate 10, the recognition code 31 capable of recognizing the insertion start position is the dirt 35, 38, 37, 37, or 39 b. It is formed at one end to indicate the insertion start direction.

As shown in FIG. 4A, the main alignment plate 10 and the sub alignment plate 30 are bonded up and down butt joints 43 and overlapping junctions 45 and 4C as shown in FIG. 4C. One of them is selected and joined, and the joints of the dirt 35 and the dirt 35 or the block 37 and the block 37 of the main heat exchanger plate 10 are left and right butt joints 33.

The unit of the main plate 10 of the main alignment plate 10 and the sub-alignment plate 30 is that the probe head size can be inspected at one time.

Example 2

As shown in FIGS. 6A to 6N, the first conducting plate 20 and the second conducting plate 25 made of a substrate etch through holes at once from the upper surface to the one lower surface. In order to etch the through opening at the first conducting plate 20 at a time, a notch prevention layer is deposited on the selected lower surface of the substrate, and the through opening is etched by dry etching from the upper surface to the lower surface. FIG. 7 is a view illustrating the first conducting plate 20 and the second conducting plate 20. When the first conducting plate 20 and the second conducting plate 25 are manufactured and the conductive material is filled in the through openings formed in the first conducting plate 20, the filled through openings become vertical conducting wirings 27. In addition, the conductive wiring film 29 is attached to the upper horizontal layer of the second conductive plate 25, and the first conductive plate and the second conductive plate 25 are bonded to each other to manufacture a multi-layer spatial deformer.

In the above, the multi-layer spatial transducer is composed of the first conducting plate 20 and the second conducting plate 25.

The first conducting plate 20 and the second conducting plate 25 are bonded to each other to increase the strength of the conducting plate.

6A to 6N are flowcharts illustrating embodiments of a manufacturing process of the first conducting plate and the second conducting plate in detail.

As shown in FIG. 6A, a current-carrying plate is manufactured by using a MEMS process, and is made of a single-crystal silicon substrate of 100 directions with good etching. The silicon substrate is polished and cleaned with flatness on the upper and lower surfaces to improve adhesion and application performance do.

The silicon substrate is used as the first conducting plate to proceed to the next step.

As shown in FIG. 6B, the photoresist is uniformly and evenly coated on the upper surface of the first conducting plate by using a spin coater.

As shown in FIG. 6C, a photoresist mask having a through opening pattern is prepared, and exposed and developed with a photoresist mask on an upper surface of the first conductive plate to which the photoresist is applied to pattern a desired through opening shape.

As shown in FIG. 6D, a notch preventing layer is deposited on the lower surface of the first conducting plate by sputtering.

The notch prevention layer may be used by selecting any one of Cu, Al, Cr, Ti / Au, and all the metals for the notch prevention layer can be used.

As shown in FIG. 6E, the through opening is performed on the upper surface of the first conducting plate by a Deep RIE or Bosch process.

As shown in FIG. 6F, the notch prevention layer remaining on the lower surface of the first conducting plate is separated and the photoresist remaining on the upper surface is removed.

As shown in FIG. 6G, an insulating film is deposited on the through opening wall formed on the first conducting plate and the entire exposed first conducting plate.

The insulating film of the first conducting plate is deposited by selecting one of an oxide film, a nitride film, and a TEOS film.

As shown in FIG. 6H, a seed film is formed on the through opening wall formed in the first conducting plate.

The seed film is preferably any one of Ti / Au, Ni alloy, Ni or Cu.

The selected seed film is required as a plating facilitating layer for supplying electrons for reducing metal ions when electroplating is used to embed the conductive electrode material in the through hole of the first conducting plate.

As shown in FIG. 6I, plating for filling and filling the conductive electrode material metal by electroplating is performed in the through opening of the first conducting plate.

The conductive material of the conducting electrode embedded in the through opening of the first conducting plate is embedded with Cu.

As shown in FIG. 6J, the metal overfilled in the through opening of the upper surface of the first conducting plate is polished.

Polishing is preferably carried out by a chemical machining (CMP) process.

As shown in FIG. 6K, an anti-reflection image is formed on the upper surface of the first conducting plate, and the front surface of the first conducting plate on which the vertical conducting wiring embedded in the through opening is formed is cleaned.

The anti-reflection image may be processed by selecting one of sandblasting, texture processing, non-conductive polymer resin deposition, and laser processing. The texture processing is a wet etching solution with a mixture of alkali and acid.

Next, a second conduction plate process is performed.

As illustrated in FIG. 6L, the second conducting plate patterns the through openings in the shape of semiconductor chip units, using a dry film DFR as a mask.

The through opening of the patterned second conducting plate as shown in step 6m is to use any one of the dry etching processing, sandblast processing, ultrasonic processing, laser processing.

A relay element and a condenser element are added to the second conducting plate.

The purpose of adding the relay element and the condenser element to the second conducting plate is that the relay element can divide the semiconductor chip inspection formed on the wafer, and the condenser element controls the noise and bypass current generated during the inspection.

After cleaning the second conductive plate penetrated as shown in FIG. 6N, the conductive wiring film is added to the horizontal plane to be connected to the first conductive plate.

The second conducting plate is manufactured by selecting any one of a silicon substrate, a glass plate, a quartz glass plate, and a Pyrex glass plate.

If there is conductivity in the second conducting plate, an insulating film is deposited, and the first conducting plate and the joining method may be coated with a first adhesive plate or a polymer adhesive or photoresist between butt joints of the first conducting plate and the second conducting plate. The second conducting plate is baked and bonded to each other.

The plurality of conducting electrodes of the first conducting plate may be formed in the number of inspection probe pins in the unit of the semiconductor chip.

The first conductive plate and the second conductive plate are bonded to each other by selecting one of a silicon substrate / silicon substrate, a silicon substrate / glass plate, and a silicon substrate / polymer resin.

The size and combination of the first conducting plate and the second conducting plate is to select one of blocks / blocks, blocks / bout, and bout / bout.

The block unit is formed of one dirt to a plurality of dirts.

The first conducting plate connects the block and the block in a left-right butt joint method, and the block is coated with an insulating material on four sides in order to insulate the block side and the block side during the butt joint.

In addition, in the butt joint of the dirt and the dirt, the insulating material is applied to the side of the dirt in four directions for the insulation of the dirt side and the dirt side.

The insulating material is used to select any one of an insulating polymer and a photoresist.

The block unit of the first conducting plate and the second conducting plate has a plurality of dirt units of a row of semiconductor chips or a plurality of dirt units of a row of semiconductor chips.

In addition, a recognition code for recognizing the starting position when the probe pin is automatically bonded to the conducting electrode of the first conducting plate is formed on the upper surface of the dirt unit, the block unit, or the plate unit. will be.

The unit of one plate of the first conducting plate and the second conducting plate is that the probe head size can inspect the wafer to be inspected at a time.

The bonding method of the first conducting plate and the second conducting plate of the second embodiment, the insulation method in the dirt unit, the block unit, and the indication of the recognition code direction are the same as those of FIGS. 3A to 3E and 4A to 4C of the first embodiment.

In addition, the space transformer manufactured by the MEMS process is laminated with the energizing plate layer so as to be the desired space transformer, and a partial process is repeated when the lamination process is added.

In addition, the embodiment and the manufacturing method of the square shaped energizing plate by the MEMS process are also the same as the above-mentioned Example.

The present invention is not limited to the above embodiments of the bonding method of the current carrying plate, but a known joining method may be used within the technical spirit and scope of the present invention, and a method of manufacturing the modified heat exchanger and the carrying plate. Is the same.

1A is a cross-sectional view illustrating a step difference occurring in a through opening wall during bidirectional etching of a conventional silicon substrate.

1B is a cross-sectional view illustrating a state in which a notch phenomenon is formed in a through opening in a conventional silicon substrate.

2 is a cross-sectional view showing a state in which the through opening is well formed by the one-way etching of the present invention.

3A, 3B, 3C, 3D, and 3E are perspective views illustrating a joint state of dirt units and block units of the main alignment plate and the sub-alignment plate of the present invention.

4A, 4B, and 4C are perspective views illustrating a bonding method between a main alignment plate and a sub alignment plate of the present invention.

5 is a process flowchart illustrating a method of manufacturing a main alignment plate and a sub alignment plate of the present invention.

FIG. 6 is a process flowchart illustrating a method of manufacturing the first conducting plate and the second conducting plate of the present invention, and FIG. 7 shows a state of the first conducting plate and the second conducting plate of the present invention.

Description of the Related Art

10... ... Through opening 15... Step difference 18. Notch phenomenon

20 ... First energizing plate 23. Through opening 25... Second conducting plate 27. Vertical energization wiring

29... Horizontal conductive wiring film 30.. . Support plate 31. Recognition code 33... Butt joint

35... Dirt 37... Block 39... Bout 43. Butt Joint

45... Overlap junction 47... Space bar junction 53... Antireflection film 55. Notch protection layer

Claims (15)

In the heat transfer plate and the heat transfer plate of the probe pin made of a silicon substrate, the heat transfer plate is composed of a main heat transfer plate and a sub-alignment plate, the current transfer plate is composed of a first conducting plate and a second conducting plate, Depositing a notch preventing layer on the lower surface of the sub-alignment plate, the first conducting plate and the second conducting plate, and etching the through opening at once from the upper surface to the lower surface, and the first conducting plate embeds the conductive metal after the vertical opening. The vertical conduction wiring, the second conduction plate horizontally conduction wiring film is the conduction wiring, the sub-alignment plate and the second conduction plate is a relay element and a condensate element is added, And the sub-alignment plate, the first conducting plate, and the second conducting plate are overlapped with each other. According to claim 1, wherein the notch prevention layer on the lower surface of the main order plate, the sub-alignment plate, the first conducting plate and the second conducting plate is deposited by sputtering by selecting any one of Cu, Al, Cr, Ti / Au. An alignment plate and an energizing plate of the probe pin. The method of claim 1, wherein the main order plate, the sub-alignment plate, the first conducting plate and the second conducting plate is selected from the silicon substrate, glass plate, quartz glass plate, Pyrex glass plate and processing the alignment of the probe pins Plate and energizing plate. According to claim 1, wherein the size and the combination of the order plate and the sub-alignment plate, the first conducting plate and the second conducting plate is formed of block / block, block / Han, Han / Han, The block unit of the alignment plate and the first conducting plate and the second conducting plate is the dirt of a single chip in a row and the dirt of a plurality of chips in a row, and the dirt of a chip having two rows in a row is a plurality of chips in a second row. And a unit of the main alignment plate, the sub-alignment plate, the first conducting plate, and the second conducting plate, the probe head having a single size, and the through opening size of the sub-aligning plate has a unit of 1 dirt. Alignment plate and conduction plate of the probe pin, characterized in that formed in a plurality of dirt units. 5. The block of claim 4, wherein the blocks of the main ordering plate, the sub-ordering plate, the first conducting plate, and the second conducting plate are coated with an insulating material on side surfaces in four directions. Dirt of the plate and the second conducting plate is an insulating material is applied to the side of the four directions, the insulating material is an insulating polymer and a photoresist, the alignment plate and the conducting plate of the probe pin, characterized in that used to be used. 5. The method of claim 4, wherein the top and bottom joints of the main order plate and the sub-alignment plate are selected by butt joining, overlapping joining, and space bar addition joining. Alignment plate and energizing plate of the probe pin, characterized in that the right butt joint. The method of claim 1, wherein the through opening of the columnar heat sink, the sub-arrangement plate, and the first conducting plate and the second conducting plate are processed using any one of dry etching processing, sandblast processing, ultrasonic processing, and laser processing. An alignment plate and an energizing plate of the probe pin. The semiconductor device of claim 1, wherein the through opening of the alignment plate may be formed in the number of probe pins in the unit of dirt of one semiconductor chip, and the through opening of the alignment plate may be formed in the unit of dirt of one semiconductor chip. The unit is the number of individual probe pins of the chip, the alignment plate and the energizing plate of the probe pin, characterized in that the groove is etched only a part of the depth of both ends of the through opening. The method of claim 4, wherein the recognition code direction for recognizing the starting position when inserting the probe pin into the through opening of the main heat exchanger plate and bonding the probe pin to the conducting electrode of the first conducting plate has a unit of dirt, block, or plate. An alignment plate and an energizing plate of the probe pin, characterized in that formed on the upper surface of the unit. The method of claim 1, wherein the junction between the main heat exchanger plate, the sub-arrangement plate, and the first conducting plate and the second conducting plate is selected from a silicon substrate / silicon substrate, a silicon substrate / glass plate, and a silicon substrate / polymer resin. Alignment plate and conduction plate of the probe pin. The method of claim 1, wherein the main heat exchanger plate, the sub-arrangement plate, and the first conduction plate and the second conduction plate are bonded to each other by baking a polymer adhesive or photoresist between an enodic bond, an upper butt butt, and a baking bond. Alignment plate and the energizing plate of the probe pin, characterized in that for selecting the. The main and sub-arrangement plates are manufactured by MEMS process and are made of single-etch silicon substrates with good etchability in 100 directions.The silicon substrates polish and clean the flatness of the top and bottom surfaces precisely to improve adhesion and coating performance. Step a. B, applying a photoresist on the top surface of the main heat alignment plate uniformly and evenly using a spin coater; C) preparing a photoresist mask having a through opening pattern and exposing and developing a photoresist mask on an upper surface of the columnar heat treatment plate coated with the photoresist to pattern a desired through opening shape. D. Depositing a notch prevention layer by sputtering on a lower surface of the main heat alignment plate. Step e of performing the through opening on the top surface of the columnar order plate by Deep RIE. F notifying the notch prevention layer on the lower surface of the spirit plate and removing the photoresist remaining on the upper surface of the spirit plate. G step of forming an anti-reflection image on the upper surface of the columnar alignment plate and cleaning the entire surface. H depositing an insulating film on the through opening wall formed in the main alignment plate and the entire surface of the exposed alignment plate. I) forming a probe pin insertion position recognition code at one end of the main order plate; Step j for cleaning the entire surface of the ordered heat plate formed with the through opening and the recognition code. The sub-alignment plate is a step k for patterning the through-opening to dry film (DFR) in chip unit size. A step of processing the through opening to the patterned sub-alignment plate and attaching a relay element, a content element element. After cleaning the perforated sub-alignment plate, the main alignment plate and the sub-alignment plate manufacturing method characterized in that it is manufactured in step m to join the upper surface of the sub-alignment plate with each other. The first and second conduction plates are manufactured by using a MEMS process, and are made of a single-crystal silicon substrate in 100 directions with good etching. The silicon substrate is precisely polished and cleaned of the flatness of the top and bottom surfaces, and thus adhesion and coating performance. A step to make good. B, applying a photoresist uniformly and evenly to the upper surface of the first conducting plate by using a spin coater; C) preparing a photoresist mask having a through-opening pattern and exposing and developing a photoresist mask on an upper surface of the first conductive plate to which the photoresist is applied to pattern a desired through-opening shape. D. Depositing a notch prevention layer by sputtering on the lower surface of the first conductive plate. (E) etching the through opening on the upper surface of the first conducting plate by a Bosch process. F notifying the notched layer on the lower surface of the first conducting plate and removing the photoresist remaining on the upper surface. G depositing an insulating film on the through opening wall formed on the first conductive plate and the entire exposed first conductive plate. Step h to form a seed film on the through-opening wall formed in the first conductive plate. I) performing plating to fill-up the conductive electrode material metal by electroplating on the upper surface of the through opening formed in the first conducting plate. Step j of grinding the metal overfilled in the through opening of the upper surface of the first conducting plate by a chemical mechanical processing (CMP) process. K forming an anti-reflection image on the upper surface of the first conducting plate and cleaning the entire surface. The second conducting plate is a step of patterning the through opening with a dry film (DFR) mask. Step m for processing the through opening in the patterned second conducting plate. The first conducting plate and the second conducting plate are manufactured in an n step of attaching a horizontal conducting wiring film after cleaning the second conducting plate and bonding the lower surface of the first conducting plate and the upper surface of the second conducting plate. Method for manufacturing the current carrying plate. The method of claim 12, wherein the anti-reflective image formed on the upper surface of the spirit heating plate is selected from among sandblast processing, texture processing, non-conductive resin deposition, and laser processing. 14. The first conductive plate according to claim 13, wherein the anti-reflective image formed on the upper surface of the first conductive plate is processed by selecting any one of sandblast processing, texture processing, non-conductive resin deposition, and laser processing. Manufacturing method.

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