KR100992122B1 - Thin film transistor array panel - Google Patents

Abstract

       The thin film transistor array panel according to the present invention includes an insulating substrate, a gate line having a gate electrode formed on the insulating substrate, a gate insulating film covering the gate line, a semiconductor layer formed on the gate insulating film, and a source at least partially overlapping the semiconductor layer. A data line having an electrode, a drain electrode facing the source electrode centering on the gate electrode and at least partially overlapping the semiconductor layer, connected to the drain electrode, and the edge includes a pixel electrode overlapping the gate line or the data line; An incision is formed.

       Thin film transistor, light leakage, gate line

Description

       Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

       1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

       FIG. 2 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line II-II'-II ''-II '' '.

       3 is a graph measuring light leaking from a part of a liquid crystal display according to the related art.

       4 is a graph measuring light leaking from a part of a liquid crystal display including a thin film transistor array panel according to the present invention;

       5 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

       FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI′-VI ″ -VI ′ ″.

Description of the Related Art [0002]

110: insulated substrate 121: gate line

140: gate insulating film 151: semiconductor layer

161 and 165: ohmic contact layer 171: data line

       The present invention relates to a thin film transistor array panel.

       A liquid crystal display injects a liquid crystal material between a thin film transistor array panel and a color filter panel and applies an electric field to the liquid crystal to change the orientation of the liquid crystal to induce a change in the polarization state of light passing therethrough and pass through the polarizer according to the polarization state. It is a device that displays an image by changing the amount of light.

       The thin film transistor array panel may include a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to a gate line and a data line in each pixel, and a pixel electrode connected to the thin film transistor. Is done.

       In order to increase the aperture ratio of the liquid crystal display, the protective film of the thin film transistor array panel is formed of an organic material having a low dielectric constant. In other words, when the protective film is formed of an organic material, the pixel electrode can be formed to overlap the data line and the gate line, so that the aperture ratio of the pixel is improved.

       However, since the boundary portion of the pixel electrode is positioned on the gate line, the liquid crystal positioned at the boundary portion of the pixel electrode is affected by not only an electric field by the pixel electrode but also an electric field by the gate line.

       When the electric field is applied not only to the pixel electrode but also to the liquid crystal as described above, the fringe field for aligning the liquid crystal affects the fringe field formed by only the pixel electrode and the common electrode, and thus disorients the alignment of the liquid crystal. There is a problem that light leakage occurs.

       An object of the present invention is to provide a thin film transistor array panel that can minimize the light leakage from the edge of the pixel area by minimizing the effect of the electric field of the gate line to solve the above problems.

       In the thin film transistor array panel according to the exemplary embodiment of the present invention, a cutout is formed in a gate line of the pixel electrode of a neighboring pixel.

       More specifically, an insulating substrate, a gate line formed on the insulating substrate and having a gate electrode, a gate insulating film covering the gate line, a semiconductor layer formed on the gate insulating film, and a source electrode at least partially overlapping the semiconductor layer A drain electrode which faces the data line, the gate electrode, and is opposite to the source electrode and overlaps at least a portion of the semiconductor layer; and a pixel electrode that is connected to the drain electrode and whose edge is overlapped with the gate line or the data line. Formed.

       It is preferable to further include an ohmic contact layer formed between the semiconductor layer and the data line having the source electrode and the drain electrode.

       In addition, a protective film is further formed to cover the drain electrode and the data line, and the pixel electrode is preferably connected to the drain electrode through a contact hole formed in the protective film.

       In this case, the semiconductor layer has the same planar pattern as the ohmic contact layer except for a predetermined region, and the data line and the drain electrode having the source electrode preferably have the same planar pattern as the ohmic contact layer.

       In addition, the predetermined region is preferably a channel portion forming a channel between the source electrode and the drain electrode.

       In addition, it is preferable that the boundary portion of the pixel electrode is formed to overlap the cutout portion, or the cutout portion is formed between the boundary portions of the neighboring pixel electrodes.

       DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

       In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said "on top" of another part, this includes not only the other part "right over" but also another part in the middle. On the contrary, when a part is “just above” another part, there is no other part in the middle.

       [First Embodiment]                     

       First, the structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

       1 is a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is cut along the line II-II'-II ''-II '' 'of the thin film transistor array panel shown in FIG. It is sectional drawing.

       On the insulating substrate 110, a gate line 121 made of a single layer or a plurality of layers of metal such as molybdenum, tantalum, titanium, aluminum, or an alloy thereof is formed long in one direction. A portion or branched portion of the gate line 121 is used as the gate electrode 124.

       In this case, the gate line 121 has the cutout 201. The cutout 201 is positioned between the data lines 171 to be described later, and the boundary line of the pixel electrode 190 overlaps the cutout 201.

       One end 129 of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal from a driving circuit (not shown).

       In addition, in order to increase the storage capacitance, a storage electrode line 131 parallel to the gate line 121 and overlapping with the drain electrode 175 described later is formed. The storage electrode line 131 may be omitted when the storage capacitor formed to overlap the gate electrode of the front end adjacent to the pixel electrode 190 is sufficient.

       On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiNx) covers the gate lines 121 and 124 and the storage electrode line 131.

       A semiconductor layer 151 made of amorphous silicon without doping impurities is formed in a predetermined region of the gate insulating layer 140. The semiconductor layer 151 extends along the data line 171, which will be described later, and has a linear shape. The semiconductor layer 151 is extended to the bottom of the drain electrode 175.

       In addition, ohmic contacts 161 and 165 including amorphous silicon or silicide doped with impurities are formed on the semiconductor layer 151. The ohmic contacts 161 and 165 are islands facing the portion of the linear portion 161 around the linear portion 161 and the gate electrode 124 extending along the data line 171 together with the semiconductor layer 151. It consists of a mold 165. The island portion 165 is formed at a predetermined distance away from the linear portion 161, and they have the same planar pattern as the semiconductor layer 151 except for a predetermined region of the semiconductor layer 151. The predetermined region of the semiconductor layer 151 is a channel portion that forms a channel of the thin film transistor.

       A data line 171 is formed on the ohmic contact layer 161 to cross the gate line 121 to define a pixel area. The data line 171 is branched and has a source electrode 173 overlapping the gate electrode 124.

       In addition, a drain electrode 175 is formed on the ohmic contact layer 165 facing the source electrode 173 at a predetermined distance from the gate electrode 124 and partially overlapping the gate electrode 124. In this case, the data line 171 is in contact with the linear portion 161 of the ohmic contact layer and the drain electrode 175 is in contact with the island portion 165. One end 179 of the data line may be wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown).                     

       A passivation layer 180 made of an organic material, which is a low dielectric constant material, is formed on the data line 171 and the semiconductor layer 154 that is not covered.

       The passivation layer 180 is provided with a contact hole 183 exposing the drain electrode 175 and contact holes 181 and 182 exposing one end portions 129 and 179 of the gate line and the data line, respectively. On the passivation layer 180, a pixel electrode 190 made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, is connected to the drain electrode 175 through a contact hole 183. .

       In this case, the boundary line of the pixel electrode 190 overlaps the gate line 121. The cutout 201 formed in the gate line 121 is positioned between the boundary lines of the pixel electrode 190.

       In addition, contact auxiliary members 81 and 82 are formed on the passivation layer 180 to be connected to one end portions 129 and 179 of the gate line and the data line, respectively, through the contact holes 181 and 182. The contact auxiliary members 81 and 82 are for supplementing contactability and are selectively formed as necessary.

       As described above, when the cutout 201 is formed on the gate line 121, and the boundary line of the pixel electrode 190 overlaps the cutout 201, the liquid crystal positioned at the boundary of the pixel electrode 190 is formed. The electric field by the gate line 121 does not reach. Therefore, the range where the liquid crystal is disturbed at the boundary of the pixel electrode 190 is narrowed so that the light leakage generating region is reduced. That is, the light leakage region is moved to a region adjacent to the boundary of the pixel electrode 190 so that light leakage does not occur at a portion adjacent to the edge of the gate line 121.                     

       FIG. 3 is a graph illustrating light leaking from a part of a liquid crystal display according to the related art, and FIG. 4 shows light leaking from a part of a liquid crystal display including a thin film transistor array panel according to a first embodiment of the present invention. It is a graph measured. In FIG. 3, light leaks generated at one side of the gate line 121 are completely disappeared in FIG. 4, and light leaks generated at the other side are confirmed to be moved to the center of the gate line 121. Can be.

       As the light leakage generating region moves to the center of the gate line 121, light leakage generated around the gate line 121 may be completely blocked. Therefore, since the process margin for forming the gate line 121 width is increased to form the gate line 121 with a narrower width, the aperture ratio of the pixel region may be improved by the reduced width of the gate line 121.

       Second Embodiment

       FIG. 5 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line VI-VI′-VI ″ -VI ′ ″ of FIG. 5.

       As shown, the second embodiment has a planar pattern in which the data lines 171 and 173 and the drain electrode 175 have the same planar pattern as the ohmic contacts 161 and 165, unlike the first embodiment. , 165 has the same planar pattern except for a predetermined region of the semiconductor layer 154. The predetermined region is a channel portion that forms a channel of the thin film transistor.

       Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

       As described above, when a part of the gate line is removed, light leakage can be prevented by weakening the electric field between the boundary portions of the pixel electrode. In addition, the process margin of the gate line width is increased and the aperture ratio of the pixel region is increased to provide a high quality thin film transistor array panel.

Claims (7)

Insulation board, A gate line formed on the insulating substrate and having a gate electrode, A gate insulating film covering the gate line, A semiconductor layer formed on the gate insulating film, A data line having a source electrode overlapping the semiconductor layer, A drain electrode facing the source electrode with respect to the gate electrode and overlapping the semiconductor layer; A pixel electrode connected to the drain electrode and having an edge overlapping the gate line or the data line; A cutout is formed in the gate line, and the cutout is formed along a horizontal side of the pixel electrode. In claim 1, A protective film is further formed to cover the drain electrode and the data line. The pixel electrode is connected to the drain electrode through a contact hole formed in the passivation layer. The method of claim 1 or 2, And a resistive contact layer formed between the semiconductor layer and a data line and a drain electrode having the source electrode. 4. The method of claim 3, The semiconductor layer includes a wiring portion overlapping the data line and the drain electrode, and a channel portion overlapping the source electrode and the drain electrode, wherein the wiring portion has the same planar pattern as the data line and the drain electrode. delete The method of claim 1 or 2, And a boundary portion of the pixel electrode overlaps the cutout portion. The method of claim 1 or 2, The cut portion is a thin film transistor array panel disposed between the boundary line of the neighboring pixel electrode.

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