KR100990932B1 - Method for forming landing plug of semiconductor device - Google Patents

Method for forming landing plug of semiconductor device Download PDF

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KR100990932B1
KR100990932B1 KR1020030051578A KR20030051578A KR100990932B1 KR 100990932 B1 KR100990932 B1 KR 100990932B1 KR 1020030051578 A KR1020030051578 A KR 1020030051578A KR 20030051578 A KR20030051578 A KR 20030051578A KR 100990932 B1 KR100990932 B1 KR 100990932B1
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landing plug
film
forming
contact hole
nitride film
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KR20050012578A (en
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신원호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 반도체소자의 랜딩플러그 형성방법을 개시한다. 개시된 본 발명은, 실리콘기판상에 모트산화막을 형성하고 모트산화막 상에 게이트를 형성하는 단계; 게이트를 포함한 전면에 질화막을 형성하는 단계; 질화막상에 층간절연막을 형성하는 단계; 층간절연막과 질화막을 패터닝하여 실리콘 기판을 노출하는 랜딩플러그콘택홀을 형성하는 단계; 세정공정을 진행하는 단계; 세정공정시 랜딩플러그콘택홀 측면의 모트산화막이 소실되어 형성된 터널부 및 랜딩플러그콘택홀을 포함한 전면에 실리콘질화막 또는 실리콘산화질화막을 형성하는 단계; 실리콘질화막 또는 실리콘산화질막을 랜딩플러그콘택홀 측벽 및 터널부에만 남도록 선택적으로 제거하는 단계; 및 랜딩플러그콘택홀 내에 폴리실리콘막을 매립하여 랜딩플러그를 형성하는 단계를 포함하여 구성되어, 랜딩플러그와 게이트 간의 쇼트 발생을 원천적으로 차단하여 수율 및 신뢰성을 향상 시킬 수 있는 것이다.The present invention discloses a method for forming a landing plug of a semiconductor device. The disclosed invention comprises the steps of: forming a mot oxide film on a silicon substrate and forming a gate on the mot oxide film; Forming a nitride film on the entire surface including the gate; Forming an interlayer insulating film on the nitride film; Patterning the interlayer insulating film and the nitride film to form a landing plug contact hole exposing the silicon substrate; Proceeding with the cleaning process; Forming a silicon nitride film or a silicon oxynitride film on the entire surface including the landing portion and the landing plug contact hole formed by the mort oxide film on the side of the landing plug contact hole during the cleaning process; Selectively removing the silicon nitride film or the silicon oxide film so that only the landing plug contact hole sidewalls and the tunnel portion remain; And embedding the polysilicon film in the landing plug contact hole to form a landing plug, thereby preventing short circuiting between the landing plug and the gate to improve yield and reliability.

Description

반도체소자의 랜딩플러그 형성방법{Method for forming landing plug of semiconductor device} Method for forming landing plug of semiconductor device

도 1은 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 반도체소자의 레이아웃도,1 is a layout view of a semiconductor device for explaining a method for forming a landing plug of a semiconductor device according to the prior art;

도 2는 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 단면도로서, 도 1의 Ⅱ-Ⅱ선에 따른 단면도,FIG. 2 is a cross-sectional view illustrating a method of forming a landing plug of a semiconductor device according to the prior art, and is a cross-sectional view taken along the line II-II of FIG. 1;

도 3은 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 단면도로서, 도 1의 Ⅲ-Ⅲ선에 따른 단면도,3 is a cross-sectional view illustrating a method of forming a landing plug of a semiconductor device according to the prior art, a cross-sectional view taken along line III-III of FIG.

도 4는 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 반도체소자의 레이아웃도,4 is a layout view of a semiconductor device for explaining a method of forming a landing plug of a semiconductor device according to the present invention;

도 5a 및 도 5b는 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 단면도로서, 도 4의 Ⅴ-Ⅴ선에 따른 단면도,5A and 5B are cross-sectional views illustrating a method of forming a landing plug of a semiconductor device according to the present invention, and are cross-sectional views taken along the line VV of FIG. 4.

[도면부호의설명][Description of Drawing Reference]

31 : 실리콘기판 33 : 모트산화막31 silicon substrate 33 mote oxide film

35 : 폴리실리콘층 37 : 텅스텐박막35 polysilicon layer 37 tungsten thin film

39 : 하드마스크 41 : 게이트구조39: hard mask 41: gate structure

43 : 스페이서용 질화막 45 : 층간절연막 43 nitride film for spacer 45 interlayer insulating film                 

47 : 랜딩플러그 콘택홀 47a : 터널부47: landing plug contact hole 47a: tunnel portion

49 : 실리콘나이트라이드막(질화산화막) 49 silicon nitride film (nitride oxide film)

본 발명은 반도체소자의 랜딩플러그 형성방법에 관한 것으로서, 보다 상세하게는 반도체소자에서 랜딩플러그 스페이서를 이용한 게이트와의 쇼트를 방지할 수 있는 반도체소자의 랜딩플러그 형성방법에 관한 것이다.The present invention relates to a method of forming a landing plug of a semiconductor device, and more particularly, to a method of forming a landing plug of a semiconductor device capable of preventing a short with a gate using a landing plug spacer in the semiconductor device.

최근 디램 프로세스 테크놀러지는 그 최소 선폭(minimul feature size)이 줄어듦에 따라 셀의 게이트와 게이트사이에 소스/드레인전극을 형성방법이 바 타입의 콘택홀(LPC)을 형성한 후 그 부분에 폴리실리콘을 증착하는 기술이 있다.Recently, DRAM process technology has reduced the minimum feature size, so that the source / drain electrodes are formed between the gate and the gate of the cell to form a bar type contact hole (LPC). There is a deposition technique.

이러한 기존의 반도체소자의 랜딩플러그 형성방법에 대해 도 1 내지 도 3을 참조하여 설명하면 다음과 같다.A method of forming a landing plug of the conventional semiconductor device will be described with reference to FIGS. 1 to 3 as follows.

도 1은 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 반도체소자의 레이아웃도이고, 도 2는 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 단면도로서, 도 1의 Ⅱ-Ⅱ선에 따른 단면도이다.1 is a layout diagram of a semiconductor device for describing a landing plug forming method of a semiconductor device according to the prior art, and FIG. 2 is a cross-sectional view illustrating a method for forming a landing plug for a semiconductor device according to the prior art. It is sectional drawing along the -II line.

또한, 도 3은 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명 하기 위한 단면도로서, 도 1의 Ⅲ-Ⅲ선에 따른 단면도이다.3 is a cross-sectional view illustrating a method of forming a landing plug of a semiconductor device according to the prior art, and is a cross-sectional view taken along line III-III of FIG. 1.

종래기술에 따른 반도체소자의 랜딩플러그 형성방법은, 도 1에 도시된 바와 같이, 실리콘기판(11)상에 게이트산화막(13)을 형성한후 그 위에 폴리실리콘층(15), 텅스텐박막(17) 및 하드마스크(19)를 순차적으로 적층한다.In the method of forming a landing plug of a semiconductor device according to the related art, as shown in FIG. 1, after forming a gate oxide film 13 on a silicon substrate 11, a polysilicon layer 15 and a tungsten thin film 17 thereon. ) And the hard mask 19 are sequentially stacked.

그다음, 상기 하드마스크(19), 텅스텐박막(17) 및 폴리실리콘층(15)을 선택적 으로 제거하여 게이트구조(20)를 형성한다.Next, the hard mask 19, the tungsten thin film 17, and the polysilicon layer 15 are selectively removed to form the gate structure 20.

이어서, 상기 게이트구조(20)를 포함한 게이트산화막(13)상에 스페이서용 질화막(21)을 증착한후 그 위에 층간절연막(23)을 두껍게 증착한다.Subsequently, a nitride layer 21 for spacers is deposited on the gate oxide layer 13 including the gate structure 20, and a thick interlayer insulating layer 23 is deposited thereon.

그다음, 랜딩플러그 콘택마스크(미도시)를 상기 층간절연막(23)상에 형성한후 이를 마스크로 상기 층간절연막(23)과 스페이서용 질화막(21) 및 게이트산화막(13) 부분을 선택적으로 제거하여 랜딩플러그 콘택홀(25)을 형성한다.After that, a landing plug contact mask (not shown) is formed on the interlayer insulating layer 23, and then a portion of the interlayer insulating layer 23, the spacer nitride layer 21, and the gate oxide layer 13 are selectively removed using a mask. The landing plug contact hole 25 is formed.

이어서, 상기 랜딩플러그 콘택홀(25)을 포함한 층간절연막(23)상에 랜딩 플러그용 폴리실리콘층(27)을 증착한후 이를 평탄화시켜 랜딩플러그(미도시)를 형성한다.Subsequently, a landing plug polysilicon layer 27 is deposited on the interlayer insulating layer 23 including the landing plug contact hole 25 and then planarized to form a landing plug (not shown).

그러나, 랜딩플러그콘택홀(25)에 폴리실리콘층을 증착하기 전에 계면의 이물질 및 표면 산화막을 제거하기 위한 세정방법으로 BOE등을 사용하는데, 이때, BOE는 표면의 이물질뿐만 아니라 STI 구조의 모우트(moat)부분에 있는 버퍼산화막(라이너산화막)(11b)를 제거시키게 된다.However, before depositing the polysilicon layer in the landing plug contact hole 25, BOE or the like is used as a cleaning method for removing foreign matter and surface oxide film at the interface, wherein the BOE is not only a foreign material on the surface but also a moat of STI structure. The buffer oxide film (liner oxide film) 11b in the moat portion is removed.

도 2의 "A" 및 도 3에서와 같이, 전 세정공정에 의해 STI의 모트부분에 형성된 산화막터널부분에 랜딩플러그용 폴리실리콘 일부가 증착되므로써 게이트전극(20)과의 쇼트가 발생 (즉, 터널이 완전히 게이트에 닿을 경우)하여 불량이 되거나, 터널이 게이트까지 닿지는 않았다 하더라도 후속 열공정 및 패키지 이후에 실시하는 생산 버닝(인위적으로 스트레스를 주어 불량이 될만한 취약한 제품을 걸러 내는 과정)에 의해 불량이 되게 된다.As shown in FIG. 2A and FIG. 3, a portion of the polysilicon for landing plug is deposited on the oxide tunnel portion formed in the mote portion of the STI by a pre-cleaning process, so that a short with the gate electrode 20 occurs (that is, If the tunnel is completely in contact with the gate), or if the tunnel is not in contact with the gate, it is produced by subsequent thermal processes and production burning after the package (a process that filters out vulnerable products that are likely to be defective due to artificial stress). It becomes a defect.

결국, 이와 같은 불량이 많을 경우 수율을 떨어 뜨려 경제적인 손실을 유발할 뿐만 아니라 제품의 신뢰성도 떨어 뜨리는 주요 원인이 되고 있다.As a result, a large number of such defects are not only causing economic losses by lowering the yield, but also being a major cause of declining product reliability.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 랜딩플러그 폴리기법을 이용하는 모든 디램셀에서 랜딩플러그와 게이트 간의 원하지 않는 터널에 의한 쇼트 발생을 미리 차단하여 수율 및 신뢰성을 향상 시킬 수 있는 반도체소자의 랜딩플러그 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, in order to improve the yield and reliability by blocking the occurrence of an unwanted tunnel between the landing plug and the gate in advance in all DRAM cells using the landing plug poly technique. It is an object of the present invention to provide a method for forming a landing plug of a semiconductor device.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 랜딩플러그 형성방법은, Landing plug forming method of a semiconductor device according to the present invention for achieving the above object,

실리콘기판상에 모트산화막을 형성하고 모트산화막 상에 게이트를 형성하는 단계;Forming a mot oxide film on the silicon substrate and forming a gate on the mot oxide film;

게이트를 포함한 전면에 질화막을 형성하는 단계;Forming a nitride film on the entire surface including the gate;

질화막상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the nitride film;

층간절연막과 질화막 및 모트산화막을 패터닝하여 실리콘기판을 노출하는 랜딩플러그콘택홀을 형성하는 단계;Patterning the interlayer insulating film, the nitride film, and the oxide oxide film to form a landing plug contact hole exposing the silicon substrate;

세정공정을 실시하는 단계;Performing a cleaning process;

세정공정시 랜딩플러그콘택홀 측면의 모트산화막이 소실되어 형성된 터널부 및 랜딩플러그콘택홀을 포함한 전면에 실리콘질화막 또는 실리콘산화질화막을 형성하는 단계;Forming a silicon nitride film or a silicon oxynitride film on the entire surface including the landing portion and the landing plug contact hole formed by the mort oxide film on the side of the landing plug contact hole during the cleaning process;

상기 실리콘질화막 또는 실리콘산화질화막을 상기 랜딩플러그콘택홀측벽 및 터널부에만 남도록 선택적으로 제거하는 단계; 및Selectively removing the silicon nitride film or the silicon oxynitride film so as to remain only at the landing plug contact hole side wall and the tunnel portion; And

상기 선택적으로 제거되고 남은 실리콘질화막 또는 실리콘산화질화막을 포함한 랜딩플러그콘택홀 내에 폴리실리콘막을 매립하여 랜딩플러그를 형성하는 단계를 포함하여 구성되는 것을 특징으로 한다.And embedding the polysilicon film in the landing plug contact hole including the silicon nitride film or the silicon oxynitride film that has been selectively removed and formed to form a landing plug.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a landing plug of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 4는 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 반도체소자의 레이아웃도이고, 도 5는 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 단면도로서, 도 4의 Ⅴ-Ⅴ선에 따른 단면도이다.4 is a layout diagram of a semiconductor device for describing a method for forming a landing plug of a semiconductor device according to the present invention, and FIG. 5 is a cross-sectional view illustrating a method for forming a landing plug for a semiconductor device according to the present invention. Sectional view along the -V line.

본 발명에 따른 반도체소자의 랜딩플러그 형성방법은, 도 5a에 도시된 바와 같이, 실리콘기판(31)상에 게이트산화막으로 사용하기 위한 모트산화막(33)을 형성한후 그 위에 폴리실리콘층(35), 텅스텐박막(37) 및 하드마스크(39)를 순차적으로 적층한다.In the method for forming a landing plug of a semiconductor device according to the present invention, as shown in FIG. 5A, a polysilicon layer 35 is formed on a silicon oxide layer 31 after forming a mott oxide layer 33 for use as a gate oxide layer. ), The tungsten thin film 37 and the hard mask 39 are sequentially stacked.

그다음, 상기 하드마스크(39), 텅스텐박막(37) 및 폴리실리콘층(35)을 패터닝하여 게이트(41)를 형성한다.Next, the hard mask 39, the tungsten thin film 37, and the polysilicon layer 35 are patterned to form a gate 41.

이어서, 상기 게이트(41)를 포함한 모트산화막(33)상에 스페이서용 질화막(43)을 증착한후 그 위에 층간절연막(45)을 두껍게 증착한다.Subsequently, a nitride nitride film 43 for spacers is deposited on the mot oxide film 33 including the gate 41, and a thick interlayer insulating film 45 is deposited thereon.

그다음, 랜딩플러그 콘택마스크(미도시)를 상기 층간절연막(45)상에 형성한후 이를 마스크로 상기 층간절연막(45)과 스페이서용 질화막(43) 및 모트산화막 (33)을 식각하여 랜딩플러그 콘택홀(47)을 형성한 후 랜딩플러그 형성용 콘택마스크(미도시)를 제거한다. After that, a landing plug contact mask (not shown) is formed on the interlayer insulating layer 45, and the landing plug contact is etched by etching the interlayer insulating layer 45, the spacer nitride layer 43, and the mot oxide layer 33 using the mask as a mask. After forming the hole 47, the contact plug forming contact mask (not shown) is removed.

이어서, 세정용액(예를들어, BOE 또는 HF)을 이용한 세정공정을 진행하여 랜딩플러그 콘택홀(47) 바닥 측면에 있는 모트산화막(33)부분이 제거되면서 터널부 (47a)가 형성된다. 이때, 상기 랜딩플러그콘택홀(47)은 표면에 실리콘 기판과 트렌치산화막, 그리고 이들 사이의 스트레스를 완충시키기 위하여 형성된 모트산화막(33) 부분이 드러나게 되는데, 이 모트산화막(33) 부분은 BOE(pre cleaning)등에 잘 소실된다. 이로 인해, 랜딩플러그 콘택홀(47)을 폴리실리콘으로 채우기 전에 전 세정공정에 의해 콘택홀 바닥측면에 있는 모트산화막(33) 부분이 딥아웃(dip out)되어 게이트까지 터널부(47a)를 형성하게 된다. 이러한 현상은 랜딩플러그 콘택홀과 게이트 간의 간격이 짧을수록 더욱 잘 발생하고, 제품을 작게하여 넷 다이를 증가시키는데 한계가 되기도 한다.Subsequently, a cleaning process using a cleaning solution (for example, BOE or HF) is performed to remove the mott oxide layer 33 on the bottom side of the landing plug contact hole 47, thereby forming the tunnel portion 47a. In this case, the landing plug contact hole 47 exposes a silicon substrate, a trench oxide film, and a mote oxide film 33 formed on the surface to buffer the stress therebetween, and the mote oxide film 33 is formed of BOE (pre). It is lost well by cleaning). Therefore, before filling the landing plug contact hole 47 with polysilicon, a part of the mote oxide film 33 at the bottom side of the contact hole dips out by a pre-cleaning process to form the tunnel portion 47a to the gate. Done. This phenomenon is more likely to occur with shorter gaps between landing plug contact holes and gates, and may limit the increase in net die by making products smaller.

이어서, 이와 같은 불량을 방지하기 위하여, 상기 랜딩플러그 콘택홀(47)을 포함한 층간절연막(45)상에 50∼150Å정도 두께의 부도체물질인 실리콘 질화막(SiN) 또는 실리콘산화질화막(SiON)(49)을 증착한다. 이때, 실리콘질화막(SiN) 또는 실리콘산화질화막(SiON)(49)의 두께는 일반적으로 얇을수록 좋으며, 그 증착 방식이 CVD 등의 기법이어야만 기 형성된 터널부(47a)에도 잘 증착된다.Subsequently, in order to prevent such a defect, a silicon nitride film (SiN) or a silicon oxynitride film (SiON) 49 is formed on the interlayer insulating film 45 including the landing plug contact hole 47. E). At this time, the thickness of the silicon nitride film (SiN) or the silicon oxynitride film (SiON) 49 is generally thinner, and the better the thickness of the silicon nitride film (SiN) or the silicon oxynitride film (SiON) 49.

그다음, 도 5b에 도시된 바와같이, 상기 실리콘질화막 또는 실리콘산화질화막(49)을 상기 랜딩플러그콘택홀(47)측면에만 남도록 직진성을 갖는 건식 식각을 진행하여 플러그스페이서(49a)를 형성한다. 이때, 상기 터널부(47a)에 채워진 물질은 남게 된다. 또한, 상기 플러그 스페이서(49a) 형성시에 상기 실리콘기판(31)표면이 드러나게 된다. 이렇게 하여 전세정공정에서 생성된 터널부(47a)에 위와 같은 부도체 물질로 채워 넣음으로써 게이트간의 쇼트가 방지된다.Next, as shown in FIG. 5B, the dry etching process is performed such that the silicon nitride film or the silicon oxynitride film 49 remains on the landing plug contact hole 47 side only to form a plug spacer 49a. At this time, the material filled in the tunnel portion 47a remains. In addition, the surface of the silicon substrate 31 is exposed when the plug spacer 49a is formed. In this way, the gate portion is prevented by filling the tunnel portion 47a generated in the pre-cleaning process with the above non-conductive material.

이어서, 도면에는 도시하지 않았지만, 상기 드러난 실리콘기판(31)표면을 포함한 전체 구조의 상면에 랜딩 플러그용 폴리실리콘층(27) 을 증착한후 이를 평탄화시켜 랜딩플러그(미도시)를 형성한다. Subsequently, although not shown in the figure, the landing plug polysilicon layer 27 is deposited on the upper surface of the entire structure including the exposed silicon substrate 31, and then planarized to form a landing plug (not shown).

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 랜딩플러그 형성방법에 의하면, 랜딩플러그 폴리실리콘 기법을 이용하는 모든 디램셀에서 랜딩플러그와 게이트간의 원하지 않는 터널에 의한 쇼트발생을 미리 차단하여 수율 및 신뢰성을 향상시키며, 축소기법을 이용하여 넷다이 증진을 가능하게 하여 막대한 경제적 이익을 향상시킨다.As described above, according to the method for forming a landing plug of a semiconductor device according to the present invention, in all DRAM cells using the landing plug polysilicon technique, a short circuit caused by an unwanted tunnel between the landing plug and the gate is prevented in advance to yield and reliability. It is possible to increase net die by using reduction technique and to increase enormous economic benefits.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (5)

실리콘기판상에 모트산화막과 게이트 도전막 및 하드마스크막을 적층하고 상기 하드마스크막 및 게이트 도전막을 패터닝하여 게이트를 형성하는 단계;Forming a gate by stacking a mott oxide film, a gate conductive film, and a hard mask film on a silicon substrate and patterning the hard mask and gate conductive films; 상기 게이트를 포함한 전면에 질화막을 형성하는 단계;Forming a nitride film on the entire surface including the gate; 상기 질화막상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the nitride film; 상기 층간절연막과 질화막 및 모트산화막을 패터닝하여 상기 실리콘 기판을 노출하는 랜딩플러그콘택홀을 형성하는 단계;Patterning the interlayer insulating film, the nitride film, and the oxide oxide film to form a landing plug contact hole exposing the silicon substrate; 세정공정을 실시하는 단계;Performing a cleaning process; 상기 세정공정시 상기 랜딩플러그콘택홀 바닥 측면의 상기 모트산화막이 제거됨에 따라 형성된 터널부 및 상기 랜딩플러그콘택홀을 포함한 전면에 실리콘질화막 또는 실리콘산화질화막을 형성하는 단계Forming a silicon nitride film or a silicon oxynitride film on the entire surface including the landing portion and the landing plug contact hole formed by removing the mott oxide film on the bottom of the landing plug contact hole during the cleaning process; 상기 실리콘질화막 또는 실리콘산화질화막을 상기 랜딩플러그콘택홀 측벽 및 터널부에만 남도록 선택적으로 제거하는 단계; 및Selectively removing the silicon nitride film or the silicon oxynitride film so that only the landing plug contact hole sidewalls and the tunnel portion remain; And 상기 랜딩플러그콘택홀에 폴리실리콘막을 매립하여 랜딩플러그를 형성하는 단계;Embedding a polysilicon layer in the landing plug contact hole to form a landing plug; 를 포함하여 구성되는 것을 특징으로 하는 반도체소자의 랜딩플러그 형성방법.Landing plug forming method of a semiconductor device comprising a. 삭제delete 제1항에 있어서, 상기 세정공정 진행시에 BOE 또는 HF 용액을 사용하는 것을 특징으로하는 반도체소자의 랜딩플러그 형성방법.The method of claim 1, wherein a BOE or HF solution is used during the cleaning process. 제1항에 있어서, 상기 실리콘질화막 또는 실리콘산화질화막을 50∼100Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 랜딩플러그 형성방법.The method of claim 1, wherein the silicon nitride film or silicon oxynitride film is formed to a thickness of 50 to 100 GPa. 제1항에 있어서, 상기 실리콘질화막 또는 실리콘산화질화막을 선택적으로 제거하는 단계는 건식 식각방식으로 수행하는 것을 특징으로 하는 반도체소자의 랜딩플러그 형성방법.The method of claim 1, wherein selectively removing the silicon nitride film or the silicon oxynitride film is performed by a dry etching method.
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