KR100985462B1 - 8 to 10.9 GHz Band LC VCO for SONET Communication - Google Patents

Abstract

The present invention relates to an 8-10.9 GHz band LC VCO for a SONET communication system. More specifically, the present invention provides a trade-off between power consumption, phase noise, and tuning range in a conventional complementary cross-coupled LC VCO scheme. NMOS cross-coupled and PMOS active load technology is used to improve the off-relationship for CDR applications of SONET communication systems, and 8 ~ 10.9 for new structure SONET communication systems with wider tuning range and lower phase noise than conventional methods. Provides GHz band LC VCO.

 LC VCO, SONET Communication

Description

8 to 10.9 GHz Band LC VCO for SONET Communication for SONET communication systems

The present invention relates to 8 ~ 10.9GHz band LC VCO for SONET communication system, and more particularly, to improve the trade-off relationship between power consumption, phase noise and tuning range in the conventional complementary cross-coupled LC VCO scheme. NMOS cross-coupled and PMOS active load technology enables 8 to 10.9GHz band LC VCO for new architecture of SONET communication system with wide tuning range and low phase noise, which is possible for CDR application of SONET communication system, but with wider tuning range than conventional method It is about.

While Internet traffic is exploding due to the increase in broadband multimedia services such as Internet broadcasting, bottlenecks in the network are prominent because network infrastructure is not being expanded. In order to solve this phenomenon, 10 GHz band optical communication system (SONET) technology and market are growing rapidly, and the emergence of broadband applications such as cable HD-TV, instant HD video on demand and HD video telephony using the Internet, The use of high speed optical communication such as download of high speed online games and large multimedia files is increasing.

In the technical trend, systems at 10 Gb / s per channel are currently underway in the form of either OC-192 or STM-64 using European synchronous data layer or synchronous optical network, respectively.

In terms of process technology, optical communication system products using GaAs or SiGe technology have been the mainstream until now, but due to the development of micro process technology, the circuit line width is reduced, and the cut-off frequency of the device reaches 70 GHz for the MOSFET using the 0.18㎛ process. As the high frequency characteristics of active devices have been improved, research on the design and fabrication of CMOS VCOs has been increasing for high integration, reduction of manufacturing cost, and low power.

First, FIG. 1 is a block diagram showing the structure of a general optical communication receiver. Referring to FIG. 1, a clock and data recovery (CDR) plays a role of restoring data and generating a clock from a received signal mixed with noise through TIA and LA. The VCO not only generates the clock required for the CDRs, but also generates jitter for the entire CDR circuitry, which affects the CDR performance based on the VCO design results. In general LC VCO structure, the power consumption and phase noise are trade-off, and the tuning range is also trade-off. There is a relationship. When applied to optical communication systems, low power consumption and phase noise characteristics need to be improved. In addition, the oscillation frequency and the tuning range characteristics are inversely related, so the extension of the tuning range is a very important factor in the optical communication system above 10GHz.

Figure 2 is a circuit diagram showing a typical cross-coupled LC VCO structure, showing a cross-coupled CMOS LC VCO structure with a general fully differential negative-gm. Referring to FIG. 2, the structure shown in FIG. 2 is a symmetrical structure of the PMOS core and the NMOS core, so that the negative resistance component is doubled to significantly reduce the loss generated in the LC tank circuit, and to adjust the voltage of the varactor. Change frequency

In addition, the oscillation frequency is determined by the inductance of the resonance portion and the capacitance viewed from the oscillation node. At this time, the capacitance seen from the oscillation node can be classified into the capacitance of the varactor, the inductor's parasitic capacitance, and the parasitic capacitance of the PMOS core and the NMOS core.

Adding them all, the oscillation frequency of the oscillator is as shown in Equation 1 below.

Equation 1

As such, in LC VCOs using CMOS technology, the reduction in supply voltage due to the reduced gate length of CMOS does not have a wide frequency tuning range. In addition, variations in the output voltage magnitude over the LC VCO's frequency tuning range result in phase noise in the LC VCO.

If the inductance value is set too high to improve the phase noise characteristics, the varactor value of the resonator portion is reduced and the tuning range is narrowed. If the W value of the MOS transistor is reduced too much, the loss component of the LC-tank cannot be compensated for, and the oscillation condition is reduced. You get out. These results show that there is a trade-off between phase noise and tuning range.

The present invention has been made to solve the problems of the tuning range and phase noise, which are trade off relations, and the tradeoff between phase noise and power consumption. In order to improve the trade-off relationship between power consumption, phase noise and tuning range, the NMOS cross-coupled and PMOS active load technology is applied to the CDR application of SONET communication system, but with a wider tuning range and lower than conventional methods. It is an object of the present invention to propose a design technique of a 8 V to 10.9 GHz band LC VCO for a SONET communication system having a phase noise.

In order to achieve the above object, according to an embodiment of the present invention, a first current source for supplying current to the entire LC VCO circuit; A first node existing between said first current source and an LC VCO overall circuit; An LC VCO overall circuit connected between the first node and ground, wherein the LC VCO overall circuit has its drain connected to the first node, respectively, and its source to the second node and the third node, respectively. A third MOSFET and a fourth MOSFET, each of which is connected to a second MOSFET, a source of which is connected to a second node and a third node, each of which has a drain connected to a second current source; A first inductor connected between the second node and the third node, a varactor connected between the second node and the third node, and connected to respective sources and gates of the third and fourth MOSFETs. An NMOS cross-coupled circuit and a PMOS active load circuit coupled to the NMOS cross-coupled circuit, the gate of the first MOSFET being connected to a third node, Crab of the second MOSFET Is connected to a second node, the second current source is grounded at one side of the ground, and the PMOS active load circuit includes a fifth MOSFET and a sixth MOSFET connected with a second voltage source and respective drains. The fifth MOSFET and the sixth MOSFET have their gates and sources connected to each other, and the NMOS cross-coupled circuit includes a seventh MOSFET having a source connected to a source of the fifth MOSFET and the sixth MOSFET, respectively. The eighth MOSFET, the gate of the seventh MOSFET is connected to the gate of the fourth MOSFET and the second node, and the gate of the eighth MOSFET is connected to the gate of the third MOSFET and the third node. And the drains of the seventh and eighth MOSFETs are respectively grounded to ground, and the PMOS active load circuit and the NMOS cross-coupled circuit are connected to each other to reduce phase noise. Implemented symmetrically, the Gm of the transistor is the same, and the first current source is a first TAIL MOSFET (M _tail1 ) and a second TAIL MOSFET (M) connected to a first voltage source, the first voltage source and each drain _thereof . _tail2 ), a resistance between the gate of the first TAIL MOSFET and the gate of the second TAIL MOSFET, a bias current source between the source and the ground of the first TAIL MOSFET, and flicker noise between the first voltage source and the first node. And a capacitor to remove the source, wherein a source of the second TAIL MOSFET is connected to the LC VCO entire circuit at the first node and comprises the first MOSFET, the second MOSFET, the seventh MOSFET, and the eighth MOSFET. Is NMOS, the third MOSFET, the fourth MOSFET, the fifth MOSFET and the sixth MOSFET, the first TAIL MOSFET and the second TAIL MOSFET are PMOS, and the LC VCO overall circuit is the first node. Serial between ground and ground A first buffer circuit having a second inductor and a ninth MOSFET connected to the node (the positive output node is located between the second inductor and the ninth MOSFET) and a third inductor connected in series between the first node and the ground; And a second buffer circuit (the (-) output side node located between the third inductor and the tenth MOSFET) of the tenth MOSFET, and the gates of the ninth MOSFET and the tenth MOSFET are respectively the second node. And a ninth MOSFET and the tenth MOSFET, which are NMOS, for an 8-10.9 GHz band LC VCO for a SONET communication system.

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In addition, the first inductor is a spiral inductor, the varactor is an accumulation mode varactor, which is configured by replacing p + of the source and drain electrodes of the PMOS transistor with n +, and connects a bulk to n + diffusion and applies a control voltage thereto. .

Further, the first voltage source and the second voltage source are preferably 3.3V and 1V, respectively.

According to the 8 ~ 10.9GHz band LC VCO for SONET communication system according to an embodiment of the present invention, NMOS cross-coupled and PMOS active load technology is applied in the conventional cross-coupled LC VCO method using a 0.35㎛ CMOS process This provides an 8 to 10.9GHz band LC VCO for new SONET communication systems with wide tuning range and low phase noise.

The 8-10.9 GHz band LC VCO for SONET communication system according to an embodiment of the present invention has a tuning range of 29% from 8 GHz to 10.9 GHz, and the phase noise characteristics are simulated using Specter-RF. When oscillating with frequency, it has phase noise characteristics of -117dBc / Hz and -137dBc / Hz at offset frequencies of 1MHz and 10MHz, respectively. The FOM, which is widely used to compare with other conventional LC VCOs, is -189dBc / Hz @ 1MHz in the 10GHz band.

Therefore, the technical content of the present invention is very useful for 10Gb / s clock and data recovery circuits and SONET communication applications.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the present specification and claims should not be construed as being limited to the common or dictionary meanings, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

First, it will be described with reference to FIG. 3. 3 is a circuit diagram of an LC VCO according to an embodiment of the present invention having a wide tuning range and low phase noise according to an embodiment of the present invention.

The LC VCO structure proposed in the present invention is an NMOS cross-coupled (seventh and eighth MOSFETs (M7, M8)) and a PMOS active load (a fifth MOSFET and a sixth MOSFET). It is designed to have wide tuning range and low phase noise by applying M5, M6)) technology. As shown in FIG. 3, when the PMOS TR and the NMOS TR are symmetrically implemented, the Gm becomes the same to reduce phase noise, and the frequency can be changed by adjusting the voltage of the varactor. In order to reduce phase noise, the VCO output saturates the operating point to keep the output symmetrical to improve the phase noise. As can be seen in FIG. 1, unlike the prior art, the LC VCO of the present invention is composed of different first and second voltage sources VDD1 and VDD2, respectively.

The first voltage source VDD1 is for powering each loop of the LC VCO, and the second voltage source VDD2 is in the inner loop for phase noise optimization. The second voltage source VDD2 is applied at 1V, and the external first voltage source VDD1 is set at 3.3V. In addition, the output buffers (Buffer 1, Buffer 2) are connected to the output of the LC VCO to vary the oscillation frequency due to the gate loading effect to obtain the desired characteristics. NMOS (ninth MOSFET, tenth MOSFET (M9, M10)) having high conductance was used, and inductors indicated by dotted lines (second inductor and third inductor (I1, I2)) were designed outside the chip for impedance matching. .

The structure as shown in FIG. 3 connects an NMOS latch (first and second MOSFETs (M1 and M2)) and a PMOS latch (third and fourth MOSFETs (M3 and M4)) to compensate for the loss of the LC tank. By reusing the current, phase noise characteristics are improved compared to power consumption. In addition, the proposed structure has a larger oscillation swing voltage at the same power consumption than other structures, less influence of power supply noise and substrate noise, and excellent symmetry between the rise time and fall time of the oscillation waveform. The influence of noise was also based on a widely used method with a small structure.

The use of PMOS as the current source of the first and second TAIL MOSFETs (M _tail1 and M _tail2 ) is because the PMOS has less flicker noise than the NMOS, and the capacitor C _tail has high frequency components of the PMOS transistor used as the tail current source. Inserted to suppress affecting nodes.

The first inductor of the LC VCO of the present invention uses a spiral inductor, and the varactor is an accumulation mode varactor made by replacing p + of the source and drain electrodes of the PMOS transistor with n +. In addition, when bulk is connected to n + diffusion and a control voltage is applied to it, a depletion layer is formed under the gate. At this time, the control voltage is changed to change the capacitance.

MOS varactors have high linearity and wide tuning range, making them popular. Since the present invention does not provide an RF model of the accumulation mode selector, it is simulated by changing the L / W ratio of the PMOS using a Specter RF tool. The results are shown in FIG. In gated mode varactors, shorter gate lengths reduce series resistance, resulting in higher Q value and improved phase noise characteristics, while narrower tuning ranges between tunable ranges and Q values affecting phase noise. The length of the gate was determined by considering the trade-off relationship.

(Simulation and result)

The new LC VCO proposed by the present invention was designed in 3.3V supply voltage, external voltage 1V and 0.35㎛ CMOS process using Cadence's Specter-RF tool. 5 is a diagram illustrating a frequency spectrum simulation of a center frequency of 10.2 GHz, and FIG. 6 is a diagram illustrating a tuning range of an LC VCO structure according to the present invention having a wide tuning range and low phase noise. In general, the definition of the tuning range required by the RF system is shown in Equation 2.

Equation 2

In Equation 2, f _center is the oscillation center frequency of 10GHz. The LC VCO's tuning range is designed for a wide tuning range of LC VCOs, taking into account the process error of capacitance when parasitic capacitors are placed on the chip and the parasitic capacitance values of inductors and MOS transistors. As shown in FIG. 6, the LC VCO according to an embodiment of the present invention has a tuning range of 29% from 8 GHz to 10.9 GHz. FIG. 7 illustrates the design of an LC VCO according to an embodiment of the present invention, which simulates phase noise using Cadence's Specter-RF. When oscillating at a frequency of 10 GHz, -117 dBc / Phase noise characteristics of Hz and -137dBc / Hz. Equation 3 shows the phase noise mathematically. Where q _max represents the maximum signal amplitude and Δω represents the offset frequency from the carrier signal.

Equation 3

When a constant voltage is input to the LC VCO according to an embodiment of the present invention, a constant clock is output. In FIG. 8, when an ideal clock is input, about 3.3 V is input, 10.2 GHz is output. After checking it, attach a voltage source to the VCO input terminal and input and change 3.3V, which is 0V to VDD, and measure the period that comes out each time. In order to identify the worst case during the Coner Simulation, the VCO gain characteristic curves are different for each fast type, typical type, and slow type because the supply voltage is also changed. 9 is a diagram illustrating a layout of an LC VCO according to an embodiment of the present invention. The layout core size is 270 μm × 340 μm. Basic layout considerations for high frequency VCOs are important, as a top priority, to make the differential characteristics of the VCO structure fully symmetrical.

LC VCO according to an embodiment of the present invention is a figure of merit (FOM) that is widely used to compare with other LC VCO is defined by Equation 4.

Equation 4

L {Δf} is the phase noise at offset from the carrier and P is the power consumption of the LC VCO core. The FOM of this design with a 3.3 V supply voltage is -189 dBc / Hz @ 1 MHz in the 10 GHz band. Table 1 shows the results of comparing the phase noise and tuning range characteristics of the LC VCO according to an embodiment of the present invention, Table 2 shows the results of the LC VCO and the prior art 1, 2, 3 according to an embodiment of the present invention This is a comparison table. For reference, the prior art 1 is Tae-young Choi; Hanil Lee; Katehi, L. P. B .; Mohammadi, S, "A low phase noise 10 GHz VCO in 0.18 um CMOS process" Wireless Technology, 2005. A technique disclosed in a paper published in The European Conference on, 273-276, 2005. Prior art 2, TP Liu, “A 1.5 V 10-12.5 GHz Integrated CMOS Oscillators,” IEEE Symposium on VLSI Circuits, pp. 55-56, 1999. A technique disclosed in a paper contributed to R. Murji and JM Deen, “A Low-Power, 10 GHz Back-Gated Tuned Voltage Controlled Oscillator with Automatic Amplitude and Temperature Compensation,” A technique disclosed in a paper published in ISCAS 2004, Vancouver, BC, Canada, 4 pages, (23-26 May, 2004).

Table 1. Comparison of Phase Noise and Tuning Range of VCOs

Technology 0.35㎛ CMOS Supply Voltage 3.3V Tuning range 29% (8 GHz to 10.9 GHz) KVCO <2.06 GHz / V Power consumption 6.48mW Phase noise -117 dBc / Hz @ 1M offset, -137 dBc / Hz @ 10M offset Figure of merit (FOM) -189 dBc / Hz @ 1M offset, -194 dBc / Hz @ 10M offset Chip Size 270 μm x 340 μm

Table 2. Comparison of Results for VCOs

Invention Prior art 1 Prior art 2 Prior art 3 Tuning range (GHz) 29%
8.0-10.9 20.1% 10.2-12.5 20.5%
10-12.5 5%
9.5-10 Phase noise (1 MHz) -117 dBc / Hz -125 dBc / Hz -106 dBc / Hz -102 dBc / Hz FOM (dBc / Hz) -189 -188 -151 -161 Power consumption 6.48mW 50 mW 45 mW 3.7 mW

In the present invention, a new LC VCO with wide tuning range and low phase noise is proposed and designed by applying NMOS cross-coupled and active load technology in the conventional cross-coupled LC VCO using 0.35㎛ CMOS process. .

The LC VCO proposed in the present invention has a tuning range of 29% from 8 GHz to 10.9 GHz, and the phase noise characteristics are simulated using Specter-RF. When oscillating at a frequency of 10 GHz, the offset frequency of 1 MHz and 10 MHz is- It has phase noise of 117dBc / Hz and -137dBc / Hz. A widely used FOM for comparison with other LC VCOs is -189dBc / Hz @ 1MHz in the 10GHz band.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications, changes and variations are possible within the scope of the claims to be described.

1 is a block diagram showing the structure of a general optical communication receiver.

2 is a circuit diagram showing a general cross-coupled LC VCO structure.

3 is a circuit diagram of an LC VCO proposed in the present invention having a wide tuning range and a low phase shift according to an embodiment of the present invention.

4 is a diagram showing a tuning range of the accumulation mode varactor.

5 shows a frequency spectrum simulation of a center frequency of 10.2 GHz.

6 is a view showing a tuning range of the LC VCO structure according to the present invention having a wide tuning range and low phase noise.

7 illustrates phase noise of an LC VCO according to an embodiment of the present invention.

8 is a view showing the results of Coner Simulation of the LC VCO according to an embodiment of the present invention.

9 illustrates a layout of an LC VCO according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

node 1 first node

M1 first MOSFET

M2 2nd MOSFET

M3 3rd MOSFET

M4 4th MOSFET

M5 fifth MOSFET

M6 6th MOSFET

M7 7th MOSFET

M8 8th MOSFET

M9 9th MOSFET

M10 10th MOSFET

M _tail1 1st TAIL MOSFET

M _tail2 2nd TAIL MOSFET

VDD1 first voltage source

VDD2 second voltage source

Inductor first inductor

I1, I2 second inductor, third inductor

Buffer 1 First output buffer circuit

Buffer 2 2nd output buffer circuit

Control voltage of Vctrl varactor

Vout + (+) Output Node

Vout- (-) Output Node

NMOS CORE on M1 ', M2' Prior Art

M3 ', M4' Prior Art PMOS CORE

Claims (8)

A first current source for supplying current to the entire LC VCO circuit; A first node existing between said first current source and an LC VCO overall circuit; An LC VCO overall circuit connected between the first node and ground, The entire LC VCO circuit, A third MOSFET and a fourth MOSFET, each of which has a drain connected to the first node and whose source is connected to a second node and a third node, respectively; First and second MOSFETs each having a source connected to a second node and a third node, each drain of which is connected to a second current source; A first inductor connected between the second node and the third node; A varactor connected between the second node and the third node, An NMOS cross-coupled circuit connected to the source and gate of each of the third and fourth MOSFETs; A PMOS active load circuit connected to the NMOS cross coupled circuit; A gate of the first MOSFET is connected to a third node, a gate of the second MOSFET is connected to a second node, the second current source is grounded at one side to ground, The PMOS active load circuit includes a fifth MOSFET and a sixth MOSFET to which a second voltage source and respective drains are connected, and each of the fifth and sixth MOSFETs has its gate and source connected to each other.  The NMOS cross-coupled circuit includes a seventh MOSFET and an eighth MOSFET, each of which is connected to a source of the fifth and sixth MOSFETs, and the gate of the seventh MOSFET is a gate of the fourth MOSFET. And a gate of the eighth MOSFET are connected to a gate of the third MOSFET and a third node, and drains of the seventh and eighth MOSFETs are respectively grounded to ground. The PMOS active load circuit and the NMOS cross coupled circuit are implemented symmetrically with each other in order to reduce phase noise, and the transistors have the same Gm, The first current source may include a first TAIL MOSFET (M _tail1 ) and a second TAIL MOSFET (M _tail2 ) connected to a first voltage source, the first voltage source, and a drain thereof, the first TAIL MOSFET, and the second TAIL. A resistor for removing flicker noise between the first voltage source and the first node and a bias current source between the gate of the MOSFET, the bias current source between the source and ground of the first TAIL MOSFET, and the second TAIL MOSFET. A source of is connected to the LC VCO overall circuit at the first node, The first MOSFET, the second MOSFET, the seventh MOSFET and the eighth MOSFET are NMOS, and the third MOSFET, the fourth MOSFET, the fifth MOSFET and the sixth MOSFET, the first TAIL MOSFET and the The second TAIL MOSFET is a PMOS, The LC VCO overall circuit comprises a first buffer circuit comprising a second inductor and a ninth MOSFET connected in series between the first node and ground (the positive output node is located between the second inductor and the ninth MOSFET). And a second buffer circuit comprising a third inductor and a tenth MOSFET connected in series between the first node and ground (the (-) output side node is located between the third inductor and the tenth MOSFET), Gates of the ninth MOSFET and the tenth MOSFET are connected to the second node and the third node, respectively, and the ninth MOSFET and the tenth MOSFET are NMOS, 8 to 10.9 GHz band for the SONET communication system. LC VCO. delete delete delete delete delete The method of claim 1, The first inductor is a spiral inductor, the varactor is an accumulation mode varactor, and is configured by replacing p + of the source and drain electrodes of the PMOS transistor with n +, and bulk is connected to n + diffusion, and a control voltage is applied thereto. 8 V to 10.9 GHz band LC VCO for SONET communications systems. The method of claim 7, wherein The LC VCO of the 8 ~ 10.9GHz band for SONET communication system, characterized in that the first voltage source and the second voltage source is 3.3V and 1V, respectively.

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