KR100983825B1

KR100983825B1 - ?-nitride semiconductor light emitting device

Info

Publication number: KR100983825B1
Application number: KR1020050094082A
Authority: KR
Inventors: 김창태; 유태경
Original assignee: 주식회사 에피밸리
Priority date: 2005-10-07
Filing date: 2005-10-07
Publication date: 2010-09-27
Also published as: KR20070038794A

Abstract

The present invention relates to a group III nitride semiconductor light emitting device, comprising: a p-side electrode formed on a plurality of nitride semiconductor layers; And a p-side bonding pad in electrical contact with the p-side electrode for wire bonding, wherein the p-side electrode includes a first region in which the p-side bonding pad is in direct contact with the plurality of nitride semiconductor layers. A group III nitride semiconductor light emitting device is provided, wherein a second region in which a p-side electrode contacts a plurality of nitride semiconductor layers is formed.

Light emitting element, light emitting diode, nitride semiconductor, active layer, bonding pad

Description

Group III nitride semiconductor light emitting device {Ⅲ-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE}

1 is a plan view showing a conventional Group III nitride semiconductor light emitting device,

2 is a cross-sectional view showing a conventional Group III nitride semiconductor light emitting device;

3 is a plan view showing a group III nitride semiconductor light emitting device according to the present invention;

4 is a cross-sectional view showing a group III nitride semiconductor light emitting device according to the present invention;

5 is a view showing another example of the group III nitride semiconductor light emitting device according to the present invention;

The present invention relates to a group III nitride semiconductor light emitting device, and more particularly, to a structure in which a transparent electrode is partially disposed between a bonding pad and a p-type semiconductor yarn to improve an operating voltage of the device.

Here, the group III nitride semiconductor light emitting device has a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Means a light emitting device, such as a light emitting diode including a, and additionally excludes that the semiconductor layer or the material itself of the other group elements, such as SiC, SiN, SiCN, CN, etc. It is not.

1 and 2 are diagrams illustrating a conventional group III nitride semiconductor light emitting device, wherein the light emitting device is epitaxially grown on the substrate 100, the substrate 100, and an n-type epitaxially grown on the buffer layer 200. The nitride semiconductor layer 300, the active layer 400 epitaxially grown on the n-type nitride semiconductor layer 300, the p-type nitride semiconductor layer 500 epitaxially grown on the active layer 400, and the p-type nitride semiconductor layer 500 The p-side electrode 600 formed on the entire surface, the p-side bonding pad 700 formed on the p-side electrode 600, at least the p-type nitride semiconductor layer 500 and the active layer 400 are mesa-etched and exposed. And an n-side electrode 800 formed on the type nitride semiconductor layer 301. In FIG. 1, reference numeral 701 denotes a portion where the p-side bonding pad 700 is in direct contact with the p-type nitride semiconductor layer 500.

As the substrate 100, a GaN-based substrate is used as the homogeneous substrate, and a sapphire substrate, a silicon carbide substrate, or a silicon substrate is used as the heterogeneous substrate. Any substrate may be used as long as the nitride semiconductor layer can be grown. When the silicon carbide substrate is used, the n-side electrode 800 may be formed on the silicon carbide substrate side.

The nitride semiconductor layers epitaxially grown on the substrate 100 are mainly grown by MOCVD (organic metal vapor growth method).

The buffer layer 200 is for overcoming the difference in lattice constant and thermal expansion coefficient between the dissimilar substrate 100 and the nitride semiconductor, and US Pat. A technique for growing an AlN buffer layer is disclosed. U.S. Patent No. 5,290,393 discloses Al (x) Ga (1-x) N (with a thickness of 10 kPa to 5000 kPa at a temperature of 200C to 900C on a sapphire substrate. A technique for growing a 0? X <1) buffer layer is disclosed, and Korean Patent No. 10-0448352 discloses growing a SiC buffer layer at a temperature of 600 ° C. to 990 ° C., followed by In (x) Ga (1-x). Techniques for growing an N (0 <x ≦ 1) layer are disclosed.

In the n-type nitride semiconductor layer 300, at least a region (n-type contact layer) on which the n-side electrode 800 is formed is doped with an impurity, and the n-type contact layer is preferably made of GaN and doped with Si. U.S. Patent No. 5,733,796 discloses a technique for doping an n-type contact layer to a desired doping concentration by controlling the mixing ratio of Si and other source materials.

The active layer 400 is a layer that generates photons (light) through recombination of electrons and holes, and is mainly composed of In (x) Ga (1-x) N (0 <x≤1), and one quantum well layer (single quantum wells) or multiple quantum wells. WO02 / 021121 discloses a technique for doping only a portion of a plurality of quantum well layers and barrier layers.

The p-type nitride semiconductor layer 500 is doped with an appropriate impurity such as Mg, and has a p-type conductivity through an activation process. US Patent No. 5,247,533 discloses a technique for activating a p-type nitride semiconductor layer by electron beam irradiation, and US Patent No. 5,306,662 discloses a technique for activating a p-type nitride semiconductor layer by annealing at a temperature of 400 ° C or higher. Korean Patent No. 10-043346 discloses a technique in which a p-type nitride semiconductor layer has p-type conductivity without an activation process by using NH ₃ and a hydrazine-based source material together as a nitrogen precursor for growth of a p-type nitride semiconductor layer. Is disclosed.

The p-side electrode 600 is provided to provide a good current to the entire p-type nitride semiconductor layer 500. US Patent No. 5,563,422 is formed over almost the entire surface of the p-type nitride semiconductor layer and is a p-type nitride semiconductor. A light transmissive electrode is disclosed which is in ohmic contact with a layer and is made of Ni and Au. US Pat. No. 6,515,306 discloses an n-type superlattice layer formed on a p-type nitride semiconductor layer and then indium tin oxide (ITO) thereon. Disclosed is a technique in which a translucent electrode is formed.

On the other hand, the p-side electrode 600 may be formed to have a thick thickness so as not to transmit light, that is, to reflect the light toward the substrate side, the light emitting element using the p-side electrode 600 is flip chip (flip chip) This is called. U. S. Patent No. 6,194, 743 discloses a technique for an electrode structure including an Ag layer having a thickness of 20 nm or more, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al covering the diffusion barrier layer.

The p-side bonding pad 700 and the n-side electrode 800 are for supplying current and wire bonding to the outside, and US Patent No. 5,563,422 discloses a technique in which the n-side electrode 800 is composed of Ti and Al. US Patent No. 5,652, 434 discloses a technique in which a part of the light transmitting electrode is removed so that the p-side bonding pad is directly in contact with the p-type nitride semiconductor layer.

Meanwhile, an additional n-type nitride semiconductor layer may be provided between the p-type nitride semiconductor layer 500 and the p-side electrode 600, and WO 2005/086244 discloses a SiCN semiconductor layer doped with high concentration. The technique which lowered the drive voltage of an element is disclosed.

As shown in FIG. 2, when the lower portion of the p-side bonding pad 700 is in direct contact with the p-type nitride semiconductor layer 500, a metal such as aluminum or chromium, which is generally used as the p-side bonding pad 700, is p. The nitride semiconductor layer 500 has a Schottky junction characteristic. Therefore, at a constant driving current, the current density to this portion is lowered, and the current density flowing to the p-side electrode 600 becomes higher and the driving voltage is higher when viewed as a whole. In addition, when the p-side electrode 600 is formed entirely on the lower side of the p-side bonding pad 700 (when the p-side bonding pad 700 is formed on the p-side electrode 600), the p-side bonding pad ( 700) The phenomenon that the current is driven down occurs, which degrades the reliability and performance of the device.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to improve the operating voltage and reliability of an element by partially arranging the p-side electrode between the p-side bonding pad and the p-type nitride semiconductor layer.

To this end, the present invention is a group III nitride semiconductor light emitting device having a plurality of nitride semiconductor layers including an active layer for generating light by recombination of electrons and holes, p-side electrode formed on the plurality of nitride semiconductor layers; And a p-side bonding pad in electrical contact with the p-side electrode for wire bonding, wherein the p-side electrode includes a first region in which the p-side bonding pad is in direct contact with the plurality of nitride semiconductor layers. A group III nitride semiconductor light emitting device is provided, wherein a second region in which a p-side electrode contacts a plurality of nitride semiconductor layers is formed.

In another aspect, the present invention provides a group III nitride semiconductor light emitting device characterized in that the second region is cross-shaped.

The present invention also provides a group III nitride semiconductor light emitting device characterized in that the second region is a mesh (mesh).

In another aspect, the present invention provides a Group III nitride semiconductor light emitting device, characterized in that the second region is in the form of a plurality of stripes.

In another aspect, the present invention provides a group III nitride semiconductor light emitting device, characterized in that the first region is in ohmic contact with the plurality of nitride semiconductor layers.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

3 and 4 are diagrams showing an example of a group III nitride semiconductor light emitting device according to the present invention, wherein a buffer layer 20, an n-type nitride semiconductor layer 30, an active layer 40, and p are disposed on a substrate 10. The type nitride semiconductor layer 50 is sequentially grown epitaxially. The p-side electrode 60 and the p-side bonding pad 70 are formed on the p-type nitride semiconductor layer 50, and the n-side electrode 80 is formed on the mesa-etched n-type nitride semiconductor layer 31. . In the light emitting device according to the present invention, the p-side electrode 60 is partially formed between the p-side bonding pad 70 and the p-type nitride semiconductor layer 50. In FIG. 3, reference numeral 71 denotes a portion where the p-side bonding pad 70 is in direct contact with the p-type nitride semiconductor layer 50. Here, the active layer 40 is a layer that generates light by recombination of electrons and holes. The p-side electrode 60 is arranged in a cross shape, a mesh shape, or a plurality of stripes in a portion where the p-side bonding pad 70 and the p-type nitride semiconductor layer 50 are in contact with each other (first region). The ohmic contact (second region) 61 was made to flow a certain amount of current while preventing excessive current injection, thereby improving the reliability and performance of the device.

5 is a view showing another example of the group III nitride semiconductor light emitting device according to the present invention. Unlike the light emitting device of FIG. 4, an n-type semiconductor layer (between the p-type nitride semiconductor layer 50 and the p-side electrode 60) 90). This device configuration is particularly helpful in improving the electrical contact between the p-type nitride semiconductor layer 50 and the p-side electrode 60 when the p-side electrode 60 is formed of a metal oxide such as ITO. Preferably, the n-type semiconductor layer 90 may be made of a material such as GaN or SiC _x N _y .

The present invention improves the operating voltage of the device and the reliability of the device by disposing a transparent electrode partially between the p-side bonding pad and the p-type nitride semiconductor layer.

Claims

In a group III nitride semiconductor light emitting device having a plurality of nitride semiconductor layers including an active layer that generates light by recombination of electrons and holes,

A p-side electrode formed on the plurality of nitride semiconductor layers; And a p-side bonding pad in electrical contact with the p-side electrode for wire bonding.

The p-side electrode includes a first region in which the p-side bonding pad is in direct contact with the plurality of nitride semiconductor layers, and a second region in which the p-side electrode contacts the plurality of nitride semiconductor layers is formed in the first region. Group III nitride semiconductor light emitting device.

The group III nitride semiconductor light emitting device according to claim 1, wherein the second region is cross-shaped.

The group III nitride semiconductor light emitting device according to claim 1, wherein the second region is a mesh type (mesh type).

The group III nitride semiconductor light emitting device according to claim 1, wherein the second region has a plurality of stripe shapes.

The group III nitride semiconductor light emitting device according to claim 1, wherein the first region is in ohmic contact with the plurality of nitride semiconductor layers.

The group III nitride semiconductor light emitting device according to claim 1, further comprising an n-type semiconductor layer between the plurality of nitride semiconductor layers and the p-side electrode.