KR100982140B1 - Method for forming micro-pattern of semiconductor device - Google Patents

Abstract

The present invention is to provide a method of forming a fine pattern of a semiconductor device to reduce the process cost and prevent the pattern collapse, the present invention is the step of laminating the first, second, hard mask film on the substrate on which the etched layer is formed Forming a photoresist pattern on the second hard mask film, forming a silicon oxide film on the entire surface including the photoresist pattern at a temperature that does not cause deformation of the photoresist pattern, and performing oxygen plasma treatment on the silicon oxide film. Forming a spacer on the side surface of the photoresist pattern by etching the entire silicon oxide layer, removing the photoresist pattern, and etching the second hard mask layer using the spacer as a mask to form a second hard mask layer pattern. And a first hard mask film using a spacer and a second hard mask film pattern as a mask. Etching to provide a fine pattern formation method of a semiconductor device including a step of forming a first hard mask pattern.

Fine pattern, amorphous carbon film, silicon oxide film, oxygen plasma treatment

Description

METHOD FOR FORMING MICRO-PATTERN OF SEMICONDUCTOR DEVICE}

TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a method of forming a fine pattern having a pitch below a limit resolution.

As the design rule of the semiconductor device decreases, the minimum pitch of the pattern required for forming the semiconductor device also decreases significantly. However, the resolution of the lithography process used to implement the pattern does not support the reduction of design rules.

Particularly, excimer lasers of 153 nm wavelength or extreme ultra violet (EUV) lithography technologies having shorter wavelengths, which are required to form patterns of 30 nm or less, are still under development and are difficult to be used for actual pattern formation. Thus, a method of forming a fine pattern having a pitch below the limit resolution is introduced by using a SPT (Pacer Patterning Technology) scheme.

1A to 1G are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art using an SPT scheme.

First, as shown in FIG. 1A, the etched layer 12 is formed on the lower layer 11 formed on the substrate 10, and the first hard mask layer 13 is formed on the etched layer 12.

The first hard mask layer 13 is used as a hard mask in etching the etched layer 12 and should have an etching selectivity with respect to the etched layer 12. In addition, the spacer layer 16 (see FIG. 1D) to be formed later should have an etching selectivity. Ideally, an amorphous carbon film is suitable as the first hard mask film 13, and a laminated structure of a silicon oxynitride film (SiON) and an amorphous carbon film may be taken.

Subsequently, a second hard mask film 14 is formed on the first hard mask film 13. The second hard mask layer 14 is formed of a material having an etching selectivity with respect to the first hard mask layer 13 and the spacer layer 16 formed thereafter, for example, polysilicon.

Subsequently, a third hard mask film 15 is formed on the second hard mask film 14.

The third hard mask film 15 is formed of a laminated film of silicon oxynitride film (SiON) and amorphous carbon film.

Next, the photoresist pattern PR is formed on the third hard mask film 15. In this case, the space S between neighboring photoresist patterns PR may be three times or more than the line width L of the photoresist pattern PR.

Subsequently, as illustrated in FIG. 1B, the third hard mask layer 15 is etched using the photoresist pattern PR as an etch mask to form a third hard mask layer pattern 15A.

Next, as illustrated in FIG. 1C, the second hard mask layer 14 is etched using the photoresist pattern PR and the third hard mask layer pattern 15A as an etch mask to form the second hard mask layer pattern 14A. ).

Subsequently, as shown in FIG. 1D, the remaining photoresist pattern PR and the third hard mask layer pattern 15A are removed, and the spacer layer 16 is disposed on the entire surface including the second hard mask layer pattern 14A. To form.

The spacer layer 16 is formed of a material having an etch selectivity with respect to the second hard mask layer pattern 14A and the first hard mask layer 13, for example, polycrystalline silicon.

Subsequently, as shown in FIG. 1E, the spacer layer 16 is etched to the entire surface to form the spacer 16A on the side of the second hard mask layer pattern 14A. As a result of the entire surface etching process, the spacer layer 16 is left only on the side surface of the second hard mask layer pattern 14A. Accordingly, the first hard layer is disposed on the upper surface of the second hard mask layer pattern 14A and lower portions of both sides of the spacer 16A. The mask film 13 is exposed.

As a result of the above process, the pitch P2 of the spacer 16A becomes half the pitch P1 of the photoresist pattern PR.

Subsequently, as shown in FIG. 1F, the second hard mask layer pattern 14A is removed by a wet etching process, and the first hard mask layer 13 is etched using the spacer 16A as an etch mask to etch the first hard mask. The film pattern 13A is formed.

Then, as shown in Fig. 1G, the spacer 16A is removed.

Subsequently, although not shown, a fine pattern having a pitch P2 that is about half the pitch P1 of the photoresist pattern PR may be etched by etching the etching target layer 12 using the first hard mask layer pattern 13A as an etching mask. Form.

However, the above-described prior art uses two expensive amorphous amorphous carbon processes twice, and uses twice the amorphous amorphous carbon process and a spacer 16A made of nitride film, so that the number of process steps is about 20 to 25. There is a high problem.

In addition, in the etching process of the third hard mask layer 15 and the second hard mask layer 14, a thick photoresist pattern PR should be formed in order to secure an etching margin, since a thick photoresist pattern PR is used. Accordingly, there is a problem that the pattern aspect ratio is increased and is very vulnerable to pattern collapse.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of forming a fine pattern of a semiconductor device capable of reducing the number of expensive amorphous carbon processes and reducing the number of process steps. The purpose is.

Another object of the present invention is to provide a method for forming a fine pattern of a semiconductor device capable of preventing pattern collapse.

According to an aspect of the present invention, a first, second, and hard mask film are laminated on a substrate on which an etched layer is formed, and a photoresist pattern is formed on the second hard mask film. And forming a silicon oxide film on the entire surface including the photoresist pattern at a temperature that does not cause deformation of the photoresist pattern, subjecting the silicon oxide film to oxygen plasma treatment, and etching the silicon oxide film on the entire surface. Forming a spacer on a side surface of the pattern, removing the photoresist pattern, etching the second hard mask layer using the spacer as a mask, and forming a second hard mask layer pattern; The first hard mask layer is etched using the second hard mask layer pattern as a mask to form the first hard mask layer. Disk provides a fine pattern formation method of a semiconductor device including a step of forming a pattern film.

According to the present invention, it is possible to reduce the number of amorphous carbon processes, which is an expensive process, and to reduce the number of process steps, which were 20 or more, by 15 by omitting the third hard mask film, thereby reducing the device manufacturing cost. .

In addition, since the pattern aspect ratio can be reduced by lowering the height of the photoresist pattern, pattern collapse is prevented.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2A to 2F are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2A, the lower layer 21 is formed on the substrate 20, and the etched layer 22, the first hard mask layer 23, and the second hard mask layer are formed on the lower layer 21. (24) are laminated and the photoresist pattern PR is formed on the second hard mask film 24.

The lower layer 21 may be any one of a gate insulating layer, a gate electrode layer, a bit line layer, or a metal line layer. In the case of the gate insulating layer, the lower layer 21 may be an oxide film, an oxynitride film, or a high-k film. In the case of the gate electrode layer, the lower layer 21 may have a stacked structure of conductive polycrystalline silicon, tungsten (W) or tungsten silicide (WSix) and a barrier metal. In the case of the bit line layer or the metal line layer, the lower layer 21 may have a stacked structure of a metal such as tungsten (W) or aluminum (Al) and a barrier metal.

The etched layer 22 may be a hard mask layer for an actual pattern such as a gate, a bit line, a metal line or an active pattern. The etched layer 22 may include, for example, a thermal oxide layer, a chemical vapor deposition (CVD) oxide film, an atomic layer deposition (ALD) oxide film, a high density plasma plasma (HDP) oxide film, an undoped silica glass (USG), and spin (SOG). On glass) or a nitride such as SiON, SiN, SiBN, BN, or the like.

The first hard mask film 23 may be formed of an amorphous carbon film having a high etching selectivity with respect to the etching target layer 22. Further, a silicon oxynitride layer (SiON) may be further included below the amorphous carbon layer to serve as an etch stopper when the first hard mask layer 23 is etched.

The second hard mask layer 24 may be formed of a material having an etch selectivity with respect to the first hard mask layer 23 and the spacer layer 25 (see FIG. 2B) formed later, for example, polycrystalline polysilicon. have.

The photoresist pattern PR may be formed by applying a photoresist on the second hard mask layer 24 and patterning the photoresist in an exposure and development process. Meanwhile, an antireflection layer (not shown) may be further formed on the second hard mask film 24 before applying the photoresist.

At this time, the space S between the photoresist patterns PR is set to be three times or more the line width L of the photoresist pattern PR. That is, the relationship of S≥3L is satisfied.

Subsequently, as shown in FIG. 2B, a silicon oxide film is deposited on the entire surface including the photoresist pattern PR to form a spacer film 25.

The spacer film 25 must satisfy the following requirements.

First, since the photoresist pattern PR should not be deformed during the deposition of the spacer layer 25, the photoresist pattern PR should be able to be formed at a low temperature. Third, it must have a high etching selectivity with respect to the photoresist pattern PR and the second hard mask film 24.

The spacer layer 25 is an atomic layer deposition (ALD) process and a molecular layer deposition process having good applicability at a temperature that does not cause deformation of the photoresist pattern PR, for example, a cryogenic temperature of 25 to 150 ° C. It can be formed as.

When using an atomic layer deposition (ALD) process or a molecular layer deposition process, silicon and oxygen sources are used as reaction gases, and silicon and oxygen sources are continuously introduced into a process chamber containing a substrate. do.

Looking specifically at the process, the silicon source is first introduced into the process chamber and adsorbed onto the surface of the substrate structure. Oxygen source is then introduced into the process chamber and reacted with the silicon source to form silicon oxide. The spacer film 25 made of the silicon oxide film is formed by repeating the silicon source introduction process and the oxygen source introduction process in one cycle and the cycle is repeated at least once. In addition, a purge step is performed between the processes in which each reaction gas is introduced.

Silicon sources include Hexa-Chlorine-Disilane, Si ₂ Cl ₆ , TCS (SiCl ₄ ), Bt-BAS, TriDMAS (Tri-DiMethylAminoSilane, C ₆ H ₁₉ N ₃ Si), TSA (TriSylilAmine, (SiH ₃ ) ₃ N) or DS (Di-Silane, Si ₂ H ₆ ) may be used, and as the oxygen source, any one of O ₂ , H ₂ O, and O ₃ may be used.

In addition, a catalyst may be further used in addition to the silicon source and the oxygen source to improve the process reaction temperature or the deposition rate. As the catalyst, any one of pyridine (C ₅ H ₅ N) containing an amine group (Amine), ammonia (NH ₃ ) or a metal component (Tri-Methalen-Aluminum, TMA) containing aluminum may be used. .

For example, the spacer layer 25 processes silicon and oxygen sources together with a catalyst using HDC as a silicon source, water vapor (H ₂ O) as an oxygen source, and pyridine (C ₅ H ₅ N) as a catalyst. A method of depositing a silicon oxide film in an atomic layer deposition process continuously introduced into a chamber, using BT-BAS or TriDMAS as a silicon source and using oxygen radical or ozone (O ₃ ) activated by plasma with an oxygen source. The silicon oxide film may be formed by an atomic layer deposition process or a molecular layer deposition process in which a silicon source and an oxygen source are continuously introduced into a process chamber including a substrate.

Meanwhile, the spacer layer 25 may be formed by a catalytic chemical vapor deposition process. For example, aluminum may be adsorbed onto the surface of the photoresist pattern PR using TMA and then formed by a catalytic chemical vapor deposition process in which organo-silicate is deposited.

3 is a photograph of the device cross-section after the spacer film 25 is formed, and it can be seen that the deposition of the spacer film 25 having excellent applicability without deformation of the photoresist pattern PR is performed.

Since the spacer layer 25 is used as a hard mask during the subsequent photoresist pattern PR removal process and the etching process of the second hard mask layer 24, the spacer layer 25 may be used for the photoresist pattern PR and the second hard mask layer 24. It should have a high etching selectivity. However, since the silicon oxide film constituting the spacer film 25 is deposited at a low temperature, it does not guarantee a high etching selectivity for the photoresist pattern PR and the second hard mask film 24.

Thus, as shown in FIG. 2C, the spacer layer 25 is subjected to oxygen plasma treatment so as to have a high etching selectivity with respect to the photoresist pattern PR and the second hard mask layer 24.

At this time, the oxygen plasma (O ₂ ^* , O ^* ) may be formed using any one of a RF plasma (Radio Frequency Plasma), a capacitor coupling (capacitor coupling), a remote plasma (remote plasma).

The process is appropriately controlled so that the lower photoresist pattern PR is not oxidized during the oxygen plasma treatment.

4 is a view illustrating a change in the etch rate of a silicon oxide layer according to a method of forming a silicon oxide layer, wherein the spacer layer 25 is etched during a subsequent photoresist pattern PR and an etching process of the second hard mask layer 24. Indicates.

The silicon oxide film case3 deposited at cryogenic temperature has a higher etching rate than the silicon oxide films case 1 and case 2 formed by thermal oxidation or CVD. That is, the silicon oxide film deposited at cryogenic temperatures cannot be used as a hard mask because a large amount is etched during the photoresist pattern PR removal process and the second hard mask film 24 etching process. However, when the silicon oxide film deposited at cryogenic temperature is subjected to oxygen plasma treatment (case 5), the etching rate is lowered, and thus the etching rate is lower than that of the silicon oxide film case 2 formed by the CVD method.

Based on this, it can be seen that the spacer layer 25 has high etching resistance to the subsequent photoresist pattern PR removal process and the second hard mask layer 24 etching process through the process of FIG. 2C. Can be.

Subsequently, as shown in FIG. 2D, the spacer layer 25 is etched to the entire surface to form the spacer 25A on the sidewall of the photoresist pattern PR.

As a result of the entire surface etching process, the upper surface of the photoresist pattern PR and the second hard mask layer 24 under both sides of the spacer 25A are exposed. The pitch P2 of the spacer 25A is half of the pitch P1 of the photoresist pattern PR.

Next, as shown in FIG. 2E, the photoresist pattern PR is removed. The photoresist pattern PR may be removed using an oxygen plasma.

Next, the second hard mask layer 24 is etched using the spacers 25A as a mask to form the second hard mask layer pattern 24A.

Subsequently, as shown in FIG. 2F, the first hard mask layer 23 is etched using the spacer 25A and the second hard mask layer pattern 24A as an etch mask to form the first hard mask layer pattern 23A. Then, the remaining spacer 25A and the second hard mask film pattern 24A are removed.

Subsequently, although not shown, the etching target layer 22 is patterned using the first hard mask film pattern 23A as a mask.

According to the present invention, since the number of expensive amorphous carbon processes can be reduced, device manufacturing costs are reduced. In addition, since the third hard mask film is omitted, the number of process steps that have been 20 or more steps can be reduced to about 15 steps, thereby reducing the device manufacturing cost.

In addition, since the photoresist pattern PR is not used as an etching mask, it is not necessary to form a thick photoresist pattern as in the prior art, thereby reducing the pattern aspect ratio and preventing pattern collapse.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

3 is a photograph taken of the element cross section after the spacer film is formed.

4 is a view illustrating an etching rate change of a silicon oxide film according to a method of forming a silicon oxide film.

Description of the Related Art

20: substrate

21: lower layer

22: etched layer

23, 24: 1st, 2nd hard mask film

23A, 24A: First and second hard mask film patterns

25 spacer film

25A: spacer

Claims (16)

Stacking first and second hard mask layers on a substrate on which an etched layer is formed; Forming a photoresist pattern on the second hard mask film; Forming a silicon oxide film on the entire surface including the photoresist pattern at a temperature that does not cause deformation of the photoresist pattern; Oxygen plasma treating the silicon oxide film; Etching the entire silicon oxide layer to form a spacer on a side surface of the photoresist pattern; Removing the photoresist pattern; Etching the second hard mask layer using the spacers as a mask to form a second hard mask layer pattern; Etching the first hard mask layer using the spacers and the second hard mask layer pattern as a mask to form a first hard mask layer pattern Method for forming a fine pattern of a semiconductor device comprising a. The method of claim 1, After the forming of the first hard mask film pattern, Removing the spacers and the second hard mask layer pattern; Etching the etched layer using the first hard mask layer pattern as a mask Method of forming a fine pattern of a semiconductor device further comprising. The method of claim 1, The method of forming a fine pattern of a semiconductor device to form the silicon oxide film at a temperature of 25 to 150 ℃. The method of claim 1, And forming the silicon oxide film using any one of an atomic layer deposition process, a molecular layer deposition process, or a catalytic chemical vapor deposition process. The method of claim 4, wherein The method of forming a fine pattern of a semiconductor device using a silicon source and an oxygen source as a reaction gas in the atomic layer deposition process or molecular layer deposition process. The method of claim 5, Introducing the silicon source and adsorbing the entire surface including the photoresist pattern; In one cycle, the oxygen source is introduced and reacted with the adsorbed silicon source to form silicon oxide. Forming the silicon oxide film by repeating the cycle at least once or more times. The method of claim 6, And purging between the silicon source and the step of introducing the oxygen source. The method of claim 5, The silicon source may be HCD (Si ₂ Cl ₆ ), TCS (SiCl ₄ ), TriDMAS (C ₆ H ₁₉ N ₃ Si), BT-BAS, TSA ((SiH ₃ ) ₃ N) or DS (Si ₂ H ₆ ) Method for forming a fine pattern of a semiconductor device using any one. The method of claim 5, The method of forming a fine pattern of a semiconductor device using any one of O ₂ , H ₂ O, O ₃ as the oxygen source. The method of claim 5, The method of forming a fine pattern of a semiconductor device using a catalyst in addition to the silicon source and the oxygen source. The method of claim 10, The method of forming a fine pattern of a semiconductor device using any one of a metal material containing a pyridine (pryridine) containing a amine group, ammonia, aluminum as the catalyst. The method of claim 4, wherein And forming a silicon oxide layer by adsorbing a metal material including aluminum on the entire surface including the photoresist pattern and depositing an organo silicate during the catalytic chemical vapor deposition process. The method of claim 1, The method of forming a fine pattern of a semiconductor device to control the photoresist pattern is not oxidized during the oxygen plasma treatment. The method of claim 1, The method of forming a fine pattern of a semiconductor device using an oxygen plasma to remove the photoresist pattern. The method of claim 1, And forming the first hard mask film as a single film of an amorphous carbon film or a laminated film of a silicon nitride oxide film and an amorphous carbon film. The method of claim 1, The method of forming a fine pattern of a semiconductor device, wherein the second hard mask film is formed of polycrystalline polysilicon.

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