KR100980536B1 - 멀티스레디드 프로세서에서 스레드-방식 메모리 액세스를위한 방법 및 장치 - Google Patents

멀티스레디드 프로세서에서 스레드-방식 메모리 액세스를위한 방법 및 장치 Download PDF

Info

Publication number
KR100980536B1
KR100980536B1 KR1020057005888A KR20057005888A KR100980536B1 KR 100980536 B1 KR100980536 B1 KR 100980536B1 KR 1020057005888 A KR1020057005888 A KR 1020057005888A KR 20057005888 A KR20057005888 A KR 20057005888A KR 100980536 B1 KR100980536 B1 KR 100980536B1
Authority
KR
South Korea
Prior art keywords
memory
thread
processor
multithreaded processor
thread identifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1020057005888A
Other languages
English (en)
Korean (ko)
Other versions
KR20050046819A (ko
Inventor
에르뎀 호케넥
마얀 모우드길
존 씨. 글로스너
Original Assignee
샌드브리지 테크놀로지스, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 샌드브리지 테크놀로지스, 인코포레이티드 filed Critical 샌드브리지 테크놀로지스, 인코포레이티드
Publication of KR20050046819A publication Critical patent/KR20050046819A/ko
Application granted granted Critical
Publication of KR100980536B1 publication Critical patent/KR100980536B1/ko
Assigned to 아스펜 액퀴지션 코포레이션 reassignment 아스펜 액퀴지션 코포레이션 권리의 전부이전등록 Assignors: 샌드브리지 테크놀로지스, 인코포레이티드
Assigned to 퀄컴 인코포레이티드 reassignment 퀄컴 인코포레이티드 권리의 전부이전등록 Assignors: 아스펜 액퀴지션 코포레이션
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)
KR1020057005888A 2002-10-11 2003-10-09 멀티스레디드 프로세서에서 스레드-방식 메모리 액세스를위한 방법 및 장치 Expired - Lifetime KR100980536B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/269,247 2002-10-11
US10/269,247 US6925643B2 (en) 2002-10-11 2002-10-11 Method and apparatus for thread-based memory access in a multithreaded processor

Publications (2)

Publication Number Publication Date
KR20050046819A KR20050046819A (ko) 2005-05-18
KR100980536B1 true KR100980536B1 (ko) 2010-09-06

Family

ID=32068735

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057005888A Expired - Lifetime KR100980536B1 (ko) 2002-10-11 2003-10-09 멀티스레디드 프로세서에서 스레드-방식 메모리 액세스를위한 방법 및 장치

Country Status (9)

Country Link
US (1) US6925643B2 (https=)
EP (1) EP1550032B1 (https=)
JP (1) JP2006502507A (https=)
KR (1) KR100980536B1 (https=)
CN (1) CN1332303C (https=)
AU (1) AU2003282511A1 (https=)
ES (1) ES2758623T3 (https=)
HU (1) HUE046355T2 (https=)
WO (1) WO2004034218A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101279343B1 (ko) 2005-09-13 2013-07-04 프리스케일 세미컨덕터, 인크. 멀티-스레딩된 프로세서 구조

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591755B1 (ko) * 2003-07-22 2006-06-22 삼성전자주식회사 복수의 스레드를 동시에 처리하는 장치 및 방법
US20050102494A1 (en) * 2003-11-12 2005-05-12 Grochowski Edward T. Method and apparatus for register stack implementation using micro-operations
US7475222B2 (en) * 2004-04-07 2009-01-06 Sandbridge Technologies, Inc. Multi-threaded processor having compound instruction and operation formats
US7797363B2 (en) * 2004-04-07 2010-09-14 Sandbridge Technologies, Inc. Processor having parallel vector multiply and reduce operations with sequential semantics
US8074051B2 (en) 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7797728B2 (en) * 2004-10-27 2010-09-14 Intel Corporation Mechanism to generate restricted and unrestricted execution environments
TW200625097A (en) * 2004-11-17 2006-07-16 Sandbridge Technologies Inc Data file storing multiple date types with controlled data access
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20060136681A1 (en) * 2004-12-21 2006-06-22 Sanjeev Jain Method and apparatus to support multiple memory banks with a memory block
US20070223599A1 (en) * 2005-07-25 2007-09-27 Sysair, Inc., A Delaware Corporation Cellular PC modem architecture and method of operation
KR101305490B1 (ko) * 2005-10-01 2013-09-06 삼성전자주식회사 메모리 맵핑 방법 및 장치
US7584342B1 (en) * 2005-12-15 2009-09-01 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue
US7861060B1 (en) * 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP5076418B2 (ja) * 2006-09-19 2012-11-21 ソニー株式会社 共有メモリ装置
US8819099B2 (en) * 2006-09-26 2014-08-26 Qualcomm Incorporated Software implementation of matrix inversion in a wireless communication system
WO2008060948A2 (en) * 2006-11-10 2008-05-22 Sandbridge Technologies, Inc. Method and system for parallelization of pipelined computations
US7596668B2 (en) * 2007-02-20 2009-09-29 International Business Machines Corporation Method, system and program product for associating threads within non-related processes based on memory paging behaviors
US20100241834A1 (en) * 2007-11-05 2010-09-23 Sandbridge Technologies, Inc. Method of encoding using instruction field overloading
US8539188B2 (en) * 2008-01-30 2013-09-17 Qualcomm Incorporated Method for enabling multi-processor synchronization
WO2009114691A2 (en) * 2008-03-13 2009-09-17 Sandbridge Technologies, Inc. Method for achieving power savings by disabling a valid array
EP2324430A4 (en) 2008-08-06 2012-07-25 Aspen Acquisition Corp DIRECT MEMORY ACCESS MOTOR (DMA) THAT CAN BE STOPPED AND RESTARTED
CN101739242B (zh) * 2009-11-27 2013-07-31 深圳中微电科技有限公司 一种流数据处理方法及流处理器
CN102141905B (zh) * 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
GB2519813B (en) 2013-10-31 2016-03-30 Silicon Tailor Ltd Pipelined configurable processor
US9436501B2 (en) 2014-08-26 2016-09-06 International Business Machines Corporation Thread-based cache content saving for task switching
CN104461961B (zh) * 2014-11-20 2018-02-27 上海宝存信息科技有限公司 一种多核多线程的闪存装置及闪存控制方法
US11243880B1 (en) * 2017-09-15 2022-02-08 Groq, Inc. Processor architecture
CN114816529B (zh) * 2020-10-21 2025-07-18 上海壁仞科技股份有限公司 配置向量运算系统中的协作线程束的装置和方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6317872B1 (en) * 1997-07-11 2001-11-13 Rockwell Collins, Inc. Real time processor optimized for executing JAVA programs
US6341338B1 (en) * 1999-02-04 2002-01-22 Sun Microsystems, Inc. Protocol for coordinating the distribution of shared memory

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0553158B1 (en) * 1990-10-19 1994-12-28 Cray Research, Inc. A scalable parallel vector computer system
US5682491A (en) 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US6128720A (en) 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5649135A (en) 1995-01-17 1997-07-15 International Business Machines Corporation Parallel processing system and method using surrogate instructions
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US6263404B1 (en) * 1997-11-21 2001-07-17 International Business Machines Corporation Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system
US6079010A (en) 1998-03-31 2000-06-20 Lucent Technologies Inc. Multiple machine view execution in a computer system
US6317821B1 (en) 1998-05-18 2001-11-13 Lucent Technologies Inc. Virtual single-cycle execution in pipelined processors
US6269425B1 (en) * 1998-08-20 2001-07-31 International Business Machines Corporation Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system
US6260189B1 (en) 1998-09-14 2001-07-10 Lucent Technologies Inc. Compiler-controlled dynamic instruction dispatch in pipelined processors
US6256725B1 (en) 1998-12-04 2001-07-03 Agere Systems Guardian Corp. Shared datapath processor utilizing stack-based and register-based storage spaces
US6282585B1 (en) 1999-03-22 2001-08-28 Agere Systems Guardian Corp. Cooperative interconnection for reducing port pressure in clustered microprocessors
US6230251B1 (en) 1999-03-22 2001-05-08 Agere Systems Guardian Corp. File replication methods and apparatus for reducing port pressure in a clustered processor
US6269437B1 (en) 1999-03-22 2001-07-31 Agere Systems Guardian Corp. Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor
US6351808B1 (en) * 1999-05-11 2002-02-26 Sun Microsystems, Inc. Vertically and horizontally threaded processor with multidimensional storage for storing thread data
US20020103990A1 (en) * 2001-02-01 2002-08-01 Hanan Potash Programmed load precession machine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6317872B1 (en) * 1997-07-11 2001-11-13 Rockwell Collins, Inc. Real time processor optimized for executing JAVA programs
US6341338B1 (en) * 1999-02-04 2002-01-22 Sun Microsystems, Inc. Protocol for coordinating the distribution of shared memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101279343B1 (ko) 2005-09-13 2013-07-04 프리스케일 세미컨덕터, 인크. 멀티-스레딩된 프로세서 구조

Also Published As

Publication number Publication date
EP1550032A4 (en) 2008-03-12
US6925643B2 (en) 2005-08-02
US20040073772A1 (en) 2004-04-15
JP2006502507A (ja) 2006-01-19
CN1708747A (zh) 2005-12-14
EP1550032B1 (en) 2019-09-11
ES2758623T3 (es) 2020-05-06
KR20050046819A (ko) 2005-05-18
HUE046355T2 (hu) 2020-03-30
EP1550032A2 (en) 2005-07-06
AU2003282511A1 (en) 2004-05-04
WO2004034218A2 (en) 2004-04-22
WO2004034218A3 (en) 2004-06-03
AU2003282511A8 (en) 2004-05-04
CN1332303C (zh) 2007-08-15

Similar Documents

Publication Publication Date Title
KR100980536B1 (ko) 멀티스레디드 프로세서에서 스레드-방식 메모리 액세스를위한 방법 및 장치
KR100988955B1 (ko) 멀티스레디드 프로세서에서 레지스터 파일 포트 감소를위한 방법 및 장치
KR100991912B1 (ko) 토큰 트리거 방식 멀티스레딩을 위한 방법 및 장치
KR101295569B1 (ko) 쓰레드 당 다중의 동시적 파이프라인을 갖는 멀티쓰레드 프로세서
JP3784766B2 (ja) 多ポート統合キャッシュ
US7631171B2 (en) Method and apparatus for supporting vector operations on a multi-threaded microprocessor
US6119220A (en) Method of and apparatus for supplying multiple instruction strings whose addresses are discontinued by branch instructions
US20070300044A1 (en) Method and apparatus for interfacing a processor and coprocessor
US20070300043A1 (en) Method and apparatus for interfacing a processor and coprocessor
US20070300042A1 (en) Method and apparatus for interfacing a processor and coprocessor
JP4068828B2 (ja) 統合型分離型切替えキャッシュメモリ及び該キャッシュメモリを備えたプロセッサシステム
US20080141252A1 (en) Cascaded Delayed Execution Pipeline
JP3299663B2 (ja) 演算装置
Esfeden Locality-aware GPU Register File

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20050406

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20080910

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20091217

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20100604

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20100831

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20100831

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
FPAY Annual fee payment

Payment date: 20130729

Year of fee payment: 4

PR1001 Payment of annual fee

Payment date: 20130729

Start annual number: 4

End annual number: 4

FPAY Annual fee payment

Payment date: 20140730

Year of fee payment: 5

PR1001 Payment of annual fee

Payment date: 20140730

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20150630

Start annual number: 6

End annual number: 6

FPAY Annual fee payment

Payment date: 20160629

Year of fee payment: 7

PR1001 Payment of annual fee

Payment date: 20160629

Start annual number: 7

End annual number: 7

FPAY Annual fee payment

Payment date: 20180628

Year of fee payment: 9

PR1001 Payment of annual fee

Payment date: 20180628

Start annual number: 9

End annual number: 9

FPAY Annual fee payment

Payment date: 20190624

Year of fee payment: 10

PR1001 Payment of annual fee

Payment date: 20190624

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20200624

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20220622

Start annual number: 13

End annual number: 13

PR1001 Payment of annual fee

Payment date: 20230626

Start annual number: 14

End annual number: 14

PC1801 Expiration of term

Termination date: 20240409

Termination category: Expiration of duration