KR100967918B1 - Data loss prevention apparatus and method of single poly eeprom by surge noise - Google Patents

Abstract

An apparatus for preventing data loss of a single poly Ypirom caused by surge noise according to the present invention includes: a first signal processor configured to delay and output a signal input from an external source for a predetermined time; A second signal processor connected in parallel with the first signal processor and outputting a signal input from the outside for a predetermined time smaller than the first signal processor; During programming, the enable signal High is received from the outside and operated to provide a control signal low, and when the program is not input, the signal input through the second signal processor in conjunction with the second signal processor is not used. A signal input control unit controlling a delay; And, when programming, receive a control signal from the signal input control unit to output an input signal input through the first signal processing unit to an Y-pyrom control unit, and if the program is not input, the first signal input unit. And an input power determination unit which cuts or outputs an input signal according to a signal input time difference of the second signal processor, wherein the data loss of Y-pyrom generated by surge noise is not generated without programming or deleting Y-pyrom. There is an excellent effect that can be prevented.

Description

DATA LOSS PREVENTION APPARATUS AND METHOD OF SINGLE POLY EEPROM BY SURGE NOISE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for preventing data loss of a single poly Ipyrom due to surge noise. The present invention relates to a single poly with embedded information for output voltage, brightness, and white balance of an active organic light emitting diode panel. It's about this pyrom.

In general, one method of implementing a nonvolatile memory is a single poly IEPROM using a standard CMOS process.

Single poly ypyrom is disadvantageous in terms of area compared to using a conventional ypyrom process, but is very useful for applications requiring less memory because it can reduce the number of masks added.

However, in this case, since immunity to external surge noise is very low, data loss due to system assembly and external noise may occur.

Hereinafter, the operating principle of the single poly Y pyrom will be described.

1 is a view showing the structure of a typical single poly ypyrom.

It can be implemented with one n-type MOSFET (Metal Oxide Silicon Fie Effect Transistor) and two Poly-Active capacitors.

In this case, the active node of each capacitor becomes the program gate (PG) 31 and the erase gate (EG) 32, and the poly node of the capacitor and the gate of the MOSFET are short-circuited to form the floating gate (FG). 33 is formed.

The program / erase operation is implemented by controlling voltages applied to PG and EG as shown in [Table 1] below.

TABLE 1

PROGRAM GATE ERASE GATE DRAIN program High volt GND Floating Erase GND High volt Floating Read GND GND VDD (2.5-3.3 V)

In this case, there is a coupling of about 20: 1 in the capacitor forming the PG (cap1) 31 and the EG (cap2) 32. That is, in the case of a program, when a high voltage (approximately 20 V) is applied to the PG 31 and GND (0 V) is applied to the EG 32, electrons are FG through the EG 32 by coupling of two capacitors. (FN-tunneling), and the threshold voltage (VT) of the n-type MOSFET 34 becomes high.

On the contrary, in the case of erasing, when GND is applied to the PG 31 and a high voltage (about 20 V) is applied to the EP 32, electrons injected into the FG 33 exit through the EG 32 (FN−). tunneling), the VT of the n-type MOSFET 34 is lowered.

As shown in Table 1, 0V is simultaneously applied to the PG 31 and EG 32 to sense data on and off of the n-type MOSFET 34.

FIG. 2 is a diagram showing a capacitance equivalent circuit for a typical single poly ypyrom circuit.

In the case of the conventional single poly YPIROM circuit, in the case of the MTP operating normally, the stored data value should not change unless the program / erase operation is performed.

However, when the surge noise occurs on the power line without the power applied, the state of the single poly Y pyrom may change into a program.

FIG. 3 is a capacitance equivalent circuit showing the input of surge noise. When the MOSFET 34 acts as a capacitor, the program gate cap1 31 / erase gate cap2 32 / MOSFET cap3 ( 34) has a capacitance of 20: 1: 1.5.

In this case, the capacitance of the MOSFET 34 depends on its size, and since the body of the n-type MOSFET 34 is connected to GND, one node of the MOSFET (cap3) 34 is always connected to GND.

If surge noise is applied through a power line applying a high voltage in a state where power is not applied, the YPIROM control unit 10 may not play a role, and a high level may be simultaneously applied to the program gate 31 / erase gate 32. Voltage can be applied.

In this case, electrons are injected into the FG 33 through the body of the MOSFET by the coupling of the program gate cap1 31 and the MOSFET cap3 34 to change to a program state (VT rise). There was a problem.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to implement a filter circuit for external surge noise. Disclosed is an apparatus and method for preventing data loss of polypyrom.

According to an aspect of the apparatus for preventing data loss of a single poly Ypirom due to surge noise according to an embodiment of the present invention for achieving the above object, the first signal for delaying and outputting a signal input from the outside for a predetermined time Processing unit; A second signal processor connected in parallel with the first signal processor and outputting a signal input from the outside for a predetermined time smaller than the first signal processor; During programming, the enable signal High is received from the outside and operated to provide a control signal low, and when the program is not input, the signal input through the second signal processor in conjunction with the second signal processor is not used. A signal input control unit controlling a delay; And, when programming, receive a control signal from the signal input control unit to output an input signal input through the first signal processing unit to an Y-pyrom control unit, and if the program is not input, the first signal input unit. And an input power determination unit which blocks or outputs an input signal according to a signal input time difference of the second signal processing unit.

The first signal processor includes an R / C including a first resistor having one side connected to an input terminal of an external line and the other side connected to a second input terminal of the input power determination unit, and a first capacitor connected in parallel with the first resistor. The second signal processor is a second resistor, one side of which is connected to an input terminal of an external line and the other side of which is connected in parallel to the first input terminal of the input power determining unit and the signal input controller.

The signal processing delay time of the first signal processing unit and the second signal processing unit sets the time delay difference between the signals provided from the first signal processing unit and the second signal processing unit by the time constant difference.

The signal input controller may include a gate configured to receive an enable signal High or a disable signal Low from an external source, a drain connected in series with the second resistor of the second signal processor and the input power determination unit, and a GND. Is a first transistor consisting of a source connected to.

The input power determining unit may include a gate connected to the second signal processing unit and the signal input control unit in parallel, an inverting terminal, a drain connected to the first resistor and the first transistor of the first signal processing unit, and a source serving as an output terminal. 2 transistors.

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As described above, according to the apparatus and method for preventing data loss of a single poly Ipirom caused by surge noise according to the present invention, it is possible to avoid data loss of Ipirom caused by surge noise without program or deletion of Ipirom. There is an excellent effect that can be prevented.

Hereinafter, a preferred embodiment of an apparatus and a method for preventing data loss of a single poly ypirom caused by surge noise according to the present invention will be described in detail with reference to the accompanying drawings. At this time, it will be understood by those of ordinary skill in the art that the system configuration described below is a system cited for the purpose of the present invention and does not limit the present invention to the following system.

4 is a functional block diagram showing the configuration of a data loss prevention device of a single poly Ipyrom by surge noise according to an embodiment of the present invention, Figure 5 is a circuit diagram of a data loss prevention device of a single poly Ipyrom by surge noise to be.

An apparatus for preventing data loss of a single poly Y pyrom due to surge noise according to the present invention includes a first signal processor 210, a second signal processor 220, a signal input controller 230, and an input power determiner 240. do.

The first signal processor 210 delays a signal input from the outside for a predetermined time and outputs the signal to the input power determination unit 240. Here, the first signal processor 210 may be connected in parallel with a first resistor R1 having one side connected to an external input terminal and the other side connected to a second input terminal of the input power determination unit 240. It is an R / C circuit composed of the first capacitor C1.

In addition, the second signal processor 220 is connected in parallel with the first signal processor 210, and the input power determination unit 240 is delayed for a predetermined time in which a signal input from the outside is smaller than the first signal processor 210. Will output Here, the second signal processor 220 is a second resistor R2 connected at one side to an external input terminal and the other side connected in parallel to the first input terminal of the input power determination unit 240 and the signal input controller 230.

In this case, the signal processing delay time between the first signal processing unit 210 and the second signal processing unit 220 is determined by the time constant difference between the signals provided from the first signal processing unit 210 and the second signal processing unit 220. Set the time delay difference.

In addition, the signal input control unit 230 receives the enable signal High from the outside during the program operation, provides the control signal Low to the signal input determination unit 230 to drive the program, or does not delete the program. If not, the disable signal Low is received from the outside to operate as a capacitor, and in conjunction with the second signal processor 220 to control the delay of the signal input through the second signal processor 220. Here, the signal input controller 230 may include a gate for receiving an enable signal High or a disable signal Low from the outside, a second resistor R2 of the second signal processor 220, and an input power determiner ( 240 is a first transistor TR1 composed of a drain connected in series and a source connected to GND. Meanwhile, the enable signal High or the disable signal Low may be provided through a separate control unit, or may be supplied through the Epyrom control unit 10.

In addition, the input power determination unit 240 receives a control signal Low from the signal input control unit 230 during programming and operates the input signal input through the first signal processing unit 210 to the Y. pyrom control unit 10. On the other hand, when the program is not input, the input signal is blocked or output according to the signal input time difference between the first signal input unit and the second signal processor 220. Here, the input power determination unit 240, the second signal processing unit 220 and the signal input control unit 230 is connected in parallel, the gate is an inverting terminal, and the first resistor (R1) of the first signal processing unit 210. And a second transistor TR2 including a drain connected to the first transistor TR1 and a source as an output terminal.

General functions and detailed operations of the above-described elements will be omitted, and the operations will be described with reference to FIGS. 4 and 5 based on the operations corresponding to the present invention.

First, when programming / deleting the EPIROM, the signal input controller 230 is operated by receiving an enable signal High from the outside.

Then, the signal input controller 230 provides the control signal Low to the input power determination unit 240 through the input enable signal HIGH.

In addition, the signal High input to the second signal processor 220 through the external line is converted into a control signal Low and is input to the input power determination unit 240.

Then, the input power determination unit 240 which receives the control signal Low from the signal input control unit 230 and the second signal processing unit 220 is operated, and is input from the external line through the first signal processing unit 210. The received signal is provided to the program gate 31 or the erase gate 32 through the Y pyrom control unit 10.

On the other hand, when the program / deletion is not performed in the Y-e-ROM, the disable signal Low is input to the signal input control unit 230 from the outside, so that the signal input control unit 230 operates as a capacitor and the second signal processing unit 220. The signal input to the input power determiner 240 through the second signal processor 220 is delayed in cooperation with the control unit.

Here, the time constant of the first signal processor 210 and the time constant according to the interworking between the second signal processor 220 and the signal input controller 230 are determined. Accordingly, the time constant of the first signal processor 210 is greater than the time constant between the second signal processor 220 and the signal input controller 230.

Accordingly, the signal High input through the second signal processor 220 is provided faster than the signal provided from the external line is input to the input power determiner 240 through the first signal processor 210.

Accordingly, as the signal high is first input through the second signal processor 220, the input power determination unit 240 is not driven, and the signal input through the first signal processor 210 is an Y-pyrom controller ( It is blocked from being provided to the program gate 31 or the erase gate 32 through 10).

Therefore, even if surge noise occurs in the line connected to the Y pyrom control unit 10, the data of Y pyrom is not converted or lost.

Next, a method for preventing data loss of a single poly Y pyrom by surge noise according to the present invention having the above configuration will be described with reference to FIG. 6.

First, the signal input controller 230 determines whether or not an enable signal High for performing an operation for program and deletion of EPIROM is input (S1).

When the enable signal High is input in the determination step S1 (YES), the signal input controller 230 is driven and the control signal Low is supplied to the input power determination unit 240 to be driven (S2). .

Subsequently, the input power determination unit 240 provides a signal input through the first signal processing unit 210 from the outside to perform program / deletion of EPIROM (S3).

On the other hand, when the disable signal Low is input in the determination step S1 (NO), the signal input controller 230 is not driven and operates as a capacitor (S4).

Subsequently, a signal high from the second signal processor 220 is output through the time constant of the first signal processor 210 and the time constant difference between the second signal processor 220 and the signal input controller 230. The signal output through the signal processor 210 is first provided to the input power determiner 240 (S5).

Then, the input power determination unit 240 is not driven by the signal high input from the second signal processor 220, but blocks the signal provided through the first signal processor 210 (S6).

Hereinafter, a preferred embodiment of an EPyrom program device using an apparatus for preventing data loss of a single poly EPylo due to surge noise according to the present invention will be described in detail with reference to FIG. 7.

The data loss prevention apparatus 20 is connected to the Y-pyrom control unit 10.

If not programmed or deleted in the Y pyrom, an input signal input from the outside is controlled to be not input to the program gate 31 or the erase gate 32 through the Y pyrom control unit 10. That is, the signal input through the external power line is controlled to be input to the program gate 31 or the erase gate 32.

On the other hand, when programming / deleting the YPIROM, the signal input controller 230 of the data loss prevention apparatus 20 is operated by inputting an enable signal High from the outside, and the signal input controller 230 is an input power determination unit. Provide a control signal Low at 240.

In addition, the second signal processor 220 converts a signal high input through an external line into a control signal Low and provides the signal to the input power determiner 240.

Herein, the input power determination unit 240 which receives the control signal Low from the signal input control unit 230 is operated, and the signal input through the first signal processing unit 210 is transferred through the easy pyrom controller 10. It is provided to the program gate 31 or the erase gate 32.

On the other hand, when the program / deletion is not performed on the EPIROM, the disable signal Low is input to the signal input controller 230 from the outside.

Then, the signal input controller 230 is not driven. Accordingly, the signal input controller 230 operates as a capacitor and delays a signal input to the input power determination unit 240 through the second signal processor 220 in cooperation with the second signal processor 220.

Here, the time constant of the first signal processor 210 and the time constant according to the interworking between the second signal processor 220 and the signal input controller 230 are determined. Accordingly, the time constant of the first signal processor 210 is greater than the time constant between the second signal processor 220 and the signal input controller 230.

Therefore, the signal high input through the second signal processor 220 is provided faster than the signal high input to the input power determination unit 240 through the first signal processor 210.

Accordingly, as the signal high is input through the second signal processor 220, the input power determination unit 240 is not driven, and the signal input through the first signal processor 210 is the YPI controller 10. ) Is not input to the program gate 31 or the erase gate 32.

Therefore, even if surge noise occurs in the line connected to the Y pyrom control unit 10, the data of Y pyrom is not converted or lost.

The Y pyrom including the data loss prevention apparatus 20 as described above is mounted and used in the display driver IC as shown in FIG. 8. Here is an embodiment showing an embodiment used for the active organic light emitting diode PANEL.

Although the present invention has been described in detail only with respect to the specific embodiments described, it will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the present invention, and such modifications and modifications belong to the appended claims. .

1 is a view showing the structure of a typical single poly ypyrom.

FIG. 2 shows a capacitance equivalent circuit for a typical single poly ypyrom circuit according to FIG. 1. FIG.

FIG. 3 is a diagram illustrating a capacitance equivalent circuit according to surge noise input in a typical single poly ypyrom circuit according to FIG. 1; FIG.

Figure 4 is a functional block diagram showing the configuration of a data loss prevention device of a single poly ypyrom by surge noise in accordance with the present invention.

5 is a circuit diagram showing an apparatus for preventing data loss of a single poly ypirom caused by surge noise according to the present invention.

6 is a flow chart showing a method for preventing data loss of a single poly Ypirom by surge noise in accordance with the present invention.

FIG. 7 is a functional block diagram of an EPyrom program device using an apparatus for preventing data loss of a single poly EPylo due to surge noise according to another embodiment of the present invention; FIG.

FIG. 8 is a diagram illustrating a display device in which an EPyrom program device using a device for preventing data loss of a single poly YPIROM due to surge noise is mounted on a display driver IC. Referring to FIG.

<Explanation of symbols for the main parts of the drawings>

10: Y pyrom control unit 31: program gate (PG)

32: erase gate (EG) 33: floating gate (FG)

210: first signal processor 220: second signal processor

230: signal input control unit 240: input power determination unit

Claims (11)

In a device for preventing data loss of a single poly EPyrom by surge noise, A first signal processor configured to delay and output a signal input from the outside for a predetermined time; A second signal processor connected in parallel with the first signal processor and outputting a delayed signal for a predetermined time smaller than the first signal processor from a high signal; During programming, the enable signal High is received from the outside and operated to provide a control signal low, and when the program is not input, the signal input through the second signal processor in conjunction with the second signal processor is not used. A signal input control unit controlling a delay; And During programming, the control signal Low is input from the signal input controller to operate the controller, and outputs an input signal input through the first signal processor to the Y-pyrom controller. And an input power determination unit which blocks or outputs an input signal according to a signal input time difference of the second signal processing unit. The method of claim 1, The first signal processor, An R / C circuit comprising a first resistor connected at one side to an input terminal of an external line and at the other end to a second input terminal of the input power determination unit, and a first capacitor connected in parallel with the first resistor; Data loss prevention device of single poly Y. pyrom by surge noise. 3. The method of claim 2, The second signal processor, Apparatus for preventing data loss of a single poly Ipyrom due to surge noise, characterized in that one side is connected to the input terminal of the external line and the other side is a second resistor connected in parallel to the first input terminal and the signal input control unit of the input power determination unit. The method of claim 3, wherein The signal processing delay time of the first signal processor and the second signal processor, An apparatus for preventing data loss of a single poly Ipyrom due to surge noise, characterized by setting a time delay difference between a signal provided from a first signal processor and a second signal processor by a time constant difference. The method of claim 4, wherein The signal input control unit, A gate configured to receive an enable signal (High) or a disable signal (Low) from an external source, a second resistor of the second signal processor, a drain connected in series with the input power determination unit, and a source connected to a GND; A device for preventing data loss of a single poly Ipyrom due to surge noise, characterized in that it is a transistor. The method of claim 5, The input power determination unit, The second signal processor and the signal input controller are connected in parallel, and are a second transistor including a gate which is an inverting terminal, a drain connected to the first resistor and the first transistor of the first signal processor, and a source which is an output terminal. Data loss prevention device of single poly Y pyrom by surge noise. delete delete delete delete delete

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