KR200276104Y1 - programming circuit device of flash memory fabricated with single poly - Google Patents

Abstract

The present invention relates to a programming device of a single poly flash memory, the device comprising: a comparison means for comparing the reference voltage and the voltage of the programming device, a discrimination means for determining whether the programming is to proceed, a discriminating means for classifying the type of programming, And drive means for driving the switch according to the determined result.

The present invention has the effect of effectively programming the flash memory composed of single poly by applying the write and erase voltage to the cell appropriately according to the state of the cell to the single poly flash memory requiring a plurality of programming voltages according to the above configuration. .

Description

Programming circuit device of flash memory fabricated with single poly}

The present invention relates to a programming device of a flash memory, the device comprising a comparison means for comparing the reference voltage and the voltage of the programming device, discriminating means for determining whether to continue programming, discriminating means for classifying the type of programming, And drive means for driving the switch according to the result.

Until now, digital memory has been used as a medium for storing information because of reliability, speed, and relatively simple circuit configuration. However, the digital memory that divides up to two pieces of information into one cell seems to have reached the limit of integration due to process width due to line width. One way to overcome this problem is analog memory that can store multiple states in a cell.

The proposed analog memory is based on EEPROM. EEPROM has been used mainly for data or program storage due to its inertness. Recently, EEPROM has been rapidly diversified, such as redundancy of an integrated circuit or a router block. This trend is a natural result in light of the trend of SOC.

Existing EEPROMs have been mainly manufactured in the double poly process. However, it would be economical to design and manufacture in a normal single-poly process in order for EEPROM to act as a macro that implements a function in the system rather than just memory.

The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to fabricate a circuit for applying write and erase voltages that effectively provide a plurality of program voltages required for a flash memory.

1 is a circuit diagram of a cell according to a preferred embodiment of the present invention

2 is a circuit diagram showing the configuration of a switch device according to an embodiment of the present invention

3 is a circuit diagram showing the configuration of a general voltage driving device for a high voltage according to a preferred embodiment of the present invention

4 is an enable circuit diagram according to a preferred embodiment of the present invention;

5 is a clock diagram used in an enable circuit diagram according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: storage means, 30: voltage conversion means, 40: comparison means, 41: locking means,

The above object is easily achieved by the present invention, comprising a plurality of switches according to an aspect of the present invention, means for distinguishing between writing and erasing of a program; And control means for controlling the write and erase voltages in accordance with the result of the means; Comparison means to decide whether to continue programming according to the controlled result.

1 is a circuit diagram illustrating a single poly flash memory cell 10 as an embodiment of the present invention. In a double-poly EEPROM cell, writing and erasing is possible by Fowler-Nodheim tunneling method, whereas in single-poly EEPROM, writing should be implemented by Hot-Electron injection and erasing by Fowler-Nodheim tunneling. In this way, the peripheral circuit for the case where the electron transfer method by writing and erasing is different

The design is somewhat complicated.

Figure 1 shows a single poly EEPROM (10) structure proposed by R. J. McParland. Arbitrary information is distinguished by the amount of electrons in the floating gate composed of nfet (11), pfet1 (12) and pfet2 (13). The write operation of moving electrons to the floating gate shown in the figure is performed by hot electron injection. For this purpose, a voltage must be applied to the control gate 15, a high voltage is applied to the drain 17, and the source 16 must be grounded. . This operation increases the number of electrons in the floating gate and raises the threshold voltage of the transistor. On the other hand, it is the erasing operation that sends electrons in the floating gate to the outside by Fowler-Nordheim method. To this end, a voltage is applied to the control gate 14 and all the rest are grounded. The erase operation has the effect of lowering the threshold voltage. Once programming, such as writing or erasing, is stopped, the high voltage applied from the outside is removed, and electrons in the floating gate are no longer moved by the high energy barrier of SiO2 and remain in the floating gate. The information stored in is maintained. These characteristics make EEPROM inert.

This EEPROM was enough to represent two states (logical 0 and 1) in conventional digital memory. Therefore, the information can be distinguished by applying a sufficiently high programming voltage to the node of the cell during the write and erase operations. This is because there is sufficient margin between 0 and 1 information. However, in order to apply the cell to the analog memory, it is difficult to secure sufficient margin between states, unlike in the design of the digital memory. In addition, in the case of analog memory, the number of electrons stored in the floating gate must change linearly, which may cause a problem in the programming of the cell, which can greatly affect the accuracy of the system. In order to minimize this problem and to design analog memory using EEPROM, system design by feedback circuit should be done. When designing a system using feedback circuits, unlike the digital case, programming voltages that are not too high will be applied until the difference between the analog input signal and the information stored in the inactive cell is minimized. The programming voltage level at this time is left behind by the programming speed. Higher voltages will improve programming speed while adversely affecting the reliability of analog memory. Low voltages, on the other hand, have the opposite effect. Therefore, the magnitude of the programming voltage must be determined according to the purpose of the memory.

In the conventional digital memory, in order to simplify the programming operation, the initial programming operation always started with the erasing operation. Therefore, when the data to be stored in the cell is 0, no further operation is necessary, and when 1, a sufficient amount of electrons are injected into the floating gate by the write operation. However, programming in this manner in analog memory can lead to programming time that is dependent on the difference between the current state and the desired state and consumes unnecessary programming time. Therefore, in this paper, the programming operation such as writing or writing is designed to depend on the state of the cell. In other words, when the current threshold voltage is lower than the reference voltage, the threshold voltage is increased by the erase operation, and conversely, the write operation is performed when the state of the cell to be programmed is higher than the reference voltage.

Even though the system design using the feedback circuit is made, a dish offset occurs between the external reference voltage and the voltage programmed in the cell due to problems such as the bias generated in the comparator. This problem is solved if the information is read through the same rule as that used for the programming operation during the read operation. This is because the offset generated in the write operation is returned to that amount in the read operation. However, careful consideration of stability is essential in system design using feedback circuit.

2 shows a peripheral circuit configuration for programming a single poly EEPROM cell. As shown in the figure, the programming of the circuit is complicated because the voltages applied to the control gates, injectors, and drains are different during writing, reading, and erasing.

Mechanism V _SS (source) V _DD (drain) V _CG (gate) V _EG (e_gate) Erase FN tunneling 0 0 0 10V (vin2) Program Hot electron injection 0 6V (vin1) 6V (vin1) 0 Read 0 1.5 V (vin4) 2.5V (vin3) ``

Table 1. Voltages to be Applied

Table 1 shows the voltages that must be applied in each operation of the 0.6um standard CMOS process. As shown in the table, in the case of Fowler-Nordheim tunneling for erasing, a high voltage is applied to the gate 15 and the other node must be grounded to escape electrons from the floating gate. At this time, due to the high voltage applied to the gate 15, a phenomenon such as a caption or an oxide blackdown may be expected. To prevent this, the two capacitors in Figure 1 (pfet1 (12) and pfet2 (13)) are placed in nwell. The low doping concentration of the well has the effect of raising the potential for blackdown to occur. In the case of hot electron injection for writing, a voltage of 5 to 6 V is applied and electrons are injected into the floating gate by accelerating electrons in the channel.

In FIG. 2, M1 20 is the EEPROM cell shown in FIG. 1, and the signal applied by ERCONT regulates the voltage vout2 applied to the gate in Table 1. PGCONT is a signal for adjusting the voltage vout1 applied to the injector 14.

In FIG. 2, CONVERTER 30 is a circuit for driving a high voltage at a general voltage, which is shown in FIG. In FIG. 3, in1 should be connected to a general voltage, and in2 should be connected to a high voltage to be adjusted.

4 is a block diagram showing a circuit for enabling ERCONT and PGCONT. The comparator 40 in FIG. 4 is used to determine the completion time of the program by comparing the reference voltage before and after programming with the voltage during the program and the output of the comparator 40 is opout. The block consisting of DFF and XOR is used to determine the write and erase operations to become the reference voltage in the state before programming. clk1, clk2, and clk3 are non-overlapping clocks, and thus voltages must be compared during writing or erasing. Since the operation of adding or removing electrons to the floating gate requires a delay time, there must be a sufficient delay time until clk3 or clk2 is applied after clk3 is applied. The latch block 41 is initialized by the reset input and keeps the state in which the writing or erasing operation is determined as high. When the opout state changes, the latch block 41 drops to low to stop the writing or erasing operation. inv2 and inv3 are inverter circuits to prevent ERCONT and PGCONT from turning on at the voltage near the reference voltage when programming or erasing. inv2 is a circuit block with increased fall delay time, and inv3 is a circuit block with increased rise time. to be.

The proposed analog memory is based on EEPROM. EEPROM has been used mainly for data or program storage due to its inertness. Recently, EEPROM has been rapidly diversified, such as redundancy of an integrated circuit or a router block. This trend is a natural result in light of the trend of SOC.

Existing EEPROMs have been mainly manufactured in the double poly process. However, it would be economical to design and manufacture in a normal single-poly process in order for EEPROM to act as a macro that implements a function in the system rather than just memory.

Claims (4)

A programming apparatus of a single poly flash memory, comprising: a comparison means configured to compare a program state and a reference voltage of a cell, the counter comprising a plurality of counters; Discriminating means for determining write and erase operations in accordance with the result determined by said comparing means Driving means for connecting or disconnecting a high voltage programming voltage by said comparing and discriminating means; And determining means for determining whether to stop programming according to the state of the cell programmed by the driving means. 2. The programming device according to claim 1, wherein said writing and erasing operation discriminating means includes a comparing device for comparing a magnitude between a threshold voltage and a reference voltage of a cell after programming. 2. The programming device according to claim 1, wherein the programming and reading operations occur along the same circuit trajectory, thereby eliminating the DC offset that may occur in various discriminating means, driving means, and comparing means. 2. A programming device according to claim 1, wherein the programming device recognizes the difference between the current state of the cell and the reference voltage during the programming operation and determines the write and erase operations according to the result.