KR100961201B1 - Method for manufacturing transistor in semiconductor device - Google Patents

Abstract

A transistor manufacturing method of a semiconductor device of the present invention comprises the steps of forming a gate insulating film, a gate conductive film, a diffusion barrier film, a metal film and a gate hard mask film on a semiconductor substrate; Patterning the hard mask film to form a hard mask film pattern; Forming a metal layer pattern, a diffusion barrier layer pattern, and a gate conductive layer pattern by an etching process using the hard mask layer pattern as an etching mask; And performing a selective oxidation process on the sidewalls of the gate conductive layer pattern to form a compensation layer to compensate for the damage caused by the etching process.

Selective oxidation process, oxygen gas, steam

Description

Method for manufacturing transistor in semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device.

As the degree of integration of semiconductor devices increases, the design rules of the devices are rapidly decreasing. As the design rule decreases, the gate line height and line width (CD) are also reduced. On the contrary, since the operation of the semiconductor device requires an ever-increasing speed, the resistance of the metal line that transmits the signal must be small. Therefore, the resistance of the wiring is reduced by using a material having low resistance for the metal film used to form the gate line.

In general, the gate stack has a structure in which a gate insulating film, a gate conductive film, a diffusion barrier film, a metal film, and a hard mask film are stacked on a semiconductor substrate. In this case, as the semiconductor devices are highly integrated, tungsten (W) is applied to the metal film to form a gate stack having low resistance. The gate stack is formed by forming the above-described gate target layers and then performing an etching process. However, in the process of forming the gate stack by the etching process, damage may occur on the gate stack, for example, the gate insulating layer or the gate conductive layer. As a result, post-treatment is being performed to compensate for the damage generated in the etching process. However, there may be a problem that the metal film is oxidized in the post-treatment proceeding to compensate for the damage. Accordingly, in order to prevent the metal film from being oxidized, a capping nitride that protects the metal film is formed or an oxidation process using plasma is performed. However, when the capping nitride layer is formed, a step is added, thereby complicating the process, and a stress caused by the capping nitride layer may cause a leaching phenomenon in which the gate stack is inclined in one direction. In addition, in the case of the oxidation process using plasma, the reaction apparatus is complicated, and the problem of the gate stack being damaged by the plasma may further occur because the plasma source is used. In addition, the oxidation process using plasma has a problem that it is difficult to form a gate stack stably because it is difficult to proceed at a low temperature because it proceeds in a single chamber.

A transistor manufacturing method of a semiconductor device according to the present invention comprises the steps of forming a gate insulating film, a gate conductive film, a diffusion barrier film, a metal film and a gate hard mask film on a semiconductor substrate; Patterning the hard mask layer to form a hard mask layer pattern; Forming a metal layer pattern, a diffusion barrier layer pattern, and a gate conductive layer pattern by an etching process using the hard mask layer pattern as an etching mask; And performing a selective oxidation process on the sidewalls of the gate conductive layer pattern to form a compensation layer to compensate for the damage caused by the etching process.

The diffusion barrier film may be selected from a group consisting of a titanium (Ti) film, a titanium nitride (TiN) film, and a titanium silicon nitride (TiSiN) film.

The selective oxidation process may include: loading the semiconductor substrate into a furnace; Exhausting the interior of the furnace with hydrogen (H ₂ ) gas; And maintaining a vapor pressure of 10 ³ mmHg to 10 ⁶ mmHg at a temperature of 100 ° C. to 1200 ° C. while supplying oxygen (O ₂ ) gas into the evacuated furnace. Here, the concentration of oxygen (O ₂ ) in the furnace is controlled to a maximum of 10 ppm while exhausting the inside of the furnace with hydrogen (H ₂ ) gas, and the furnace preferably uses a batch type.

The selective oxidation process may include: loading the semiconductor substrate into a furnace; Exhausting the interior of the furnace with hydrogen (H ₂ ) gas; And maintaining a vapor pressure of 10 ³ mmHg to 10 ⁶ mmHg at a temperature of 100 ° C. to 1200 ° C. while supplying steam (H ₂ O) formed by heating in the exhaust furnace. The concentration of oxygen (O ₂ ) in the furnace is controlled to a maximum of 10 ppm while exhausting the inside of the furnace with hydrogen (H ₂ ) gas, and the furnace is preferably using a batch type.

The steam is preferably formed by placing DI water in a tank and heating to a predetermined temperature.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 to 4 are views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention. 5 is a view schematically showing a phase diagram according to temperature and pressure. 6 and 7 are graphs showing material characteristics before and after the selective oxidation process.

Referring to FIG. 1, a gate insulating layer 105 is formed on a semiconductor substrate 100. Although not shown in the drawing, the semiconductor substrate 100 has an active region and an isolation region defined by an isolation layer. The gate insulating film 105 is formed of a silicon oxide (SiO ₂ ) film using an oxidation process, for example, a thermal oxidation method. Next, a gate conductive film 110 is formed over the gate insulating film 105. The gate conductive layer 110 may be formed of a conductive material, for example, a polysilicon layer.

Referring to FIG. 2, a diffusion barrier film 115 is formed on the gate conductive film 110. The diffusion barrier layer 115 prevents the silicide reaction from occurring when the gate conductive layer 110 is in direct contact with the metal layer to be formed later. When the gate conductive layer 110 is in direct contact with the metal layer, a silicide reaction occurs between the two layers, and a metal silicide layer is formed at the interface between the gate conductive layer 110 and the metal layer, and thus the dopant of the gate conductive layer 110 is formed. The problem may be that the dopant is lost. The diffusion barrier film 115 may be selected from a group consisting of a titanium (Ti) film, a titanium nitride (TiN) film, and a titanium silicon nitride (TiSiN) film. Next, a metal film 120 is formed over the diffusion barrier film 115. The metal film 120 may be formed of a metal material having a low resistance, for example, a tungsten (W) film. While the degree of integration of the device increases, the operation of the semiconductor device requires an ever-faster speed, so the resistance of the metal line for transmitting the signal must be smaller. Therefore, the metal film 120 preferably uses a material having a low resistance to reduce the resistance of the wiring. Next, a hard mask film 125 is formed on the metal film 120. The hard mask layer 125 may serve to prevent the lower layer from being etched in the etching process of forming the gate stack, and may be formed of a nitride layer. Next, a resist film pattern 130 defining a gate stack forming region is formed on the hard mask film 125.

Referring to FIG. 3, the exposed portion of the hard mask layer 125 (see FIG. 2) is etched using the resist layer pattern 130 (see FIG. 2) as an etch mask to form the hard mask layer pattern 135. Subsequently, the exposed portions of the metal layer 120, the diffusion barrier layer 115, and the gate conductive layer 110 are etched to form the metal layer pattern 140, the diffusion barrier layer pattern 145, and the gate conductive layer pattern 150. Form. The etching process is performed until the gate insulating layer 105 is exposed. Next, the resist film pattern 130 is removed. Accordingly, the gate stack 160 is formed on the gate insulating layer 105 of the semiconductor substrate 100. The gate stack 160 has a structure of a metal film pattern 140, a diffusion barrier film pattern 145, a gate conductive film pattern 150, and a hard mask film pattern 135 on the gate insulating film 105.

Referring to FIG. 4, a compensation layer 155 is formed on sidewalls of the gate conductive layer pattern 150. The gate conductive layer is formed by the etching source during the etching process of FIG. 3 to form the hard mask layer pattern 135, the metal layer pattern 140, the diffusion barrier layer pattern 145, and the gate conductive layer pattern 150. Damage occurs on the sidewall of the pattern 150. If a subsequent process is performed in a state where damage occurs on the sidewall of the gate conductive layer pattern 150, characteristics of the semiconductor device, such as a leakage current generated through the damaged portion, may be deteriorated. Accordingly, a selective oxidation process is performed on the semiconductor substrate 100 to form a compensation layer 155 that selectively compensates for damaged sidewalls of the gate conductive layer pattern 150. The compensation film 155 is formed of an oxide film.

The selective oxidation process proceeds using hydrogen (H ₂ ) gas and oxygen (O ₂ ) gas. Specifically, the semiconductor substrate 100 is loaded into a furnace. The furnace uses a batch type instead of a single type in which wafers are placed one by one. Next, hydrogen (H ₂ ) gas is supplied into the furnace to purge the inside of the furnace. In this case, the concentration of oxygen (O ₂ ) in the furnace is preferably adjusted to 10 ppm or less. Herein, the oxygen (O ₂ ) concentration is adjusted to a predetermined concentration or less in the front opening Unified Pod (FOUP), the loading area and the furnace. Next, oxygen (O ₂ ) gas is supplied into the furnace where the exhaust is advanced. The selective oxidation process is carried out in the range of maintaining a vapor pressure ratio of 10 ³ mmHg P to 10 ⁶ mmHg at a temperature of 100 ° C. to 1200 ° C. while supplying oxygen (O ₂ ) gas into the evacuated furnace. At this time, it is preferably performed at a temperature of 500 ℃ to 900 ℃. Then, the compensation layer 155 is selectively formed on the sidewall of the gate conductive layer pattern 150.

In another embodiment of the selective oxidation process in which the compensation layer 155 is formed on the sidewalls of the gate conductive layer pattern 150, vapor (H ₂ O) may be used instead of the oxygen (O ₂ ) gas. First, as described above, the semiconductor substrate 100 is loaded into the furnace, and hydrogen (H ₂ ) gas is supplied into the furnace to exhaust the inside of the furnace. Here, the concentration of oxygen (O ₂ ) in the furnace is adjusted to 10 ppm or less. Here, the concentration of oxygen (O ₂ ) is adjusted to a predetermined concentration or less in the front opening Unified Pod (FOUP), the loading area (Loading area) and the furnace. Next, steam H ₂ O is supplied into the furnace where the exhaust is performed to form a compensation film 155 on the sidewall of the gate conductive film pattern 150.

Instead of generating steam by the combustion reaction of hydrogen and oxygen using an external torch, steam is added to a tank by heating de-ionized water (DIW) to a constant temperature. Form. In this case, the temperature of the steam supplied to the furnace can be reduced, so that condensation of the steam can be prevented even when the oxidation process is performed at a low temperature. Where the vapor (H ₂ O) for using the selective oxidation step is steam (H ₂ O) to 10 ³ mmHg to 10 ⁶ mmHg in the vapor pressure at a temperature of 100 ℃ to 1200 ℃ while feeding formed by heating method in the exhaust of the furnace Keep going. At this time, it is preferably performed at a temperature of 500 ℃ to 900 ℃. Referring to FIG. 6, which shows a phase diagram of oxidation or reduction depending on the temperature and pressure of tungsten and titanium nitride and silicon, a temperature of 500 ° C. to 900 ° C. and 10 ³ mmHg to 10 ^6. In the vapor pressure range of mmHg, a reaction occurs that selectively oxidizes only silicon (Si) without oxidizing tungsten (W). Accordingly, the compensation film 155 is selectively formed on the sidewall of the gate conductive film pattern 150 by supplying oxygen gas or steam while maintaining a temperature of 500 ° C. to 900 ° C. and a vapor pressure range of 10 ³ mmHg to 10 ⁶ mmHg. . In this case, the thermal budget of the device can be reduced by proceeding at a low temperature while performing a selective oxidation process in a batch type furnace.

6 and 7 are graphs showing material properties before and after the selective oxidation process. In particular, FIG. 6 is a graph of a titanium nitride film which is analyzed before and after the selective oxidation process by using a surface analyzer (XPS; X-ray Photoelectron Spectroscopy). Comparing Fig. 6 (a) showing the surface analysis graph before the selective oxidation process with Fig. 6 (b) the surface analysis graph after the selective oxidation process, the titanium nitride film before the selective oxidation process is performed. While oxygen (O ₂ ) is measured from the surface, after the selective oxidation process, oxygen (O ₂ ) is measured 10 minutes before and after sputtering. Accordingly, it can be seen that after the selective oxidation process, oxidation penetration in the titanium nitride film is reduced. In addition, referring to FIG. 7, which shows a secondary ion mass spectrometry (SIMS) analysis of the titanium nitride film, it can be seen that the oxygen concentration in the titanium nitride film is lower after the selective oxidation process than before the selective oxidation process. .

Instead of forming the compensation film 155 on the sidewall of the gate conductive film pattern 150 by an oxidation process using a plasma source, hydrogen gas and oxygen gas (H ₂ / O ₂ ) or hydrogen gas and steam (H _{By using 2} / H ₂ O), it is possible to prevent the problem that the gate electrode is damaged by the plasma. In addition, the process of covering the tungsten metal film with the capping nitride film can be omitted, and the process step can be simplified, and an interface film, for example, a tungsten nitride (WN _x ) film is formed by the reaction between the capping film nitride film and the tungsten metal film, thereby providing resistance. This can be prevented from increasing. In addition, it is possible to fundamentally block the formation of the tungsten nitride (WN _x ) film, thereby preventing the gate stack from being leaked due to stress.

1 to 4 are views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

5 is a view schematically showing a phase diagram according to temperature and pressure.

6 and 7 are graphs showing material properties before and after the selective oxidation process.

Claims (9)

Forming a gate insulating film and a gate conductive film on the semiconductor substrate; Forming a diffusion barrier film made of a titanium (Ti) film, a titanium nitride (TiN) film, or a titanium silicide (TiSiN) film, a metal film made of tungsten (W), and a hard mask film on the gate conductive film; Patterning the hard mask layer to form a hard mask layer pattern; Forming a metal layer pattern, a diffusion barrier layer pattern, and a gate conductive layer pattern by an etching process using the hard mask layer pattern as an etching mask; And The gate conduction damaged in the etching process by supplying oxygen (O ₂ ) gas on the semiconductor substrate while maintaining a vapor pressure of 10 ³ mmHg to 10 ⁶ mmHg in which the metal film does not oxidize at a temperature of 500 ° C. to 900 ° C. Forming a compensation film selectively covering the sidewalls of the film pattern. The method of claim 1, Before supplying the oxygen (O ₂ ) gas on the sidewall of the gate conductive layer pattern, And loading the semiconductor substrate into the furnace and evacuating the inside of the furnace with hydrogen (H ₂ ) gas. The method of claim 2, And exhausting the furnace interior with hydrogen (H ₂ ) gas while controlling the oxygen (O ₂ ) concentration in the furnace not to exceed 10 ppm. The method of claim 2, The furnace is a transistor manufacturing method of a semiconductor device using a batch type. Forming a gate insulating film and a gate conductive film on the semiconductor substrate; Forming a diffusion barrier film made of a titanium (Ti) film, a titanium nitride (TiN) film, or a titanium silicide (TiSiN) film, a metal film made of tungsten (W), and a hard mask film on the gate conductive film; Patterning the hard mask layer to form a hard mask layer pattern; Forming a metal layer pattern, a diffusion barrier layer pattern, and a gate conductive layer pattern by an etching process using the hard mask layer pattern as an etching mask; And Damaged in the etching process by supplying steam (H ₂ O) formed by a heating method while maintaining a vapor pressure of 10 ³ mmHg to 10 ⁶ mmHg in which the metal film does not oxidize at a temperature of 500 ℃ to 900 ℃ on the semiconductor substrate And forming a compensation film selectively covering sidewalls of the gate conductive layer pattern. The method of claim 5, Before supplying steam (H ₂ O) formed by heating on the sidewalls of the gate conductive layer pattern, loading the semiconductor substrate into the furnace, and exhausting the inside of the furnace with hydrogen (H ₂ ) gas. A transistor manufacturing method of a semiconductor device further comprising. The method of claim 6, And exhausting the furnace interior with hydrogen (H ₂ ) gas while controlling the oxygen (O ₂ ) concentration in the furnace not to exceed 10 ppm. The method of claim 6, The furnace is a transistor manufacturing method of a semiconductor device using a batch type. The method of claim 6, The vapor is a transistor manufacturing method of a semiconductor device is formed by placing DI water in a tank and heated to a predetermined temperature.

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