KR100958964B1 - 단일 명령어 다중 데이터 실행 엔진 플래그 레지스터용평가 유닛 - Google Patents

단일 명령어 다중 데이터 실행 엔진 플래그 레지스터용평가 유닛 Download PDF

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KR100958964B1
KR100958964B1 KR1020077014564A KR20077014564A KR100958964B1 KR 100958964 B1 KR100958964 B1 KR 100958964B1 KR 1020077014564 A KR1020077014564 A KR 1020077014564A KR 20077014564 A KR20077014564 A KR 20077014564A KR 100958964 B1 KR100958964 B1 KR 100958964B1
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South Korea
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flag register
execution engine
bits
bit
simd
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Korean (ko)
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KR20070089208A (ko
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마이클 드와이어
홍 지앙
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인텔 코오퍼레이션
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
KR1020077014564A 2004-12-17 2005-12-15 단일 명령어 다중 데이터 실행 엔진 플래그 레지스터용평가 유닛 Expired - Fee Related KR100958964B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/015,778 2004-12-17
US11/015,778 US7219213B2 (en) 2004-12-17 2004-12-17 Flag bits evaluation for multiple vector SIMD channels execution

Publications (2)

Publication Number Publication Date
KR20070089208A KR20070089208A (ko) 2007-08-30
KR100958964B1 true KR100958964B1 (ko) 2010-05-20

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Country Link
US (1) US7219213B2 (https=)
JP (1) JP4901754B2 (https=)
KR (1) KR100958964B1 (https=)
CN (1) CN100422979C (https=)
DE (1) DE112005003130B4 (https=)
GB (1) GB2436499B (https=)
TW (1) TWI297853B (https=)
WO (1) WO2006066262A2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071130A (ja) * 2006-09-14 2008-03-27 Ricoh Co Ltd Ｓｉｍｄ型マイクロプロセッサ
US9892047B2 (en) * 2009-09-17 2018-02-13 Provenance Asset Group Llc Multi-channel cache memory
US8996845B2 (en) * 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
WO2013081588A1 (en) * 2011-11-30 2013-06-06 Intel Corporation Instruction and logic to provide vector horizontal compare functionality
US10318291B2 (en) 2011-11-30 2019-06-11 Intel Corporation Providing vector horizontal compare functionality within a vector register
US10255228B2 (en) * 2011-12-06 2019-04-09 Nvidia Corporation System and method for performing shaped memory access operations
US10042813B2 (en) * 2014-12-15 2018-08-07 Intel Corporation SIMD K-nearest-neighbors implementation
GB2536069B (en) * 2015-03-25 2017-08-30 Imagination Tech Ltd SIMD processing module
US20200341772A1 (en) * 2019-04-29 2020-10-29 DeGirum Corporation Efficient Architectures For Deep Learning Algorithms

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020083311A1 (en) * 2000-12-27 2002-06-27 Paver Nigel C. Method and computer program for single instruction multiple data management
KR20040027409A (ko) * 2002-09-25 2004-04-01 마쯔시다덴기산교 가부시키가이샤 프로세서

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
JP2768803B2 (ja) * 1990-04-26 1998-06-25 株式会社東芝 並列演算処理装置
JP2793357B2 (ja) * 1990-11-20 1998-09-03 株式会社東芝 並列演算装置
JP2793342B2 (ja) * 1990-08-09 1998-09-03 株式会社東芝 演算処理装置
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
JP3442225B2 (ja) * 1996-07-11 2003-09-02 株式会社日立製作所 演算処理装置
US5805875A (en) * 1996-09-13 1998-09-08 International Computer Science Institute Vector processing system with multi-operation, run-time configurable pipelines
JP3652518B2 (ja) 1998-07-31 2005-05-25 株式会社リコー Ｓｉｍｄ方式の演算器及び演算処理装置
GB2382886B (en) * 2001-10-31 2006-03-15 Alphamosaic Ltd Vector processing system
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020083311A1 (en) * 2000-12-27 2002-06-27 Paver Nigel C. Method and computer program for single instruction multiple data management
KR20040027409A (ko) * 2002-09-25 2004-04-01 마쯔시다덴기산교 가부시키가이샤 프로세서

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Publication number Publication date
JP2008524723A (ja) 2008-07-10
GB2436499A (en) 2007-09-26
JP4901754B2 (ja) 2012-03-21
DE112005003130B4 (de) 2009-09-17
GB2436499B (en) 2009-07-22
CN100422979C (zh) 2008-10-01
KR20070089208A (ko) 2007-08-30
CN1790310A (zh) 2006-06-21
WO2006066262A2 (en) 2006-06-22
GB0713878D0 (en) 2007-08-29
DE112005003130T5 (de) 2007-11-22
TWI297853B (en) 2008-06-11
TW200636573A (en) 2006-10-16
US20060149924A1 (en) 2006-07-06
US7219213B2 (en) 2007-05-15
WO2006066262A3 (en) 2006-12-14

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