KR100947562B1 - Manufacturing methode and cell transistor for memory device by using a ferroelectric layer - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor memory device using a ferroelectric film and a cell transistor thereof. In particular, a memory device having a cell gate electrode of the present invention includes a gate dielectric film and a metal gate sequentially formed on a semiconductor substrate, and a metal gate both substrate. A source / drain region formed therein, an interlayer insulating film formed on the front surface of the substrate on which the metal gate is formed, a ferroelectric film vertically connected to the metal gate through an opening in the interlayer insulating film, and a control gate connected to the ferroelectric film on the interlayer insulating film. .

Accordingly, the present invention reads data using the property that the polarization direction of the ferroelectric film is changed according to the driving voltage of the control gate by forming a three-layer structure of a metal gate, a ferroelectric film, and a control gate in the gate portion of the cell transistor.

FRAM, Metal Gate, Ferroelectric Film, Control Gate, Logic

Description

Manufacturing method of semiconductor memory device using ferroelectric film and cell transistors thereofManufacturing methode and cell transistor for memory device by using a ferroelectric layer             

1 to 8 are process flowcharts illustrating a method of manufacturing a semiconductor memory device using a ferroelectric film according to the present invention.

Explanation of symbols on the main parts of the drawings

A: memory area B: logic area

10 semiconductor substrate 12 device isolation film

14 gate insulating film 16a gate electrode

18: spacer 20: source / drain region

22, 38: interlayer insulating film 17, 24, 36: photoresist pattern

26: opening 28: gate dielectric film

30a: metal gate 32: ferroelectric film

34: control gate 40: contact

42: wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same. In particular, a semiconductor memory device using a ferroelectric film, which is a next-generation memory device requiring nonvolatile and high-speed read / write in accordance with miniaturization, low power, and high performance of information and communication devices, is manufactured. And a cell transistor thereof.

Conventional memory is divided into volatile and nonvolatile memory. Volatile DRAM is composed of one transistor and one capacitor to input and output information, which shows the advantage of compactness due to the small cell size.However, the information is lost when the power is cut off and the information is lost after a long time even when the power is connected. Therefore, you need to refresh. Non-volatile memories include EEPROM and flash memory, which have advantages in density, but because the method of writing or erasing information takes advantage of the hot carrier or tunneling characteristics of electrons generated in the channel by applying a high voltage. Data storage takes a lot of time and requires devices that operate at higher voltages and are slower than other memories. Therefore, devices that operate at multiple voltages must be configured on one chip. In addition, since it is driven at a high voltage, it consumes a lot of power, and thus there is a limit to the application of a place where information storage and chip operation require low voltage, low power, or high speed operation. In addition, it is difficult to implement an embedded memory that takes longer to program and erase data than other memory devices and integrates a memory device and a logic circuit.

In contrast, FRAM using ferroelectric materials can spontaneously polarize ferroelectric materials using voltages used in the core operation of logic to write and erase data in the memory. In addition, the polarization state is maintained even if the power is cut off after polarization. It is also possible to reverse the direction of polarization by changing the voltage across the memory.

Therefore, when manufacturing non-volatile memory and logic circuit embedded memory products using ferroelectric materials, it is possible to achieve low power and high speed of operation as well as non-volatile property that stored memory is not erased even without continuous supply of power. There is this.

An object of the present invention is to form a metal gate and a ferroelectric film in the gate portion of the cell transistor and to form a control gate connected to the ferroelectric film in order to solve the problems of the prior art as described above, the polarization direction of the ferroelectric film according to the voltage of the control gate As a result, the threshold voltage of the cell transistor is changed to read data, and when applied to a device in which a memory and logic circuit are integrated, a semiconductor memory device using a ferroelectric film that can simultaneously achieve nonvolatile characteristics, low power, and high speed of operation. It is to provide a method for producing.                         

In order to achieve the above object, the present invention forms a ferroelectric film having hysteresis characteristics in the gate portion of a cell transistor, and applies + and − voltages to a control gate connected to the ferroelectric film, thereby applying a threshold voltage of the cell transistor according to the polarization direction of the ferroelectric film. The present invention provides a cell transistor of a semiconductor memory device using a ferroelectric film for quickly reading data.

In order to achieve the above object, the present invention provides a method of forming a nonvolatile memory device having a ferroelectric film, sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate, and forming source / drain regions in both gate electrode substrates. Forming an opening by forming an interlayer insulating film on the entire surface of the resultant and selectively etching the interlayer insulating film to remove the gate electrode and the gate insulating film, and sequentially forming a gate dielectric film and a metal gate in the opening; Embedding the ferroelectric film in the opening, and forming a control gate connected to the ferroelectric film on the interlayer insulating film.

In order to achieve the above object, another method of the present invention is to form a nonvolatile memory device having a ferroelectric film and an embedded memory device integrating a logic circuit, the steps of sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate; Forming a source / drain region in both substrates of the gate electrode, forming an interlayer insulating film on the entire surface of the resultant, and selectively etching the interlayer insulating film of the memory region to remove the gate electrode and the gate insulating film to form openings; Sequentially forming a gate dielectric film and a metal gate in the opening of the semiconductor substrate, embedding a ferroelectric film in the opening of the metal gate, and forming a control gate connected to the ferroelectric film on the interlayer insulating film of the memory region. Is done.

In order to achieve the above object, the present invention provides a cell transistor of a nonvolatile memory device having a ferroelectric film, comprising: a gate dielectric film and a metal gate sequentially formed on a semiconductor substrate, source / drain regions formed in both metal gate substrates, and a metal. An interlayer insulating film formed on the entire surface of the substrate on which the gate is formed, a ferroelectric film vertically connected to the metal gate through an opening in the interlayer insulating film, and a control gate connected to the ferroelectric film on the interlayer insulating film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 8 are process flowcharts for explaining a method of manufacturing a semiconductor memory device using a ferroelectric film according to the present invention, with reference to these drawings will be described a manufacturing process according to an embodiment of the present invention. The present embodiment relates to a manufacturing process of an embedded memory device in which a memory and a logic circuit are integrated.

First, as shown in FIG. 1, as the semiconductor substrate 10, a device isolation film 12 defining an active region and an inactive region of a device by a device isolation process is disposed in a memory region A and a logic region B of a silicon substrate. Form. For example, the device isolation film 12 is formed of a shallow trench type device isolation film. An impurity ion implantation process, for example, a p-well process, is performed to form a well (not shown) in the substrate 10. Subsequently, an impurity ion implantation process is performed on the substrate 10 to control n-channels and threshold voltages of cell transistors and logic transistors.

Subsequently, silicon oxide film (SiO2) as a gate insulating film 14 and doped polysilicon as a gate electrode conductive film 16 are sequentially deposited on the entire substrate. A photoresist pattern 18 defining a gate electrode region is formed on the gate electrode conductive film 16 by a photolithography process.

An etching process using the photoresist pattern 18 is performed to pattern the gate electrode conductive film 16 and the gate insulating film 14 to remove the photoresist pattern 18.

As shown in FIG. 2, the gate insulating layer 14b and the gate electrode 16a of the cell transistor are formed on the substrate of the memory region A, and the gate insulating layer of the logic transistor is also formed on the substrate of the logic region B. 14 and a gate electrode 16a are formed. The silicon nitride film Si3N4 is deposited as an insulating film on the entire surface of the substrate of the memory and logic regions A and B and dry-etched to form spacers 18 on both sidewalls of the gate electrode 16a. In addition, source / drain regions are formed in both substrates of the gate electrode 16a by performing ion implantation (for example, n + ion implantation) using the gate electrodes 16a and the spacers 18 of the memory and logic regions A and B as masks. 20 is formed.

Then, as shown in FIG. 3, after forming the interlayer insulating film 22 using USG (Undoped Silicate Glass), BPSG (BoroPhospho Silicate Glass), etc., on the entire surface of the resultant, the upper surface of the interlayer insulating film 22 by a photolithography process. The photoresist pattern 24 is formed to mask the logic region B and open the gate electrode 16a of the memory region A. FIG. Subsequently, the interlayer insulating layer 22 exposed by the photoresist pattern 24 is selectively etched by an etching process to remove the gate electrode 16a and the gate insulating layer 14 of the memory region A, and to expose the substrate surface of the corresponding portion. The opening 26 is formed. Then, as shown in FIG. 4, the photoresist pattern 24 is removed.

Subsequently, as shown in FIG. 5, the gate dielectric layer 28 and the metal gate metal 30 are sequentially formed in the opening of the memory region A. FIG. In this case, the gate dielectric layer 28 is deposited to a predetermined thickness on the bottom of the opening, and the metal 30 is deposited to fill the remaining opening. Here, the gate dielectric layer 28 is Al ₂ O ₃ , and the metal 30 is W, Pt, IrO 2, Ir, RuO 2, or Ru inert metal material.

As shown in FIG. 6, the metal gate 30 is etched back so that the metal is embedded up to a predetermined height of the opening of the memory region A to form the metal gate 30a. The height of the metal gate 30a is preferably equal to or lower than the height of the spacer 18.

The ferroelectric film 32 is then buried in the opening above the metal gate 30a. In this case, the ferroelectric layer 32 is deposited by coating or chemical vapor deposition (CVD) by a sol-gel method, and the ferroelectric layer on the interlayer insulating layer 22 is removed by full etching or chemical mechanical polishing (CMP).                     

Subsequently, as shown in FIG. 7, a metal 34 is deposited on the entire surface of the interlayer insulating film 22, and a photoresist pattern 36 is formed thereon. The metal is patterned according to the photoresist pattern by an etching process to form a control gate 34 connected to the ferroelectric layer 32 on the interlayer insulating layer 22 of the memory region A. Referring to FIG. The photoresist pattern 36 is removed. At this time, the metal for the control gate 34 is formed of an inert metal of W, Pt, IrO ₂ , Ir, RuO ₂ , or Ru.

Then, as shown in FIG. 8, an interlayer insulating film 38 is formed on the entire surface of the resultant by using an HDP (High Density Plasma) oxide film or the like, and a wiring process is performed to form an interlayer insulating film of the memory area A and the logic area B. A contact 40 and a wiring 42 connected to the source / drain region 20 or the control gate 34 are formed in the 38 and 22.

Although the embodiment of the present invention described above relates to an embedded memory device in which a memory and a logic circuit are integrated, the present invention may be applied only to a manufacturing process of a memory device.

The cell transistor of the memory device having the ferroelectric film according to the present invention manufactured as described above is configured as follows. The gate dielectric layer 28 and the metal gate 30a sequentially formed on the semiconductor substrate 10, the source / drain regions 20 formed in both substrates of the metal gate 30a, and the front surface of the substrate on which the metal gate 30a is formed. Control connected to the ferroelectric film 32 formed on the interlayer insulating film 22, the ferroelectric film 32 vertically connected to the metal gate 30a through the openings in the interlayer insulating film 22, and on the interlayer insulating film 22. Gate 34.

Therefore, the cell gate electrode of the present invention has a three-layer structure of a metal gate 30a-ferroelectric film 32-control gate 34. When the positive voltage and the negative voltage are applied to the control gate 34 of the present invention, polarization occurs in the ferroelectric layer 32, thereby changing the potential of the metal gate 30a serving as the cell gate. As a result, the substrate state of the memory region A changes, and the threshold voltage of the cell transistor changes according to the polarization direction. The difference between the changed threshold voltages is sensed to output data of 0 and 1.

As described above, the present invention forms a three-layer structure of a metal gate, a ferroelectric film, and a control gate in the gate portion of the cell transistor to quickly read data using a property in which the polarization direction of the ferroelectric film changes according to the driving voltage of the control gate. Serve

Furthermore, when the present invention is applied to a device in which a memory and a logic circuit are integrated, it is possible to achieve nonvolatile characteristics, low power, and high speed of operation.

Claims (17)

In forming a nonvolatile memory device having a ferroelectric film, Sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate; Forming source / drain regions in both substrates of the gate electrode; Forming an interlayer insulating film on the semiconductor substrate to bury the gate electrode; Selectively etching the interlayer insulating layer to remove the gate electrode and the gate insulating layer to form an opening; Sequentially forming a gate dielectric layer and a metal gate in the opening; Filling a ferroelectric film in an opening in an upper portion of the metal gate; And And forming a control gate connected to the ferroelectric layer on the interlayer insulating layer. In forming a nonvolatile memory device having a ferroelectric film and an embedded memory device integrating a logic circuit, Sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate; Forming source / drain regions in both substrates of the gate electrode; Forming an interlayer insulating film on the semiconductor substrate to bury the gate electrode; Selectively etching the interlayer insulating layer of the memory region to remove the gate electrode and the gate insulating layer to form an opening; Sequentially forming a gate dielectric layer and a metal gate in the opening of the memory region; Filling a ferroelectric film in an opening in an upper portion of the metal gate; And And forming a control gate connected to the ferroelectric film on the interlayer insulating film of the memory region. The method of manufacturing a semiconductor memory device using a ferroelectric film according to claim 1 or 2, further comprising forming a spacer of an insulating material on a sidewall of the gate electrode after the gate electrode is formed. The method of manufacturing a semiconductor memory device using a ferroelectric film according to claim 1 or 2, wherein the gate dielectric film is Al ₂ O ₃ . The method of claim 1, wherein the metal gate is made of W, Pt, IrO ₂ , Ir, RuO ₂ , or Ru inert metal material. The method of claim 1, wherein the metal gate manufacturing process includes depositing a metal in the opening and etching the entire surface so that the metal is embedded up to a predetermined height of the opening. Way. The method of claim 1 or 2, wherein the ferroelectric film is deposited by coating or CVD by a sol-gel method so as to be embedded in the opening. The method of manufacturing a semiconductor memory device using a ferroelectric film according to claim 1, wherein the ferroelectric film is formed by filling a ferroelectric film so as to be embedded in the opening, and then removing the ferroelectric film of the interlayer insulating film by etching or CMP. The method of claim 1, wherein the control gate is formed of an inert metal of W, Pt, IrO ₂ , Ir, RuO ₂ , or Ru. The method of claim 1 or 2, further comprising, after forming the control gate, forming an interlayer insulating film and performing a wiring process to form a contact and wiring connected to the source / drain region or the control gate. A method of manufacturing a semiconductor memory device using a ferroelectric film, comprising: A cell transistor of a nonvolatile memory device having a ferroelectric film, A gate dielectric layer and a metal gate sequentially formed on the semiconductor substrate; Source / drain regions formed in both substrates of the metal gate; An interlayer insulating film formed on an entire surface of the substrate on which the metal gate is formed; A ferroelectric film vertically connected to the metal gate through an opening in the interlayer insulating film; And And a control gate connected to the ferroelectric layer on the interlayer insulating layer. 12. The cell transistor of claim 11, further comprising a spacer made of an insulating material on the sidewall of the metal gate. 12. The cell transistor of claim 11, wherein the gate dielectric layer is Al ₂ O ₃ . 12. The cell transistor of claim 11, wherein the metal gate is W, Pt, IrO ₂ , Ir, RuO ₂ , or Ru inert metal material. The cell transistor of claim 11, wherein the control gate is formed of an inert metal of W, Pt, IrO ₂ , Ir, RuO ₂ , or Ru. 12. The method of claim 11, wherein an upper interlayer insulating film is formed on the entire surface of the interlayer insulating film on which the control gate is formed, and further includes a contact and wiring connected to the source / drain area or the control gate through contact holes of the interlayer insulating films. A cell transistor of a semiconductor memory device using a ferroelectric film. 12. The cell transistor of claim 11, wherein + voltage and-voltage are applied to the control gate to polarize the ferroelectric film so that the potential of the gate electrode is changed.

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