KR100591120B1 - Manufacturing method of flash memory device - Google Patents

Abstract

A method of manufacturing a semiconductor device according to the present invention includes forming a tunneling oxide film on a semiconductor substrate, sequentially laminating a polycrystalline silicon film, an oxide film, and a first nitride film on the tunneling oxide film, and hardly patterning the first nitride film by a selective etching process. Forming a mask, forming a second nitride film covering the hard mask, etching the second nitride film to form a spacer on the sidewall of the hard mask, etching the oxide film and the polycrystalline silicon film using the hard mask and the spacer as a mask And forming a floating gate, forming a polycrystalline silicon film covering the floating gate, and etching the polycrystalline silicon film by a selective etching process to form a control gate, wherein the hard mask forming step includes etching the first nitride film and the oxide film. The first nitride film is etched with a selectivity of 20: 1 or more. The lure is.

Flash memory, selectivity

Description

Manufacturing method of flash memory device

1 is a cross-sectional view showing a profile between a hard mask and a spacer according to the prior art,

2 is a layout view of a flash memory according to the present invention;

3 is a cross-sectional view taken along the line III-III of FIG. 2,

4 is a cross-sectional view taken along the line IV-IV of FIG. 2,

5A to 9C are diagrams for explaining the method of manufacturing the flash memory of FIGS. 2 to 4.

The present invention relates to a method of manufacturing a memory device, and more particularly, to a method of manufacturing a flash memory device capable of writing and erasing data.

In general, flash memory starts from the desire to realize the advantages of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) at the same time. It is aimed at low manufacturing cost in terms of chip size.

In addition, the flash memory is a non-volatile semiconductor memory that does not lose data even when the power supply is interrupted. However, since the flash memory has the characteristics of a random access memory (RAM) in that the recording and erasing of information is easily performed in the system, a memory card is used. It is used for a storage device that replaces a hard disk of a portable office automation device.

The writing of data during the operation of such flash memory cells is performed by forming hot-electrons in the drain region and injecting them into the floating gate through the tunneling oxide layer. The erase operation of the flash memory cells is performed by Fowler-Nordheim. An erase operation is performed by discharging electrons injected into the floating gate to the source region using tunneling.

In the general structure of a conventional flash memory, a gate oxide is formed on a portion of an upper portion of an element region of a semiconductor substrate, and a floating gate made of polycrystalline silicon is formed on an upper portion of the gate oxide. It is not connected and acts as an electronic storage node.

A dielectric film having a structure in which an oxide film or a nitride film is stacked in a single layer or a plurality of layers is formed on the floating gate. A control gate made of polycrystalline silicon is formed on the dielectric layer to serve as a gate in a general MOS transistor.

As semiconductor devices become more highly integrated, gaps between devices are arranged at intervals of 0.15 μm or less, and it is difficult to pattern thin films at intervals of 0.15 μm or less by a selective etching process using a photosensitive film.

In order to solve this problem, a method of forming a spacer on the sidewall of the patterned nitride film and using the same as an etching mask is used.

This method is used when patterning floating gates when manufacturing flash memory. That is, a polycrystalline silicon film and an oxide film are formed, and a nitride film and a spacer are formed on the oxide film using a hard mask, and the oxide film and the polycrystalline silicon film are etched using the mask.

However, during the manufacturing process, the etching selectivity of the hard mask 16 and the spacer 18 and the oxide film 14 is small, so that the oxide film 14 and the polycrystalline silicon film 12 may be formed during the formation of the hard mask 16 and the spacer 18. The upper portion is also etched to a part, whereby when forming the spacer 18, the profile of the polysilicon film is weak as shown in FIG. As a result, the thickness of the polycrystalline silicon film is unevenly formed, and when the floating gate is formed by etching the polycrystalline silicon film using the spacer as an etching mask, it is difficult to control the etching end point of the polycrystalline silicon film.

1 is a cross-sectional view showing a profile between a hard mask and a spacer according to the prior art. Reference numeral 10 denotes a semiconductor substrate, 11 a source isolation region, and 13 a tunneling oxide film.

The present invention is to solve the above problems to provide a flash memory manufacturing method that can easily control the subsequent manufacturing process by maximizing the etching selectivity of the nitride film and the oxide film.

In order to achieve the above object, the present invention uses a gas having an etching selectivity of 20: 1 or more for the oxide film and the nitride film as a CH ₃ F etching gas when the nitride film is etched to form a hard mask.

Specifically, forming a tunneling oxide film on the semiconductor substrate, laminating a polycrystalline silicon film, an oxide film, a first nitride film sequentially on the tunneling oxide film, patterning the first nitride film by a selective etching process to form a hard mask, Forming a second nitride film covering the hard mask, etching the second nitride film to form a spacer on the sidewall of the hard mask, etching the oxide film and the polycrystalline silicon film using the hard mask and the spacer as a mask to form a dielectric layer and a floating gate And forming a polycrystalline silicon film covering the floating gate, and etching the polycrystalline silicon film by a selective etching process to form a control gate, wherein the hard mask forming step comprises forming an etching selectivity ratio of the first nitride film and the oxide film by 20: 1. The first nitride film is etched under the above conditions.

In this case, the first nitride film is preferably etched in an etching chamber into which CH ₃ F, O ₂ , and Ar are injected. In this case, CH ₃ F is injected into the range of 10 to 70 sccm, O ₂ is 5 to 50 sccm, and Ar is 50 to 180 sccm. It is preferable.

In the forming of the spacer, the second nitride film is preferably etched with etch back.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

It will now be described in detail with reference to the drawings with reference to embodiments of the present invention.

2 is a layout view of a flash memory according to an exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line III-III 'of FIG. 2, and FIG. 4 is a cross-sectional view taken along line IV-IV' of FIG. 2.

2 to 4, an active region in which semiconductor elements and the like are disposed in the semiconductor substrate 10 is defined, and an element isolation region 14 for insulation is formed between the semiconductor elements. A source region 26 and a drain region 26 doped with a high concentration of conductive impurities are formed in a predetermined region of the active region.

A tunneling oxide layer 16 is formed on the entire surface of the semiconductor substrate 10. The tunneling oxide film 16 is a passage through which electrons accelerated by the electric field enter the floating gate 18 described later when an electric field is applied to the semiconductor element, and enters the floating gate 18 when the electric field is not applied. It serves to block electrons from returning to the semiconductor substrate 10.

A plurality of floating gates 18 are formed on the tunneling oxide film 16. The floating gate 18 is formed of polycrystalline silicon doped with conductive impurities. The floating gate 18 stores incoming electrons, and is said to be programmed when the electrons are charged, and deleted when the electrons are discharged to the substrate according to electric field conditions.

The dielectric layer 20 is formed on the floating gate 18. The dielectric layer 20 may be formed of silicon oxide or the like.

The dielectric layer 20 prevents electrons introduced into the floating gate 18 from being transmitted to the control gate 28 described later, and better polarizes the floating gate 28 by the voltage applied to the control gate 28. Make it happen.

A control gate 28 is formed on the dielectric layer 20, which is made of polycrystalline silicon and substantially serves as an electrode. The control gate 28 is also made of polycrystalline silicon doped with conductive impurities, and is insulated from the floating gate 18 by the dielectric layer 20. An interlayer insulating layer 30 having a via hole VH is formed on the substrate 10 including the control gate 28. A plug 32 is formed on the interlayer insulating layer to be connected to the source region and the drain region 26 via via holes, respectively, and to be connected to the upper metal wiring (not shown).

On the interlayer insulating layer 30, a metal wiring layer including a plug in contact with the interlayer insulating layer and the lower wiring layer may be further formed as well as the metal wiring.

A method of manufacturing such a semiconductor device will be described with reference to FIGS. 5A to 9C and the drawings attached to FIGS. 2 to 4.

5A through 9C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

5A through 5C, an isolation region 14 is formed on the semiconductor substrate 10 to define the active region 12 using a local oxidation silicon (LOCOS) or shallow trench isolation (STI) scheme. do. The LOCOS method forms a device isolation region 14 by oxidizing a predetermined region of the substrate 10, and the STI method forms a device isolation region 14 by forming a trench in the substrate 10 and then filling an insulating material. That's the way it is.

Thereafter, the semiconductor substrate 10 is thermally oxidized to form a tunneling oxide layer 16 having a thickness of 15 to 30 kPa.

Next, as shown in Figs. 6A and 6B, polycrystalline silicon is deposited on the tunneling oxide film 16 to form a polycrystalline silicon film 18A. Thereafter, silicon oxide (SiO ₂ ) and silicon nitride (SiN _x ) are sequentially stacked on the polycrystalline silicon film 18A to form an oxide film 20A and a nitride film. The polycrystalline silicon film 18A, the oxide film 20A, and the nitride film are formed by a method such as chemical vapor deposition (CVD).

Then, the nitride film is patterned by a selective etching process to form a hard mask 22.

At this time, the atmosphere of the etching chamber is as follows. The pressure in the chamber is 20-50mT, the power is 125-450W and the RF power is maintained at 10-200MHz. And the injected gas is CH ₃ F 10 ~ 70sccm, O ₂ 5 ~ 50sccm, Ar 50 ~ 180sccm is injected.

The CH ₃ F gas maintains the selectivity ratio of the nitride film and the oxide film 20A to about 20: 1 so that the etching rate of the oxide film 20A is 20 kW / min or less. Therefore, the nitride film may be etched for a sufficient time to remove 100% of the nitride film.

As shown in FIGS. 7A and 7B, silicon nitride is deposited to cover the hard mask 22 to form a nitride film. The nitride film is removed using an etch back to form a spacer 24 on the side of the hard mask 22.

8A to 8C, the oxide film 20A and the polycrystalline silicon film 18A are etched using the hard mask 22 and the spacer 24 as a mask to form the dielectric layer 20 and the floating gate 18. do.

Thereafter, the source and drain regions 26 are formed by doping conductive type impurity ions into the active region of the semiconductor substrate 10 using the floating gate 18 as a mask.

9A to 9C, a polycrystalline silicon film is formed on the floating gate 18 and then etched through a selective etching process to form the control gate 28.

2 to 4, after the interlayer insulating layer 30 is formed, the via hole VH is formed by etching through the selective etching process. After forming a metal film on the interlayer insulating film 30 to fill the via hole VH, the metal film is polished by chemical mechanical polishing (CMP) to form a plug 32. Next, it is connected to the upper portion of the plug 32 to form a metal wiring (not shown) for inputting an external signal to the source and drain regions 26. If necessary, the process of forming the metal wiring layer connected to the lower metal wiring through the plug of the interlayer insulating film may be further performed several times.

As described above, according to the present invention, the etching selectivity of the nitride film and the oxide film is maximized to minimize the etching of the lower oxide film. Therefore, the polycrystalline silicon under the oxide film is not etched.

Therefore, it is easy to etch them and there is less or no etching, thereby providing a high quality flash memory.

Claims (4)

Forming a tunneling oxide film on the semiconductor substrate, Stacking a polycrystalline silicon film, an oxide film, and a first nitride film sequentially on the tunneling oxide film; Patterning the first nitride layer by a selective etching process to form a hard mask; Forming a second nitride film covering the hard mask; Etching the second nitride layer to form a spacer on a sidewall of the hard mask; Etching the oxide film and the polysilicon film using the hard mask and the spacer as a mask to form a dielectric layer and a floating gate; Forming a polycrystalline silicon film covering the dielectric layer and the floating gate, Etching the polycrystalline silicon film by a selective etching process to form a control gate, In the hard mask forming step, the etching selectivity between the first nitride film and the oxide film is 20: 1 or more , and the first nitride film is etched at an etching rate of 20 A / min or less . In claim 1, The first nitride film is etched in an etching chamber in which CH ₃ F, O ₂ , Ar is implanted. In claim 1, And forming the spacers by etching the second nitride layer using an etch back. In claim 2, The CH ₃ F is 10 ~ 70sccm, O ₂ is 5 ~ 50sccm, Ar is injected into the range of 50 ~ 180sccm Flash memory manufacturing method.

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