KR100941977B1 - Embeded system and method of page relocation for the same - Google Patents

Abstract

It is an object of the present invention to provide an embedded system and page relocation method therefor capable of minimizing leakage current generated in a memory. The memory is divided into multiple physical memory banks. From the processor's point of view, memory is divided into a number of logical memory pages, where the memory bank in which each memory page is physically located is determined by the data relocation circuit. When the processor reads data from the memory, it refers to the data relocation circuit to access the physical memory bank. Initially, all memory banks are turned off to eliminate leakage current. The data relocation circuitry turns on the memory bank when there is a request to store data from the processor, and when the memory invalidation request is made by the processor, all memory pages belonging to the memory bank are invalidated. Deactivate. Inactive memory banks are powered down to reduce leakage currents. The circuit proposed in the present invention minimizes leakage current by maximizing the number of memory banks that are powered off even during processor operation.

Embedded Systems, Memory, Leakage Current, Banks, Page Relocation

Description

Embedded system and how to relocate it {EMBEDED SYSTEM AND METHOD OF PAGE RELOCATION FOR THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor design technology, and more particularly, to an embedded system consisting of a processor and a memory, and more particularly, to a memory page rearrangement technology in an embedded system.

The present invention is derived from a study conducted as part of the IT Strategic Technology Development Project of the Ministry of Information and Communication and the Institute of Information and Telecommunications Research and Development. Platform]

With the development of the information technology (IT) industry, portable products have rapidly increased. Since these portable products are battery-powered, technology that minimizes power consumption of the semiconductor chips constituting the product has become a determining factor in product productivity in order to maximize operating time within a limited battery capacity.

The power consumption of semiconductor chips can be divided into two factors. First, dynamic power dissipation is power dissipation generated by capacitors present in transistors and metal lines in semiconductors. This capacitor component is charged and emptied every clock cycle. Since the charge flow is current, it is an important component of power consumption. Second is leakage power. As the semiconductor process develops, the leakage power becomes a big part of the total power consumption. This is because as the process progresses, the gate oxide thickness of the transistor becomes thinner, and as the gate oxide film becomes thinner, the operation voltage of the semiconductor circuit is lowered because the gate oxide thickness cannot withstand the high voltage, and the lower operation voltage is the threshold voltage. This is because as the voltage approaches the voltage, the transistor does not turn on or off completely and the amount of sub-threshold current that occurs below the threshold voltage increases rapidly.

Commonly used current suppression methods, such as blocking the processor clock, reducing the number of gates, or reducing the number of signal transitions occurring in a circuit, are dynamic power consumption methods that have no effect on leakage current. There is no The most common way to cut off the leakage current is to cut off the power to the circuit itself.

When the circuit is cut off, the circuit that is cut off does not operate at all, and in the case of a circuit such as flip-flop or memory, the previously memorized data is lost. have. In addition, when the entire embedded system operates in a power down mode, the entire power supply may be cut off. However, since the entire system does not operate at all, a method of shutting down only a part of the power has been proposed. . Transistor-level methods for turning off the power include a variable threshold circuit, a dual-threshold transistor, a multi-threshold transistor, and a power gating structure. gating structure).

Rather than using this new type of transistor circuit to efficiently block leakage current, it is more efficient to divide the system and dynamically control the power of the divided circuits. In particular, in recent multimedia-based embedded systems, since a large amount of memory is integrated and the number of gates of the memory occupies a large proportion of the number of logic gates, reducing the leakage current generated in the memory has a decisive effect on reducing the total power. do.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an embedded system and a page rearrangement method thereof capable of minimizing leakage current generated in a memory.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. It will also be appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

According to an aspect of the present invention for achieving the above technical problem, a processor; A data redistribution circuit configured to receive a logical address from the processor and map a valid page to a physical address so that the valid pages are concentrated and arranged in a specific bank, and generate a bank power control signal according to whether a valid page exists in the corresponding bank; And a memory including a plurality of memory banks addressed by physical addresses output from the data redistribution circuit, and a plurality of switching means for selectively applying a power supply voltage to each memory bank in response to the bank power control signal. Embedded systems are provided.

Here, the data redistribution circuit may include a page arrangement unit for generating a physical page address with reference to a page conversion unit and a page valid flag unit below; The page converter for receiving a logical page address from the page layout unit and outputting a corresponding physical page address or a newly mapped physical page address; The page valid flag unit for allocating a valid flag of each page according to the page information transmitted from the processor; And a power control section for generating the bank power control signal with reference to the page conversion section and the page valid flag section.

According to another aspect of the present invention, a page relocation method for an embedded system having a processor and a memory, the method comprising: checking whether a logical page requested from the processor is valid; As a result of the checking, finding a bank having a maximum number of valid pages and including at least one invalid page as the corresponding logical page is invalid; Writing an invalid page number into a corresponding physical page number store; Setting a valid flag corresponding to an invalid page to an on state; And outputting a result page number.

The method may further include outputting a physical page address corresponding to the logical page address as a result of the checking as a result of the checking as to whether the requested logical page is valid.

With the development of semiconductor process technology, in the process below 90nm, the leakage current occurring below the threshold voltage occupies most of the power consumed by the entire system. In particular, in embedded systems consisting of a processor and a memory, the gate portion of the memory to the total number of gates increases, so leakage current in the memory area is a key part of the total power consumption. In the present invention, a method for reducing power consumption by dividing a memory into a plurality of memory banks and mounting a circuit for blocking leakage current in each memory bank to dynamically cut off leakage current of a memory bank that is not used during system operation. Suggest. In particular, a method of dynamically controlling leakage current by relocating data used in a processor using a data relocating circuit is proposed.

The memory is divided into multiple physical memory banks. From the processor's point of view, memory is divided into a number of logical memory pages, where the memory bank in which each memory page is physically located is determined by the data relocation circuit. When the processor reads data from the memory, it refers to the data relocation circuit to access the physical memory bank. Initially, all memory banks are turned off to eliminate leakage current. The data relocation circuitry turns on the memory bank when there is a request to store data from the processor, and when the memory invalidation request is made by the processor, all memory pages belonging to the memory bank are invalidated. Deactivate. Inactive memory banks are powered down to reduce leakage currents. The circuit proposed in the present invention minimizes leakage current by maximizing the number of memory banks that are powered off even during processor operation.

Using the data rearrangement circuit according to the present invention described above can minimize the leakage current by shutting off the power of the memory bank even during the operation of the embedded system including the processor and the memory.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1 is a block diagram of an embedded system according to an embodiment of the present invention.

Referring to FIG. 1, an embedded system according to the present embodiment includes a processor 10, a data relocation circuit 20, and a memory 100.

The processor (eg, DSP core) 10 performs an operation of reading or writing data to the memory 100 every clock cycle. In particular, in the case of a DSP, several data are simultaneously read or written in every clock cycle. In the embedded system illustrated in FIG. 1, the logical memory address 11 output from the processor 10 is 16 bits. The logical memory address 11 is input to the data rearrangement circuit 20.

The data relocation circuit 20 translates the logical memory address 11 into a physical memory address 29. The logical memory address 11 is an address seen from the perspective of the program executed in the processor 10, while the physical memory address 29 is an address for accessing the actual memory. The logical memory address 11 is separated into a logical page address 21 and an offset address 22. For memory management, the whole memory is divided into certain units. Each division area is called a page. In the case of Fig. 1, since the logical page address 21 is 6 bits, there are 64 physical pages in the entire 16 bit memory address area. In addition, the memory 100 is divided into a plurality of memory banks 56, 57,..., 58. In the case of FIG. 1, there are eight memory banks. Therefore, one memory bank has a 13-bit physical offset address 55. In addition, one memory bank includes eight physical pages.

The page translator 26 in the data relocation circuit 20 generates the physical page address 28 with reference to the page valid flag 27.

2 is an operation flowchart of the page arranger 23.

Referring to FIG. 2, first, when a logical page address 21 is input, the page arranger 23 refers to the page valid flag 27 through the bus 25 whether the corresponding logical page is currently valid (200). ). A valid logical page means that a physical memory area indicated by the logical page exists in the current memory bank.

Check if the logical page is valid (210), and as a result, if the logical page is valid, the page locator 23 passes the logical page address 24 to the page converter 26. . The page converter 26 stores the physical page address 28 indicated by the requested logical page address 21 in advance in the internal page translation entry, and the page arranger 23 stores the logical page address 24. If it is transmitted, the corresponding physical page address 28 is output (220).

On the other hand, if the corresponding logical page is invalid as a result of the check, the page arranger 23 refers to the page converter 26 to map a new physical page address from the corresponding logical page address 21 (230). , 240, 250, 260).

Let's take a closer look at this process.

Referring to the page converter 26, the number of physical pages currently valid for each memory bank may be calculated. Representing an arbitrary memory bank i to B _i, and j represent the first physical page in the B _i to _{P, j} (B _i). Effective physical page number of the B _i | expressed as _{| P, j (B i)} . Page locator 23 finds memory bank I where | P _{, j} (B _i ) | is maximum and at least one invalid physical page exists, and any physical page J of invalid physical pages in B _I Find (230). That is, it finds an invalid physical page in a memory bank containing the maximum number of valid physical pages.

The page locator 23 writes 240 an invalid physical page J into an entry in the page converter 24 corresponding to the logical page address 21.

In addition, the valid flag of the invalid physical page J of the page valid flag unit 27 is changed to '1' (250), and the physical page address is output through the page converter 26 (260).

Meanwhile, the physical page address 28 output from the page converter 26 is concatenated with an offset address 22 except for the logical page address 21 among the logical memory addresses 11 output from the processor 10. Create a physical memory address 29.

The physical memory address 29 converted by the data rearrangement circuit 20 is input to the memory 100. The memory 100 is divided into a plurality of memory banks 56, 57,..., 58. Some of the upper bits of the bits of the physical memory address 29 are the bank select address 50, and the remaining bits are the physical offset address 55. In the case of FIG. 1, the bank select address 50 is 3 bits, and the physical offset address 55 is 13 bits. The bank select address 50 is decoded by the bank selector 51 to generate bank select signals 52, 53,..., 54. The select signals 52, 53, ..., 54 of each bank have only a maximum of one signal activated every clock cycle. Physical offset addresses 55 are input to all memory banks 56, 57,..., 58. The memory banks 56, 57, ..., 58 selected by the bank selection signals 52, 53, ..., 54 store or output data requested by the processor 10.

The power supply controller 60 in the data rearrangement circuit 20 outputs the memory bank power supply control signals 61, 62,..., 63. The power controller 60 refers to the page converter 26 and the page valid flag 27 to determine if there is at least one valid logical page in each memory bank 56, 57,..., 58. The power control signals 61, 62, ..., 63 are assigned to '0'. When the memory bank power control signals 61, 62, ..., 63 become '0', the power control transistors 64, 65, ..., 66 are turned on to supply power to the memory bank. If there is no valid logical page in each memory bank, the power controller 60 assigns a power control signal of the corresponding memory bank to '1'. When the memory bank power control signal becomes '1', the power control transistors 64, 65,..., 66 are turned off to cut off the power of the memory bank. When the power of the memory banks 56, 57, ..., 58 is cut off, the leakage current is cut off.

The processor 10 invalidates the logical page by outputting the page invalidation signal 80 to the page valid flag 27 when a specific logical page is no longer needed during a program operation. In this manner, only the physical pages necessary for the current processor operation in the memory 100 can be powered by the valid flag being '1'.

On the other hand, when the processor 10 is in the power down mode (power down mode), since all memory banks 56, 57, ..., 58 are not necessary for operation, the power controller 60 is connected to all memory banks 56, 57, ..., 58) The power supply is cut off.

3 shows an example of the contents of the page converter 26 and the page valid flag unit 27. Each store is arranged in a line and an address indicating each store arranged in a line becomes a logical page address 201. Each store pointed to by logical page address 201 has a number 202 of mapped physical memory banks, and a physical page number 203 within the physical memory bank. The page valid flag section 27 has a valid flag 204 corresponding to each store. Only the storage where the valid flag 204 is '1' actually represents the physical page that the processor 10 currently needs.

In an embedded system composed of a general processor 10 and a memory 100 without the data relocation circuit 20, the logical memory address 11 and the physical memory address 29 have the same value. In addition, memories required during program execution are distributed and belong to a plurality of memory banks, and all memory banks 56, 57,..., 58 may be supplied with power to perform normal operations. During operation of the processor 10, a powered memory bank generates a leakage current regardless of whether data is needed.

Using data rearrangement circuitry 20 as in the present invention, logical memory pages are actually mapped to physical memory pages when processor 10 requests memory pages. When mapping, the data relocation circuit 20 locates the logical memory page in the physical memory banks 56, 57, ..., 58 where the most logical memory pages currently exist. The set is located in the same memory banks 56, 57, ..., 58 as much as possible. The page placement algorithm shown in FIG. 2 may allow the number of physical memory banks that actually contain the necessary data to be minimal. In other words, the logical memory pages recognized by the processor 10 are not regular and are distributed in the entire memory area, but the memory banks to be powered by gathering and placing these logical memory pages in a minimum physical memory bank are located. The number of can be minimized. When the number of memory banks having valid data is minimum, the number of memory banks for which the processor 10 does not exist while the processor 10 is operating is also minimized, and there are other memory pages that are not necessary for the operation of the other processor 10. Since the memory banks are powered off, no leakage current is generated.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of an embedded system according to an embodiment of the present invention.

2 is an operation flowchart of a page layoutr.

3 is a diagram showing an example of contents of a page converter and a page valid flag unit.

* Explanation of symbols for the main parts of the drawings

10: processor

20: data redistribution circuit

100: memory

Claims (6)

A plurality of memory banks, If the logical page indicated by the logical page address input from the processor is valid, the logical page address is converted into a physical page address and output, and only the memory bank having at least one valid physical page of the memory banks is turned on. A data rearrangement circuit for generating a power control signal for the memory bank and providing the power control signal to the memory banks; A memory bank selector configured to receive and encode bit information indicating one of the plurality of memory banks from the output physical page address and to provide an enable signal to the memory bank indicated by the bit information Embedded system comprising a. The data relocating circuit of claim 1, wherein A page arrangement unit for determining whether a logical page indicated by the logical page address is valid by referring to a valid flag stored in advance, and outputting the logical page address when the determination result is valid; A page converter configured to receive the output logical page address and output the physical page address; A page valid flag unit for providing the valid flag to the page arrangement unit; A power controller configured to generate the power control signal with reference to the valid flag Embedded system comprising a. The data relocating circuit of claim 1, wherein If the logical page indicated by the logical page address is invalid, Find a memory bank having the most valid physical pages of the memory banks and having at least one or more invalid physical pages, modifying the invalid physical pages of the found memory banks to indicate the logical page address, An embedded system outputting a physical page address of the modified physical page. The data relocating circuit of claim 3, It is determined whether the logical page indicated by the logical page address is valid by referring to a predetermined valid flag. If the result is not valid, the logical page has the most valid physical pages among the memory banks and has at least one or more invalid physical pages. A page layout unit for finding a memory bank having a memory and changing the invalid physical page of the found memory bank to indicate the logical page address; A page converter for outputting a physical page address of the changed physical page; A page valid flag unit for providing the valid flag to the page arrangement unit and changing the valid flag of the logical page address to be valid; A power controller configured to generate the power control signal with reference to the valid flag Embedded system that includes A page relocation method for an embedded system including a processor and a plurality of memory banks, the method comprising: Determining whether a logical page indicated by the logical page address input from the processor is valid; If the logical page is invalid, finding a memory bank having a maximum valid physical page among the memory banks and having at least one invalid physical page; Modifying an invalid physical page of the found memory bank to indicate the logical page address Including, page relocation method. delete

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