JP2005196343A - Memory management device, memory management method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: in memory management in a virtual address space, the whole physical address space is dotted with data, so that power cannot be turned off in any memory bank. <P>SOLUTION: The memory banks 3a-3d are set with priority of address allocation. An unused head address register 132 stores an unused head address in priority order of the address allocation. In time of a page registration process, a page registration/deletion processing part 131 performs the allocation to the unused head address, retrieves the next unused head address, and turns off the power of other memory bank when the next unused head address is the other memory bank. In time of a page deletion process, the page registration/deletion processing part 131 releases a deletion target address, sets the release address as the unused head address when the unused head address is below the release address, and turns off the power of the other memory bank when the original unused head address belongs to the other memory bank and when an already allocated address is absent in the other memory bank. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a power management technique for a computer system, and more particularly to power saving of a computer system such as a mobile phone that requires battery operation.

  As a technique related to memory power saving in an operating system that manages memory in a virtual address space, there is a “computer system and a power management method for a computer system” described in Japanese Patent Laid-Open No. 9-212416.

  In the computer system, the program and data being executed are stored in a volatile memory, and it is necessary to always turn on the power to maintain the contents. In order to save power, a method of reducing the power-on range by dividing the memory into a plurality of banks and turning on only the banks that need to retain the contents is used.

In Japanese Patent Laid-Open No. 9-212416, bank power on / off control is performed in an operating system memory. The memory management unit controls area allocation and release using the memory area management table. The memory area management table stores the head address, size, and bank information for each continuous free area or used area. The memory power management unit checks the current memory usage state from the contents of the management table, and if there is an unused memory bank, the power of the corresponding memory bank is turned off or DRAM refresh is stopped to save power.
JP-A-9-212416

  The conventional method disclosed in Japanese Patent Application Laid-Open No. 9-212416 has a problem that even if there is a small amount of data, if there is data in a certain memory bank, the power of the memory bank cannot be turned off. In an operating system that manages memory in the virtual address space, the data requested by the application is assigned to a vacant physical address each time, so the data is scattered throughout the physical address space after operating for a while. become. Therefore, although the total memory consumption is small, there arises a problem that no memory bank can be turned off.

  The present invention has been made in order to solve the above-described problems. For the operating system that manages the memory in the virtual address space, the address allocation is preferentially performed to the memory bank in use. An object is to save power by turning off the power of the memory bank.

The memory management device according to the present invention includes:
A memory management device for managing a plurality of memory banks,
Set the priority for address assignment for each memory bank,
When assigning addresses, based on the priority of each memory bank and the order of the addresses in each memory bank, among the unused addresses, the priority is assigned in order from the upper address in the upper memory bank. When an address in a memory bank having a higher level is assigned to a certain level or more, unused addresses in a memory bank having a lower priority are assigned in order from the higher address.

  According to the present invention, at the time of address allocation, among the unused addresses, the priority is assigned in order from the upper address in the higher-order memory bank, and the addresses in the higher-priority memory bank are more than a certain level. When assigned, unused addresses in the lower priority memory bank are assigned in order from the higher address, so that the memory bank in use can be used preferentially, and the entire physical address space In other words, it is possible to avoid a situation where data is scattered, and by deactivating unused memory banks, it is possible to save power in memory management.

Embodiment 1 FIG.
FIG. 1 is a hardware configuration diagram of a computer system 100 according to the present embodiment.

  In the figure, 1 is a CPU (Central Processing Unit) for processing an operating system and application programs, 2 is a memory management unit for converting programs and data processed by the CPU 1 from logical addresses to physical addresses, and 3a to 3d are memory management units 2 4 is a power supply control circuit for controlling power on / off of the memory banks 3a to 3d. Memory banks 3a to 3d operate as a main storage device. Further, the priority in address allocation is set for each of the memory banks 3a to 3d. Here, the memory bank 3a has the highest priority, and the priority becomes lower toward the memory bank 3d. And The CPU 1, the memory management unit 2, and the power supply control circuit 4 function as the memory management device 200.

  FIG. 2 is a software configuration diagram of the computer system 100 according to the present embodiment.

  In the figure, 10 is an operating system operating on the CPU 1, 20 is an application program, 11 is a process management unit that manages activation and termination of the application program in the operating system 10, and 12 is an exception interrupt generated in the memory management unit 2. Exception processing unit 13 that performs processing at the time of processing, page management that releases the allocated physical memory in response to a page deletion request from process management unit 11 or a page registration request from exception processing unit 12 or newly allocates page management A data processing unit 14, page management data for storing information necessary for page registration / deletion by the page management data processing unit 13, and 15 a memory power control unit for sending a memory power control instruction to the power control circuit 4 It is.

  Further, the page management data processing unit 13 includes a page registration / deletion processing unit 131 and an unused head address register 132. The unused head address register 132 stores an unused head address located at the head in the priority order of address allocation. Here, the priority of address allocation is the target of address allocation in order from the upper address in the memory bank with the higher priority, and when all the addresses in the memory bank with the higher priority are allocated, It is assumed that the memory bank moves to a lower priority memory bank, and the lower priority memory banks are also subject to address assignment in order from the higher address.

  The page registration / deletion processing unit 131 is an example of an address assignment management unit, and the memory power control unit 15 is an example of a power supply control unit.

  Next, the operation will be described.

  When data access occurs in the application program 20, the CPU 1 sends a logical address to the memory management unit 2. Usually, the operating system handles a fixed size of several kilobytes as one unit (page), and the correspondence between the logical address and physical address for each page is stored in the page management data 14. The memory management unit 2 refers to the page management data 14, converts it to a physical address, sends the physical address to the memory banks 3a to 3d, and writes or reads the data.

  When an access to an unregistered logical address occurs, the memory management unit 2 generates an exception interrupt to the CPU 1. The exception interrupt is received by the CPU 1 and analyzed by the exception processing unit 12 of the operating system 10 operating on the CPU 1. When the exception processing unit 12 determines that the request is for a new page registration, it issues a page registration request to the page management data processing unit 13.

  The page registration / deletion processing unit 131 of the page management data processing unit 13 performs registration processing (address allocation processing) in the processing flow shown in FIG.

  That is, in ST11, the unused start address register 132 is referred to read the top physical address (unused start address) of the memory free area, and in ST12, the read physical address is used as the physical address of the page to be registered. Registered in the management data 14 (assignment to an unused head address). Subsequently, in order to update the contents of the unused head address register 132, the contents of the unused head address register 132 are increased by one page in ST13, and whether the same physical address is already used in ST14 is checked in the page management data 14. Search for.

  If the physical address has already been used, the process returns to ST13 to increase the value of the unused head address register 132 until an unused physical address is found. If a physical address that is not used is found, the search is terminated, and the value of the found physical address is set as the update value of the unused head address register 132. Note that the unused head address newly registered in the unused head address register is an address to be allocated at the next address allocation.

  Further, in ST15, if the updated physical address value of the unused first address register 132 has reached another memory bank with respect to the previous address value, the page registration / deletion processing unit 131 sets the memory power control unit in ST16. 15 is instructed to turn on (activate) the power of the memory banks 3a to 3d indicated by the unused head address register 132 updated.

  The above process will be specifically described with reference to FIGS. 13 and 14.

  In FIG. 13, the white portion of the addresses in the memory bank 3a indicates an unused address, and the colored portion indicates an assigned address. In the state of FIG. 13A, the address 301 is an unused head address, and the address 302 is an unused address positioned next to the address 301 in the priority order of address allocation. When the page registration process (address allocation process) is performed in the state of FIG. 13A, the address 301 that is an unused head address is to be allocated, and as shown in FIG. 13B, the address 301 is allocated. The address 302 that is the next unused address becomes the new unused head address and is registered in the unused head address register 132.

  Next, FIG. 14 will be described. In FIG. 14A, the address 301 is an unused head address in the memory bank 3a, and all addresses are unused in the memory bank 3b. The address 303 of the memory bank 3b is an unused address at the next position after the address 301 in the priority order of address assignment. In the state of FIG. 14A, the memory bank 3a is in the power-on state, but the memory bank 3b is in the power-off state. Here, when page registration processing (address allocation processing) is performed, an address 301 that is an unused head address is an allocation target, and the address 301 is an allocated address. Therefore, the address 303 of the memory bank 3b becomes an unused head address, and the memory bank 3b is turned on (activated).

  In this way, when assigning addresses, among the unused addresses, the priority is assigned in order from the upper address in the higher priority memory bank, and all addresses in the higher priority memory bank are assigned. In this case, the unused addresses in the lower priority memory bank are assigned in order from the higher address, so that the memory bank in use can be used preferentially, and data is stored in the entire physical address space. It is possible to avoid the situation of being scattered, and since the lower memory bank is powered on only when the updated unused head address belongs to the lower memory bank, it is possible to save power in memory management. it can.

  Next, when the application program 20 ends and the used data becomes unnecessary, the process management unit 11 recognizes the end of the application program 20 and requests the page management data processing unit 13 to delete the data.

  The page registration / deletion processing unit 131 of the page management data processing unit 13 performs deletion processing (address release processing) in the processing flow shown in FIG.

  That is, in ST21, the page data to be deleted is searched with reference to the page management data 14. If the process ID and the like are stored in the page management data 14 at the time of registration (address assignment), the page data to be deleted can be found by searching for the process ID to be deleted.

  When an entry to be deleted is found in the page management data 14, the target entry is changed to an unused state in ST22, that is, the address to be released is released, and the physical address (released address) of the deleted page is released in ST23. ) And the unused start address indicated by the unused start address register 132. When the physical address of the deleted page is smaller, that is, when it is positioned higher in the priority order of address allocation, the value of the unused head address register 132 is updated to the physical address of the deleted page in ST26.

  Further, the memory bank indicated by the unused start address register 132 before update (the memory bank to which the unused start address before update) belongs, and the memory bank indicated by the unused start address register after the update (memory bank to which the released address belongs) ) Are different, in ST24, the page management data 14 is searched for whether the physical address range of the memory bank indicated by the unused leading address register 132 before the update is used elsewhere. If not used, in ST25, the page registration / deletion processing unit 131 instructs the memory power supply control unit 15 to turn off the power to the memory bank indicated by the unused head address register 132 before update.

  The above process will be specifically described with reference to FIGS.

  In FIG. 15, the white portion of the addresses in the memory bank 3a indicates an unused address, and the colored portion indicates an assigned address. In the state of FIG. 15A, the address 301 is an unused head address. For example, as shown in FIG. 15B, an address 304 behind the address 301 that is the unused head address, that is, an address 304 that is positioned lower than the unused head address in the priority order of address allocation becomes the release target. In this case, the unused head address remains the address 301. On the other hand, as shown in FIG. 15 (c), an address ahead of the address 301 that is an unused head address, that is, an address 305 that is positioned higher than the unused head address in the priority order of address allocation is to be released. In this case, the address 305 becomes a new unused head address and is registered in the unused head address register 132.

  Next, FIG. 16 will be described. In FIG. 16A, all the addresses of the memory bank 3a have been assigned, and the address 301 of the memory bank 3b is an unused head address. In the memory bank 3b, there is an assigned address. In the state of FIG. 16A, both the memory bank 3a and the memory bank 3b are in a power-on state. Next, when the address 306 of the memory bank 3a is to be released, the address 306 is an unused address that is positioned higher than the address 301 in the priority order of address allocation. This is the start address. Further, since the allocated address exists in the memory bank 3b, the memory bank 3b remains powered on.

  Next, FIG. 17 will be described. In FIG. 17A, all addresses of the memory bank 3a have been assigned, and the address 301 of the memory bank 3b is an unused head address. In the memory bank 3b, all are unused addresses. In the state of FIG. 16A, both the memory bank 3a and the memory bank 3b are in a power-on state. Next, when the address 307 of the memory bank 3a is to be released, the address 307 is an unused address that is positioned higher than the address 301 in the priority order of address allocation. This is the start address. Since all addresses in the memory bank 3b are unused addresses, the memory bank 3b is turned off (inactivated).

  Here, consider a case where the operation and termination of a plurality of application programs 20 are repeated. At this time, a plurality of page registrations and page deletions are collectively performed, and there are cases where empty areas are scattered in the upper memory bank 3a. Therefore, an empty memory bank is created by periodically searching for an empty area and moving data.

  FIG. 5 is a processing flow of data movement. In ST31, the unused head address register 132 is checked. Since the unused head address register 132 always indicates the highest address of the empty area, if this value indicates the lowest memory bank address, an empty memory bank cannot be created. finish.

  Subsequently, in ST32, whether there is data indicating a memory bank address lower than the memory bank indicated by the address of the unused head address register 132, that is, an allocation located lower than the unused head address in the priority order of address allocation. The page management data 14 is searched for whether or not a completed address exists. If present, the page data is copied to the physical address indicated by the unused head address register 132 at ST33, and the physical address information indicated by the page management data 14 is the value indicated by the unused head address register 132 at ST34. Change to In ST35, the next empty area is searched from within page management data 14, the value of unused head address register 132 is updated, and the process returns to ST31 and the process is repeated.

  If there is no data indicating a memory bank lower than the memory bank indicated by the address of the unused head address register 132 in ST32, the power of the lower memory bank is turned off and the data movement process is terminated.

  As described above, when deleting a page, if the address deleted in the next page registration is smaller than the address assigned in the next page registration, the address assigned in the next page registration is changed to the deleted page address. The memory bank in use can be used preferentially, and the power of other memory banks can be turned off. As a result, power saving in memory management can be achieved.

  Also, by deciding the next address to be assigned after registering and deleting a page, address assignment as seen from the application program can be performed instantaneously, so that a penalty when an exception occurs can be reduced and performance degradation can be prevented.

  Further, by periodically searching for an empty data area and moving the data in the lower memory bank, it is possible to further increase the utilization rate of the memory bank in use and turn off the power to the other memory banks.

Embodiment 2. FIG.
In the first embodiment described above, data is registered and deleted on the operating system 10. Next, an embodiment in which page allocation processing is realized by hardware will be described.

  FIG. 6 is a hardware configuration diagram showing the present embodiment.

  In the figure, 5 is used for each page of the physical memory (for each address), a bitmap table indicating unused bits by bit flags, and 61a is used for any one of bitmap tables indicating pages of the memory bank 3a. Indicates an OR circuit indicating 1; 61b is an OR circuit of the same function corresponding to the memory bank 3b; and 62a and 62b are AND circuits that supply power to the memory banks 3a and 3b when the outputs of the OR circuits 61a and 62b are 1, respectively. The circuit 63 has the same input as the OR circuit 61a, and an AND circuit indicating 1 if all the bitmap tables indicate use. 7 is a flag register for page registration / deletion requests from the operating system 10 operating on the CPU 1. Flag management that responds to newly assigned physical addresses for page registration It is a road.

  In FIG. 6, the power supply control circuit 4 is an example of a power supply circuit, the bitmap table 5 is an example of an allocation status table, the OR circuit 61a and the OR circuit 61b are examples of an activation signal output circuit, and AND The circuit 62a and the AND circuit 62a are examples of a power supply control circuit, the AND circuit 63 is an instruction signal output circuit, and the flag management circuit 7 is an example of an address assignment management circuit. The signals output from the OR circuits 61a and 61b when any address is indicated in the bitmap table are examples of activation signals. A signal output from the AND circuit 63 to the OR circuit 61b when the bit map table indicates that all of the memory banks 3a are in use is an example of an instruction signal.

  Next, the operation will be described.

  When a new page is registered in the operating system 10, the request is notified to the flag management circuit 7. The flag management circuit 7 refers to the contents of the bitmap table 5 and searches for a free area.

  As a search method, the method of FIG. 7 is used. That is, the priority order is set so that the memory banks 3a to 3d are used in order from, for example, 3a, and the flag management circuit 7 searches for a free area from the bitmap table 5 for the memory bank 3a. If a free area is not found, the memory bank 3d is searched for, for example, by searching the bitmap table 5 for the memory bank 3b.

  Another search method is the method shown in FIG. In other words, a search area is provided for the resident memory such as the operating system and middleware and the memory that becomes unnecessary when the execution of the application program is completed, and the resident and non-resident memory requests are notified separately when a page registration request is issued from the operating system. To do. The flag management circuit 7 searches each area for empty areas in order from the smallest address. In the example of FIG. 8, for the operating system, an address is assigned to a memory bank with a higher priority, and for the application program, an address lower than the address assigned to the operating system is assigned.

  After an address to be newly allocated is searched by the flag management circuit 7, the address allocated to the operating system 10 is returned and the corresponding bit of the bitmap table 5 is set to 1.

  As a result of setting the bitmap table 5, for example, when all the areas of the memory bank 3a are in use, the bits of the memory bank 3a are all 1. The output of the AND circuit 63 changes from 0 to 1 (instruction signal is output), thereby changing the OR circuit 61b corresponding to the memory bank 3b from 0 to 1 (outputs the activation signal) and further corresponds to the memory bank 3b. When the AND circuit 62b to be changed from 0 to 1, power supply to the memory bank 3b is started.

  Conversely, when a page deletion request is notified from the operating system 10, the deletion target address is notified together with the deletion request. The flag management circuit 7 clears the bit of the bitmap table 5 corresponding to the notified address and changes it to unused.

  At this time, for example, when a page area on the memory bank 3a is deleted while all the areas of the memory bank 3a are in use, the output of the AND circuit 63 changes from 1 to 0 (stops the output of the instruction signal), The OR circuit 61b corresponding to the memory bank 3b is changed from 1 to 0 (the output of the activation signal is stopped), and the AND circuit 62b corresponding to the memory bank 3b is changed from 1 to 0, so that power is supplied to the memory bank 3b. Is canceled.

  Here, it is assumed that the AND circuit 62b has hysteresis characteristics as shown in FIG. That is, when the input becomes 1 and power is supplied, the operation is instantaneous. As described above, when the deletion of all the areas in the memory bank 3a and the state where all the registered areas are in use repeatedly occur in a short time, the hysteresis characteristic of the AND circuit 62b causes Energization continues.

  The bit map table 5, the flag management circuit 7 and each logic circuit can be incorporated in the memory management unit 2 or the memory interface of the CPU 1 in addition to the hardware control power supply control circuit shown in FIG.

  As described above, by using the bitmap table 5 and the flag management circuit 7, the operating system does not manage the free area in the memory and assign the physical address, so that the burden on the CPU 1 is reduced and the performance is improved. Can do.

  Further, by providing hysteresis characteristics to the AND circuit 62b, when registration and deletion are repeatedly executed at the memory bank boundary, the memory bank continues to be energized, thereby reducing the overhead time at the start of energization and turning off the power. Since the current increase due to the discharge at the time and the charge at the time of ON can be eliminated, the performance can be improved and the power can be reduced.

Embodiment 3 FIG.
The above embodiment relates to memory power saving at the time of data registration and deletion. Next, an embodiment related to memory power saving at the time of an idle state where the CPU 1 is not operating will be described. FIG. 10 is a software configuration diagram showing the present embodiment.

  In the figure, 16 is a power management unit provided in the operating system 10, 161 is an operation mode management unit that monitors the operation of the CPU 1 in the power management unit 16 and switches between the power saving mode and the operation mode, and 162 is an operation mode management unit. When the mode is switched in 161, a backup processing unit for performing backup and restore processing, and 17 is backup management data for storing information on the backed up data.

  In FIG. 10, a backup processing unit 162 is an example of a data movement management unit, and a memory power supply control unit 15 is an example of a power supply control unit. The backup management data generated by the backup processing unit 162 is an example of data movement management information.

  Next, the operation will be described. The operation mode management unit 161 starts the timer count when the processing of the CPU 1 is lost and the input from the outside is awaited. If no input occurs after a certain period of time has elapsed, the operation mode management unit 161 switches the CPU mode from the operation mode to the power saving mode, and at the same time requests the backup processing unit 162 to start backup.

  The backup processing unit 162 performs the processing sequence shown in FIG. That is, in ST41, the value of the unused head address register is substituted into the target register, and in ST42, the data at the lowest address in use (allocated) is searched from page management data 14, and this is stored in the source register. substitute. In ST43, the values of the target register and the source register are compared. If the same memory bank 3a is indicated, the power supply to the lower memory banks 3b to 3d is turned off in ST48 and the backup process is terminated.

  If the memory bank is different in ST43, backup of page data is executed in ST44. Specifically, the page data indicated by the source register is copied (moved) to the target register. In ST 45, for example, backup information as shown in FIG. 12 is created and stored in the backup management data 17. In ST46 and ST47, the address indicated by the target register is changed to the next empty area, and the process returns to ST42.

  If an interrupt such as a key input occurs during the backup process, the backup process is immediately stopped and the normal mode is restored. If an interrupt occurs after the backup memory bank is turned off after the backup process is completed, the backup processing unit 162 enters the restore process. That is, the page data of the destination address is copied (moved) to the source address according to the backup management data 17. After the completion of this work, the operation mode management unit 161 returns to the operation mode.

  Note that, at the time of backup, the data is copied to the address of the target register, but at this time, the data may be compressed. At the time of restoration, it is restored to the source address while expanding.

  As described above, since the data of the lower memory bank is copied (moved) to the empty area of the upper memory bank when there is no processing by the CPU 1, the power of the memory bank can be turned off without affecting the application performance.

  Also, since the memory bank is turned off after all backups are completed, if an interrupt occurs during the backup process, it can be immediately terminated to return to the operation mode without interrupting the interrupt response performance. The memory bank can be powered off.

  In the above first to third embodiments, the case where the power supply to the memory bank is started as the activation of the memory bank has been described. However, as an example of the activation, a refresh operation of a DRAM (Dynamic Random Access Memory) is performed. You may make it start. Similarly, in the first to third embodiments, the case where the power supply to the memory bank is stopped as the deactivation of the memory bank has been described. However, the refresh operation of the DRAM is stopped as an example of deactivation. You may make it do.

  Here, the characteristics of the memory management device described in the first to third embodiments will be described again below.

The memory management device shown in the first embodiment is an operating system that manages memory in a virtual address space, and includes the following means for powering off some banks of the memory and saving power when the memory usage is low Features:
(A) A register that stores an unused head address in the page management data processing unit (b) A memory power control unit that turns on / off the power of the memory bank in accordance with an instruction from the page management data processing unit (c) At page registration A page management data processing unit that increases the unused head address and sets the unused head address to the smallest address deleted when the page is deleted.

The memory management device shown in the second embodiment is an operating system that manages memory in a virtual address space, and includes the following means for powering off a part of the banks of the memory to save power when the memory usage is low Features:
(A) Bit map table indicating use / unuse for each memory allocation unit of the operating system (b) OR circuit indicating in use if any of the bit maps corresponding to the same bank memory is used (c) An AND circuit that ANDs an OR output and a power source and supplies power only to a memory bank indicating that it is in use.

  The memory management device described in the second embodiment is characterized in that hysteresis is provided in the AND circuit, and the characteristics are such that the power-on condition is instantaneously turned off and the power-off condition is turned off after a certain period of time. And

  The memory management device described in the second embodiment is characterized in that an AND circuit is provided in parallel with the OR circuit and is input to the OR circuit of the next bank to be used.

  The memory management device described in Embodiment 2 includes a processing device different from the CPU that processes the operating system, and changes the bitmap in response to a data registration / deletion request from the operating system.

  The memory management device shown in the first and second embodiments includes a processing device different from the CPU that processes the operating system, searches for a free area in response to a data registration request from the operating system, and responds with an address. Features.

  The memory management devices shown in the first and second embodiments are characterized in that a priority is set for each memory bank, and a low-priority memory bank starts to be used after a high-priority memory bank runs out of space.

  The memory management device shown in the second embodiment is characterized in that a resident operating system and middleware are assigned to the upper memory physical address, and an application that consumes memory only when used is assigned to the lower address.

  The memory management device shown in the first embodiment is characterized in that it periodically searches the used area of the physical memory and reassigns the data assigned to the lower address to the free space of the upper address.

When the CPU is switched to the power saving mode, the memory management device shown in the third embodiment copies the data at the lower address of the memory physical space to the empty area of the upper address and turns off the memory bank at the lower address to save power. In order to make it easier, the following means are provided:
(A) Backup management data for storing the copy destination and copy source address of the copied data (b) Memory power supply control unit for controlling power on / off of the memory bank in accordance with an instruction from the backup processing unit (c) Power-saving mode of the CPU Backup processing unit that starts backup when switching to, and restores it with an interrupt request.

  The memory management devices shown in the first to third embodiments are characterized in that power saving is achieved by stopping the refresh operation of the DRAM instead of turning off the memory power.

The figure which shows the structural example of the computer system which concerns on Embodiment 1-3. 1 is a diagram illustrating a configuration example of a memory management device according to Embodiment 1. FIG. FIG. 3 is a flowchart showing a processing flow of page registration processing according to the first embodiment. FIG. 4 is a flowchart showing a processing flow of page deletion processing according to the first embodiment. FIG. 3 is a flowchart showing a processing flow of data movement processing according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a memory management device according to a second embodiment. FIG. 10 is a diagram for explaining a method for searching for a memory free area according to the second embodiment. FIG. 10 is a diagram for explaining a method for searching for a memory free area according to the second embodiment. FIG. 6 is a diagram for explaining hysteresis characteristics of an AND circuit according to Embodiment 2; FIG. 10 is a diagram illustrating a configuration example of a memory management device according to a third embodiment. FIG. 9 is a flowchart showing a processing flow of backup processing according to the third embodiment. FIG. 10 is a diagram for explaining an example of backup management data according to the third embodiment. FIG. 6 is a diagram for explaining page registration processing according to the first embodiment. FIG. 6 is a diagram for explaining page registration processing according to the first embodiment. FIG. 6 is a diagram for explaining page deletion processing according to the first embodiment. FIG. 6 is a diagram for explaining page deletion processing according to the first embodiment. FIG. 6 is a diagram for explaining page deletion processing according to the first embodiment.

Explanation of symbols

  1 CPU, 2 memory management unit, 3 memory bank, 4 power supply control circuit, 5 bitmap table, 7 flag management circuit, 10 operating system, 11 process management unit, 12 exception processing unit, 13 page management data processing unit, page 14 Management data, 15 Memory power control unit, 16 Power management unit, 17 Backup management data, 20 Application program, 61 OR circuit, 62 AND circuit, 63 AND circuit, 100 computer system, 131 Page registration / deletion processing unit, 132 Not used Start address register, 161 operation mode management unit, 162 backup processing unit, 200 memory management device.

Claims (26)

A memory management device for managing a plurality of memory banks,
Set the priority for address assignment for each memory bank,
When assigning addresses, based on the priority of each memory bank and the order of the addresses in each memory bank, among the unused addresses, the priority is assigned in order from the upper address in the upper memory bank. A memory management device characterized in that, when an address in a higher-order memory bank has been assigned a certain level or more, unused addresses in a lower-priority memory bank are assigned in order from the higher-order address. . The memory management device includes:
If any of the allocated addresses is released and the released address is an unused start address located at the top in the priority order of address allocation, the allocated address is given priority. The memory management device according to claim 1, wherein The memory management device includes:
Every time an address is assigned, a search is made for an unused start address located at the top in the priority order of address assignment as an assignment target for the next address assignment. 2. The memory bank according to claim 1, wherein when a predetermined address is allocated to a certain level or more and an unused head address belongs to a memory bank with a lower priority, the memory bank with the lower priority is activated. The memory management device described. The memory management device includes:
When releasing an address, whether or not the address to be released is higher in the priority order of address assignment than the unused head address located at the head in the priority order of address assignment at the time of release of the address to be released When the address to be released is higher in the address allocation priority order, the address to be released is set as an unused head address, and when the address is allocated after the address to be released is released, 3. The memory management apparatus according to claim 2, wherein the address to be released is an allocation target. The memory management device includes:
When an address is released, if the address to be released is higher in the address assignment priority than the first unused address in the address assignment priority at the time of release of the address to be released It is determined whether or not the target address and the unused head address belong to the same memory bank. If the target address and the unused head address belong to different memory banks, the memory address to which the unused head address belongs To determine whether or not there is an assigned address, and if there is no assigned address in the memory bank to which the unused head address belongs, the memory bank to which the unused head address belongs is deactivated. The memory management device according to claim 4, wherein: The memory management device includes:
In a predetermined case, the allocation status of each memory bank is analyzed, and when an address located at a lower position in the priority order of address assignment than an unused head address located at the top position in the priority order of address assignment is assigned, 2. The memory management device according to claim 1, wherein the data of the allocated address located in the lower order is moved to an unused head address. The memory management device includes:
Deactivate a memory bank with a lower priority than the memory bank to which the unused head address belongs when all addresses located lower in the address allocation priority than the unused head address are unused. The memory management device according to claim 6, wherein: The memory management device includes:
4. The memory management device according to claim 3, wherein the activation of the memory bank includes at least one of start of power supply to the memory bank and start of refresh operation for the memory bank. The memory management device includes:
8. The memory management device according to claim 5, wherein at least one of stopping power supply to the memory bank and stopping refresh operation for the memory bank is performed as deactivation of the memory bank. The memory management device includes:
An unused head address register for storing an unused head address located at the head in the priority order of address allocation;
At the time of address allocation, allocation is performed for the unused head address stored in the unused head address register, and address allocation is performed among the unused addresses positioned lower in the priority order of address allocation than the unused head address. The new unused head address is searched for as a new unused head address, and the new head address that has been searched for is assigned to the next address assignment. The memory management device according to claim 1, further comprising an address allocation management unit that stores an unused head address. The memory management device further includes:
A power supply control unit that controls power supply to each memory bank in accordance with an instruction from the address allocation management unit;
The address assignment management unit
As a result of a search for a new unused head address, the power is determined when the searched new unused head address belongs to a memory bank different from the memory bank to which the unused head address stored in the unused head address register belongs. 11. The memory management device according to claim 10, wherein the memory management device instructs the supply control unit to start power supply to a memory bank to which a new unused head address belongs. The address assignment management unit
When releasing the address, release the address to be released, and whether the address to be released is higher in the priority order of address allocation than the unused head address stored in the unused head address register When the address to be released is higher in the address allocation priority order, the address to be released is stored in the unused head address register so that the address to be released is assigned at the next address allocation. The memory management device according to claim 10, wherein: is stored as a new unused head address. The memory management device further includes:
In accordance with an instruction from the address allocation management unit, a power supply control unit that controls power supply to each memory bank,
The address assignment management unit
When releasing an address, if the address to be released is higher in the priority order of address allocation than the unused head address stored in the unused head address register, the address to be released and the unused head address If the addresses to be released belong to a different memory bank, and there is an allocated address in the memory bank to which the unused head address belongs If there is no allocated address in the memory bank to which the unused head address belongs, the power supply control unit is configured to stop power supply to the memory bank to which the unused head address belongs. The memory management device according to claim 12, wherein the memory management device instructs the memory management device. The address assignment management unit
In a predetermined case, the allocation status of each memory bank is analyzed, and when an address located lower in the priority order of address allocation than the unused head address stored in the unused head address register is already allocated, 11. The memory management device according to claim 10, wherein the data of the allocated address located in the lower order is moved to an unused head address. The memory management device further includes:
In accordance with an instruction from the address allocation management unit, a power supply control unit that controls power supply to each memory bank,
The address assignment management unit
A memory having a lower priority than the memory bank to which the unused head address belongs to the power supply control unit when all addresses located lower in the priority order of address allocation than the unused head address are unused. The memory management device according to claim 14, wherein the memory management device instructs to stop power supply to the bank. The memory management device includes:
An operating system that manages memory in a virtual address space;
In response to a page registration request from the operating system, an address allocation management circuit that is a target of address allocation in order from a higher address in a memory bank having a higher priority,
Corresponding to each memory bank, based on the allocation status by the address allocation management circuit, an allocation status table indicating whether or not allocation is performed for each address in the corresponding memory bank;
Multiple activation signal outputs corresponding to each allocation status table and outputting an activation signal instructing activation of the memory bank when the corresponding allocation status table indicates that any address has been allocated Circuit,
A power supply circuit connected to each memory bank and supplying power to each memory bank;
Corresponding to each memory bank and each activation signal output circuit, when the corresponding memory bank, the corresponding activation signal output circuit and the power supply circuit are connected, and the activation signal is output from the corresponding activation signal output circuit The memory management device according to claim 1, further comprising: a plurality of power supply control circuits that supply power from a power supply circuit to a corresponding memory bank. Each of the activation signal output circuits
When the corresponding allocation status table indicates that all addresses are unused, the output of the activation signal is stopped,
Each of the power supply control circuits
17. The memory management device according to claim 16, wherein when the output of the activation signal from the corresponding activation signal output circuit is stopped, the power supply from the power supply circuit to the corresponding memory bank is stopped. Each of the power supply control circuits
18. The memory management device according to claim 17, wherein when the power supply is started, the power supply is instantaneously started, and when the power supply is stopped, the power supply is stopped after a predetermined time. The memory management device further includes:
Corresponding to each allocation status table, connected to the activation signal output circuit corresponding to the memory bank having the next priority of the memory bank corresponding to the corresponding allocation status table, all from the corresponding allocation status table A plurality of instruction signal output circuits for outputting an instruction signal for instructing output of the activation signal to the connected activation signal output circuit when the address of
Each activation signal output circuit
17. The memory management device according to claim 16, wherein when an instruction signal is output from a connected instruction signal output circuit, an activation signal is output to a corresponding power supply control circuit.   The memory management device according to claim 16, wherein the activation signal output circuit is an OR circuit, and the power supply control circuit is an AND circuit. The address assignment management circuit includes:
For at least one of the operating system and middleware, addresses are assigned in order from the upper address in the memory bank having the higher priority, and for the application program, an address assigned to at least one of the operating system and middleware. 17. The memory management device according to claim 16, wherein an address located at a lower position in the priority order of address assignment is assigned. The memory management device includes:
An operation mode management unit that switches a CPU (Central Processing Unit) mode between an operation mode and a power saving mode in a predetermined case;
An unused head address register for storing an unused head address located at the head in the priority order of address allocation;
When the CPU mode is switched to the power saving mode by the operation mode management unit, the unused head address stored in the unused head address register and the allocated address are positioned at the lowest in the priority order of address allocation. When the lowest assigned address is compared and both belong to different memory banks, the data of the lowest assigned address is moved to an unused head address, and the operation mode management unit switches the CPU mode to the operation mode. 2. The memory management according to claim 1, further comprising a data movement management unit that moves data moved to an unused head address when the CPU is switched to a power saving mode to a lowest allocated address. apparatus. The data movement management unit
When the CPU mode is switched to the power saving mode, data movement management information indicating the lowest allocated address as the movement source address and the unused head address as the movement destination address is generated,
23. The memory management according to claim 22, wherein when the CPU mode is switched to the operation mode, the data moved to the unused head address is moved to the lowest allocated address using the data movement management information. apparatus. The memory management device further includes:
In accordance with an instruction from the data movement management unit, a power supply control unit that controls power supply to each memory bank,
The data movement management unit
When the CPU mode is switched to the power saving mode, as a result of comparing the unused head address and the lowest allocated address, if both belong to the same memory bank, the unused head address and the lowest allocated address 23. The memory management device according to claim 22, wherein the power supply control unit is instructed to stop power supply to a memory bank having a lower priority than a memory bank to which the memory bank belongs. A memory management method for managing a plurality of memory banks,
Set the priority for address assignment for each memory bank,
When assigning addresses, based on the priority of each memory bank and the order of the addresses in each memory bank, among the unused addresses, the priority is assigned in order from the upper address in the upper memory bank. A memory management method characterized in that, when an address in a higher-order memory bank is assigned a certain level or more, unused addresses in a lower-priority memory bank are assigned in order from the higher-order address. . A program for causing a computer to execute a memory management process for managing a plurality of memory banks,
Set the priority for address assignment for each memory bank,
When assigning addresses, based on the priority of each memory bank and the order of the addresses in each memory bank, among the unused addresses, the priority is assigned in order from the upper address in the upper memory bank. When the address in the upper memory bank is assigned to a certain level or more, let the computer execute a process that assigns unused addresses in the lower priority memory bank in order from the higher address. A featured program.

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