KR100938093B1 - Non volatile memory device and method of operating the same - Google Patents

Abstract

The present invention relates to a nonvolatile device, comprising: a memory cell array including memory blocks including a first wordline group for storing data and a second wordline group for storing erase count information; A page buffer which loads the erase count information stored in the second word line group to increase the number of times by 1 and temporarily stores the erase count information. part; And a controller configured to control an erase start voltage when the memory block is erased according to the erase count information loaded from the second word line group.

Clear, EW Cycle, Threshold Compensation

Description

Nonvolatile memory device and method of operation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of erasing a nonvolatile memory device, and more particularly, to a nonvolatile memory device reflecting a threshold voltage of a memory cell that changes as an erase / program cycle progresses and a method of operating the same.

A flash memory device, which is one in a nonvolatile memory device, is generally configured to include a plurality of strings in which a plurality of memory cells are connected in series. Such flash memory devices are widely used in various semiconductor devices such as notebooks, personal digital assistants (PDAs), mobile electronic devices such as mobile phones, computer bios, printers, and universal serial bus (USB) drivers.

A memory cell array of a typical flash memory device has a structure in which memory cells are serially connected between a bit line (BL) and a cell source line (CSL). In addition, the NAND flash memory device may be referred to as a drain select line (DSL) and a source selective line (SSL) to electrically connect the memory cell to the bit line BL and the cell source line CSL. Two transistors are connected.

The memory cell of the NAND flash memory device generates Fowler-Nordheim tunneling (FN) through a tunnel oxide layer between floating gates according to a voltage applied to a control gate or a substrate (or bulk, PWELL). An erase operation is performed.

Program and erase operations of the flash device are repeatedly performed under constant voltage conditions. The repetitive program and erase operations deteriorate the tunnel oxide layer, causing a shift in the program and erase threshold voltages. In addition, since the erase operation is performed in units of memory blocks, an error of a specific memory block may occur due to a difference in the speed of erasing the memory blocks belonging to the same memory cell array. To avoid this, the erase voltage and time are determined based on the memory block having the slowest speed during erasing.

1 is a diagram illustrating variation of a threshold voltage of a memory cell as an erase program cycle progresses.

Referring to FIG. 1, in the erased state, the memory cells of the first cell group 110 repeat a program and an erase while the threshold voltage is changed as in the second cell group 120.

After the erase operation, the first cell group 110 performs a hard erase verify to determine whether the threshold voltages of the memory cells are erased below 0V. However, as the erase program cycle (hereinafter referred to as the EW cycle) progresses, the threshold voltage of the memory cell in the erase state moves in the 0V direction, and a fail may occur when the hard erase verification is performed later.

The erase as described above is described in more detail as follows.

2 is a flowchart illustrating an erase method of a nonvolatile memory device.

Referring to FIG. 2, address information of a memory block to perform an erase operation is input together with an erase command Erase CMD to erase a nonvolatile memory device (S201 and S203). Since the nonvolatile memory device performs erase in units of memory blocks, the address information input in step S203 includes only the memory block address.

After inputting address information for erasing, an execution command (Confirm CMD) for performing an erasing command is input (S205).

The erase of the memory block is performed by the execution command in step S205 (S207). The erase operation of the nonvolatile memory device is performed by applying a high voltage to the substrate of the memory block.

After the erase is performed, a hard erase verify (HEV) is performed to check whether the threshold voltages of the memory cells are 0 V or less (S209). The memory cells that have passed the hard erase verification have a threshold voltage of 0V or less, but the threshold voltage distribution is widely distributed below 0V, which may affect subsequent program operations.

Therefore, it is necessary to make the threshold voltage distribution of the erased memory cells close to 0V and narrow in width. To this end, the erased memory cells are soft-programmed (SOC) and soft program verification (SEV) is performed (S211, S213).

In the method of erasing the memory blocks in the order as shown in FIG. 2, the soft program must be first passed for hard erase verification. However, as mentioned above, even when the erase program cycle is repeated and the erase voltage is increased, the threshold voltage does not change below 0V. In this case, the soft erase operation is not completed, so the soft program operation cannot be performed.

Accordingly, an aspect of the present invention is to provide a nonvolatile memory device and a method of operating the same, which improves a fail in an erase operation by compensating for a threshold voltage change of a memory cell as an erase program cycle of the nonvolatile memory device proceeds. .

Nonvolatile memory device according to a feature of the present invention,

A memory cell array including memory blocks including a first wordline group for storing data and a second wordline group for storing erase count information; A page buffer which loads the erase count information stored in the second word line group to increase the number of times by '1' and temporarily stores the erase count information, and provides the program to program the temporarily stored data in the second word line group after the erase is completed. part; And a controller configured to control an erase start voltage when the memory block is erased according to the erase count information loaded from the second word line group.

In the second word line group, a pass voltage is applied during a program or read operation.

The control unit increases the erase start voltage as the erase count information stored in the second word line group increases.

And counting means for counting the erase count information stored in the second word line group to increase '1'.

Nonvolatile memory device according to another aspect of the present invention,

Memory cells capable of storing a plurality of bit information are connected to the first word line adjacent to the drain select line and the third word lines except for the second word line adjacent to the source select line, and the first and second words are connected. A memory cell array configured to store erase count information in memory cells connected to lines; A page buffer unit which loads the erase count information and increments the number of erase information before performing an erase operation to temporarily store the erase count information, and programs the temporarily stored data in the first and second word lines after the erase is completed; And a controller configured to control an erase start voltage when the memory block is erased according to the loaded erase count information.

A pass voltage is applied to the first and second word lines during a program and data read operation.

Nonvolatile memory device according to another aspect of the present invention,

A memory cell array including first memory cells storing erase count information and memory blocks including second memory cells for data storage; A page buffer unit configured to load and increase the erase count information to temporarily store the erase count information before the erase of the memory block, and to program the temporarily stored data to the first memory cells after the erase is completed; And a controller configured to control an erase start voltage when the memory block is erased according to the erase count information.

Method of operating a nonvolatile memory device according to a feature of the present invention,

Reading stored first erase count information before performing erasing of the memory block; Incrementing the read erase count information and updating the second erase count information; Temporarily storing the second erase count information in a page buffer; Setting an erase start voltage according to the first erase count information; Applying the erase block from the set erase start voltage to erase the memory block; And programming the second erase count information temporarily stored in the page buffer.

The first erase count information may be information on a number of times of erasing the memory block.

The second number of times information may be increased by '1'.

The first information may be stored in memory cells connected to a word line adjacent to the drain select line of the memory block and a word line adjacent to the source select line.

When the first number of times information is increased, the erasing start voltage is increased to be high.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Reading first erase count information stored in memory cells connected to a first word line adjacent to the drain select line and a second word line adjacent to the source select line before performing an erase of the memory block; Incrementing the read erase count information and updating the second erase count information; Temporarily storing the second erase count information in a page buffer; Setting an erase start voltage according to the first erase count information; Applying the erase block from the set erase start voltage to erase the memory block; And programming the second erase count information temporarily stored in the page buffer into memory cells connected to the first and second word lines.

The first erase count information may be information on a number of times of erasing the memory block.

The second number of times information may be increased by '1'.

When performing a program or data read, a pass voltage is applied to the first and second word lines.

When the first number of times information is increased, the erasing start voltage is increased to be high.

As described above, the nonvolatile memory device and its operation method according to the present invention can reduce the failure in the erase operation by compensating for the change of the threshold voltage of the memory cell as the erase program cycle progresses. .

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3A illustrates a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3A, a nonvolatile memory device 300 according to an exemplary embodiment may include a memory cell array 310, a page buffer unit 320, a Y decoder 330, an X decoder 340, and a voltage providing unit. 350 and the controller 360.

The memory cell array 310 includes memory blocks in which a plurality of memory cells are connected by a word line and a bit line, and the page buffer unit 320 is connected to a bit line to temporarily store data to be programmed in the memory cell. And page buffers for reading and temporarily storing data stored in the memory cell.

The Y decoder 330 provides a data input / output path of the page buffers, and the X decoder 340 selects a memory block and a word line of the memory cell array 310. The voltage providing unit 350 generates an operating voltage for performing a program operation or a data read operation, and the controller 360 controls the page buffer unit 320, the Y decoder 330, and X for the program operation or the data read operation. A control signal for controlling the decoder 340 and the voltage provider 350 is generated.

The memory cell array 310 of the nonvolatile memory device 300 according to the embodiment of the present invention configured as described above will be described in more detail as follows.

FIG. 3B is a circuit diagram of the memory cell array of FIG. 3A.

3B illustrates only one memory block included in the memory cell array 310. Referring to FIG. 3B, the memory block includes a plurality of cell strings.

The cell string includes a drain select transistor (DST), a source select transistor (SST), and a plurality of memory cells. The memory cells are connected in series between the drain select transistor DST and the source select transistor SST.

A bit line is connected to the drain side of the drain select transistor DST of the cell string, and a common source line SL is connected to the source side of the source select transistor SST.

The memory block includes cell strings having the above-described structure. The gates of the drain select transistors DST of the cell strings are commonly connected to a drain select line DSL, and the gates of the source select transistors SST are commonly connected to a source select line SSL. do.

In addition, gates of memory cells are commonly connected by word lines in the horizontal direction such as the drain select line DSL and the source select line SSL. The word line adjacent to the drain select line DSL is called a drain select word line DSWL, and the word line adjacent to the source select line SSL is a source select word line SSWL. This is called.

Therefore, if the memory string included in the cell string is 34, the memory block includes the source select line SSL, the source select word line SSWL, and the first through 32nd word lines WL <0> through WL <31>. And a drain select word line DSWL and a drain select line DSL.

No data is stored in the memory cells connected to the source select word line SSWL and the drain select word line DSWL. In general, a nonvolatile memory device defines one word line as a page and executes a program on a page basis. Accordingly, the source select word line SSWL and the drain select word line DSWL may be defined as dummy pages in which data is not stored. According to an embodiment of the present invention, information on the number of times of erasing is stored in the dummy page. On the other hand, a pass voltage is applied to the drain select word line DSWL and the source select word line SSWL to maintain the turn-on state.

In addition, the dummy page may be used by designating a specific word line separately. If a specific word line is to be used as a dummy page, the controller 360 should separately store address information about the specific word line.

When the nonvolatile memory device performs erasure, the nonvolatile memory device performs the memory block unit. Therefore, a method of erasing the memory block of the memory cell array 310 according to the embodiment of the present invention configured as described above is as follows.

4 is a flowchart of an erase operation according to an exemplary embodiment of the present invention.

Referring to FIG. 4, an erase command is input to erase a memory block (S401), and address information of a memory block to be erased is input (S403). A dummy page read command is input (S405).

According to the dummy page read command of step S405, a counting operation of reading erase count information stored in the drain select word line DSWL and the source select word line SSWL of the memory block, and adding 1 to the read erase count information Next, the erase count information is updated (S407 and S409).

Counting the read erase count information may be implemented in various ways. After outputting the data of the read dummy page, a method of inputting the read erase page information to the page buffer by increasing 1 'from the outside of the nonvolatile memory device is performed. Alternatively, a non-volatile memory device may include a separate counting means, input the dummy page data into the counting means provided, increase the value by one, and input the data into the page buffer.

In addition, a method of directly checking the read dummy page data by the controller 360, increasing the value of 1, and inputting the data into the page buffer again may be used.

The erase count information updated in step S409 is input to the page buffer through a data input operation (S411).

If an execution command for the erase command is input (S413), the erase of the corresponding memory block is performed (S415). The memory block erase in step S415 is performed by applying an erase voltage to the substrate.

At this time, the erase voltage to be erased to the substrate is applied in an incremental step pulse erasing (ISPE) method that sequentially increases from the start voltage (Start Bias). This is because when the high voltage of 20V or more is applied at one time, the threshold voltage distribution of the memory cell becomes too wide, and hence the subsequent program time becomes long.

Meanwhile, when the erase voltage is applied, the controller 360 sets an erase start voltage differently based on the erase count information loaded in step S407. The erase start voltage information according to the erase count is separately stored in the controller 360.

Therefore, after reading the erase count information in step S407, the control unit 360 sets the erase start voltage using the erase count information. Then, the erase operation of step S415 is applied to the substrate from the set erase start voltage.

After erasing, hard erase verification (HEV) is performed (S417). If the hard erase verification is not passed (S419), the erase voltage is increased by a predetermined step voltage and erased again (S421).

When the hard erase verification (HEV) of steps S417 and S419 passes, a soft program (SOC) is performed, and a soft program verification (SEV) is performed (S423, S425). The soft program and verification proceed with increasing the program voltage until a pass (S429).

Then, the result of the soft program verification is checked (S427), and when it passes, the erase count information input in step S411 is programmed into the dummy page (S431).

The erase voltage applied by the ISPE method is as follows.

5 shows an erase voltage pulse applied by an ISPE scheme.

5 is an erase voltage pulse when an erase voltage is applied up to 18 V by increasing the erase voltage by 0.5 V from a erase start voltage.

In the erase voltage applied as shown in FIG. 5, the erase start voltage may be set to a higher voltage as the erase program cycle increases. That is, the first erase start voltage may be set to 18V, and the erase start voltage may be changed to 18.5V when the erase program cycle exceeds 1,000 times.

For example, it is assumed that the initial erase start voltage is 18V, the step voltage is 0.5V, and the erase voltage can be increased up to 22V during the erase operation. In other words, if the hard erase verification does not pass even when the erase voltage rises to 22V, the corresponding memory block is failed. The erase start voltage and the highest erase voltage information according to the erase program cycle are separately stored in the controller 360.

In the first erase operation, the erase count information is '0' in the drain select word line DSWL and the source select word line SSWL which are dummy pages. After each program and erase operation, the erase count information is incremented by 1 and stored in the dummy page. The erase count information is stored in binary.

The erasing program cycle continues, and the erase count information is described in the state where the erase count information is stored as '1000' in the dummy page.

The above-described erase method will be described with reference to FIGS. 3A and 4 by way of example.

First, an erase command and address information are input (S401, S403). Accordingly, the controller 360 reads the data stored in the dummy page of the drain select word line DSWL or the source select word line SSWL into the page buffer (S405). In this case, the dummy page may define one of the drain select word line DSWL and the source select word line SSWL.

As a result of loading the dummy page, '1000' is read, and the controller 360 updates the erase count information to '1001' by adding 1 to the read data (S409) and inputs it to the page buffer. The number information is displayed in decimal for convenience of description, but is actually input in binary.

In addition, since the erase count information stored in the dummy page is '1000', the controller 360 changes the erase start voltage from an initial 18V to 18.5V and sets the erase count information.

When the execution command is input (S413), the erase is performed to the corresponding memory block. The erase voltage is applied from the previously set erase start voltage of 18.5V (S415). Then, after erasing, if a hard erase verification (HEV) is performed (S417, S419), a soft program (SOC) is performed (S423). After the soft program and verification (S423 to S429), the erase count information '1001' input to the page buffer in step S411 is programmed in the dummy page.

As described above, when the erase start voltage is set differently according to the erase program cycle, the threshold voltage of the memory cells of the memory block may be compensated for by the erase program cycle. Therefore, the erase fail of the memory block can be reduced.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 is a diagram illustrating variation of a threshold voltage of a memory cell as an erase program cycle progresses.

2 is a flowchart illustrating an erase method of a nonvolatile memory device.

3A illustrates a nonvolatile memory device according to an embodiment of the present invention.

FIG. 3B is a circuit diagram of the memory cell array of FIG. 3A.

4 is a flowchart of an erase operation according to an exemplary embodiment of the present invention.

5 shows an erase voltage pulse applied by an ISPE scheme.

* Brief description of the main parts of the drawings *

300: nonvolatile memory device 310: memory cell array

320: page buffer unit 330: Y decoder

340: X decoder 350: voltage providing unit

360 control

Claims (17)

A memory cell array including memory blocks including a first wordline group for storing data and a second wordline group for storing erase count information; A page buffer which loads the erase count information stored in the second word line group to increase the number of times by 1 and temporarily stores the erase count information. part; And A control unit controlling an erase start voltage when the memory block is erased according to the erase count information loaded from the second word line group Nonvolatile memory device comprising a. The method of claim 1, And the pass voltage is applied to the second word line group during a program or read operation. The method of claim 1, And the controller increases the erase start voltage as the erase count information stored in the second word line group increases. The method of claim 1, And counting means for counting the erase count information stored in the second word line group and increasing the number of erase information. Memory cells capable of storing a plurality of bit information are connected to the first word line adjacent to the drain select line and the third word lines except for the second word line adjacent to the source select line, and the first and second words are connected. A memory cell array configured to store erase count information in memory cells connected to lines; A page buffer unit which loads the erase count information and increments the number of erase information before performing an erase operation to temporarily store the erase count information, and programs the temporarily stored data in the first and second word lines after the erase is completed; And A controller for controlling an erase start voltage when erasing a memory block according to the loaded erase count information Nonvolatile memory device comprising a. The method of claim 5, And a pass voltage is applied to the first and second word lines during a program and data read operation. delete delete delete delete delete delete Reading first erase count information stored in memory cells connected to a first word line adjacent to the drain select line and a second word line adjacent to the source select line before performing an erase of the memory block; Incrementing the read erase count information and updating the second erase count information; Temporarily storing the second erase count information in a page buffer; Setting an erase start voltage according to the first erase count information; Applying the erase block from the set erase start voltage to erase the memory block; And Programming the second erase count information temporarily stored in the page buffer into memory cells connected to the first and second word lines. Method of operating a nonvolatile memory device comprising a. The method of claim 13, And the first erase count information is information on a number of times of erasing the memory block. The method of claim 13, And wherein the second number of times information is increased by '1' of the first number of times information. The method of claim 13, When performing a program or data read, a pass voltage is applied to the first and second word lines. The method of claim 13, And if the first number of times information is increased, the erase start voltage is increased to be high.

Images