KR20120005836A - Semiconductor memory device and method of erasing the same - Google Patents

Semiconductor memory device and method of erasing the same Download PDF

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Publication number
KR20120005836A
KR20120005836A KR1020100066512A KR20100066512A KR20120005836A KR 20120005836 A KR20120005836 A KR 20120005836A KR 1020100066512 A KR1020100066512 A KR 1020100066512A KR 20100066512 A KR20100066512 A KR 20100066512A KR 20120005836 A KR20120005836 A KR 20120005836A
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KR
South Korea
Prior art keywords
block
erase
hard
memory
command
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KR1020100066512A
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Korean (ko)
Inventor
박영수
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주식회사 하이닉스반도체
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Priority to KR1020100066512A priority Critical patent/KR20120005836A/en
Publication of KR20120005836A publication Critical patent/KR20120005836A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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Abstract

PURPOSE: A semiconductor memory device and an erasing method thereof are provided to reduce current consumption in an erasing operation by simultaneously erasing several memory blocks. CONSTITUTION: Block selection switches(131) enable a selected memory block in response to an address control signal. A control logic(160) controls a hard erasing operation by operating a block selection switch when the hard erasing operation is performed in one memory block. A new memory block is enabled according to a new block erasing command. The control logic includes a register. The register temporarily stores a block address inputted with a block erasing command.

Description

Semiconductor memory device and method of erasing

The present invention relates to a semiconductor memory device and an erase method thereof.

There is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that can be stored without data being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. To this end, a NAND type memory device in which a plurality of memory cells are connected in series to form a string, a plurality of strings constitute a memory block, and a plurality of memory blocks form an array of memory cells is provided. Proposed.

The semiconductor memory device performs an erase operation for deleting data in units of memory blocks.

1 is a flowchart illustrating an erase operation of a semiconductor memory device.

Referring to FIG. 1, as an erase command is input (S101), an erase voltage Verase is applied to a memory block for erasing (S13). The erase voltage is applied to the P-well of the memory block, thereby changing the threshold voltages of the memory cells included in the memory block to 0V or less.

After applying the erase voltage, the erase verification is performed by applying a 0V voltage to the word lines to which the memory cells of the memory block are connected (S105).

If the erase verification has not passed, the erase voltage Verase is increased by the step voltage (S107), and the erase and verify operation is performed (S103, S105).

If the erase verification passes, a soft program is performed to make the threshold voltages of the memory cells whose threshold voltages changed to 0V or less as close to 0V as possible (S109).

The soft program may be programmed in memory block units by applying a program voltage to all word lines, or may be performed for each word line.

After the soft program is executed, soft program verification is performed to confirm whether a verification pass has been made (S111). The soft program verification determines that the pass when the threshold voltage of at least one memory cell is changed to 0V or more. If the soft program does not pass, the program voltage is increased (S113), and the soft program and verification are performed again (S109, S111).

In a semiconductor memory device which performs the erase operation of such a memory block, since the above steps 101 to S113 are performed for each memory block when erasing a plurality of memory blocks, it is time to erase the multiple memory blocks. This costs a lot.

The semiconductor memory device according to an embodiment of the inventive concept provides an erase method capable of simultaneously performing some erase operations when erasing a plurality of memory blocks.

In a semiconductor memory device according to an embodiment of the present invention,

Memory blocks; Block selection switches for enabling a memory block selected in response to the address control signal; And a control logic for controlling a hard erase operation by operating a block selection switch for enabling a new memory block according to a new block erase command while a hard erase operation is performed on any one of the memory blocks. do.

In another embodiment, an erase method of a semiconductor memory device may include:

Receiving a first multi erase command, a first block address and a first verify command; Latching the first block address, outputting a ready busy signal indicating that a next instruction can be received, enabling a first block selection switch connected to the first memory block selected by the first block address, Controlling a voltage supply circuit to generate a hard erase voltage; Selecting a second block connected to a second memory block selected by the second block address when receiving a second multi erase command, a second block address, and a first confirm command while hard erasing the first memory block; Enabling a switch to cause the second memory block to be hard erased by the hard erase voltage along with the first memory block; And a third memory block selected by the third block address when a new second multi erase command, a third block address, and a second confirm command are received while hard erasing the first and second memory blocks. Enabling a third connected block select switch to cause the third memory block to be hard erased by the hard erase voltage together with the first and second memory blocks.

In the semiconductor memory device and an erase method thereof according to an embodiment of the present disclosure, when erasing a plurality of memory blocks, some of the erase operations may be performed by several memory blocks at the same time, thereby reducing the erase time and performing the erase operation. The current consumed in the can be reduced.

1 is a flowchart illustrating an erase operation of a semiconductor memory device.
2 shows a semiconductor memory device for explaining the present invention.
3 illustrates a connection relationship between a block selection switch and a memory block of FIG. 2.
4 is a timing diagram illustrating an erase method according to an exemplary embodiment of the present invention.
FIG. 5 is a diagram illustrating that a plurality of memory blocks are hard erased by the operation of FIG. 4.
6 is a diagram illustrating a hard erase process when performing multi-block erase according to another exemplary embodiment.
7 is a diagram illustrating a hard erase process when performing multi-block erase according to another exemplary embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2 shows a semiconductor memory device for explaining the present invention.

Referring to FIG. 2, the semiconductor memory device 100 may include a memory cell array 110, a page buffer group 120, an X decoder 130, a Y decoder 140, an input / output logic 150, and a voltage supply circuit 160. ), And control logic 170.

The memory cell array 100 includes a plurality of memory blocks BK1 to BKn. Each memory block includes a plurality of cell strings (CSs). The memory blocks BK1 to BKn have a common P well.

Each cell string includes a 0 th to 31 th memory cell C0 to C31 connected in series between a drain select transistor (DST) and a source select transistor (SST).

A gate of the drain select transistor DST is connected to a drain select line DSL, and a gate of the source select transistor SST is connected to a source select line SSL.

The gates of the 0th to 31st memory cells C0 to C31 are connected to the 0th to 31st word lines WL0 to WL31, respectively.

The drains of the drain select transistors DST are connected to bit lines, respectively. The bit line is divided into an even bit line (BLe) and an odd bit line (BLo).

The source of the source select transistor SST is commonly connected to a common source line SL.

The page buffer group 120 includes a plurality of page buffers PBs that operate for a program or a read operation.

Each page buffer PB is connected to one even bit line BLe and an odd bit line BLO pair.

The Y decoder 140 provides an input / output path between the page buffer group 120 and the input / output logic 150 in response to the control signal from the control logic 170.

The input / output logic 150 performs data input / output with the outside.

The X decoder 130 includes a plurality of block selection circuits 131. Each block selection circuit 131 is connected to each memory block.

In response to a control signal from the control logic 170, the block select circuit 131 may include the drain select line DSL, the source select line SSL, and the 0 th through 31 th word lines WL0 through the connected logic block. The WL31 is connected to the global source select line (GSSL), the global drain select line (GDSL), and the 0 th to 31 th global word lines GWL0 of the voltage supply circuit 160. To GWL31).

The voltage supply circuit 160 generates an operating voltage in response to the control signal from the control logic 170 and provides the generated operating voltage to the global lines GSSL, GDSL, GWL0 to GWL31.

The control logic 170 is used to control the operation of the page buffer group 120, the X decoder 130, the Y decoder 140, the input / output logic 150, and the voltage supply circuit 160 of the semiconductor memory device 100. Output a control signal.

An erase voltage Verase is applied to the P well when data is erased in the semiconductor memory device 100. As described above, since the memory blocks BK1 to BKn are formed in a common P well, all memory blocks may be simultaneously erased by inputting an erase voltage to the P well.

To prevent this, only the block select switch 131 connected to the memory block selected for erasing is enabled. The block select switch 131 connected to the unselected memory block is disabled. Since the word line of the memory block in which the block select switch 131 is disabled is in a floating state, memory cells of the non-selected memory block may be boosted to prevent the erase.

3 illustrates a connection relationship between a block selection switch and a memory block of FIG. 2.

Referring to FIG. 3, the block select switches 131 of the X decoder 130 are each connected to a memory block.

The voltage supply circuit 140 includes a pump group 141, and an operating voltage output from the pump group 141 includes a global drain select line GDSL, a global source select line GSSL, and a 0 th to 31 th global. The word lines GWL0 to GWL31 are provided.

The block selection switch 131 includes a plurality of pass gates PG and a block switch 131a.

The pass gates PG may include the global drain select line GDSL, the global source select line GSSL, and the 0 th to 31 th global word lines GWL0 to GWL31 and the drain select line of the memory block from the voltage supply circuit 140. The DSL, the source select line SSL, and the 0 th to 31 rd word lines WL0 to WL31 are respectively connected.

The block switch 131a turns on the pass gate PG in response to the address control signal from the control logic 160.

When the block switch 131a of the memory block selected by the control logic 160 by the address control signal turns on the pass gates PG, an operating voltage is provided to the corresponding memory block.

When the pump generating the erase voltage is enabled among the pump groups 141, the erase voltage Verase is supplied to the P well of the memory cell array 110.

In the semiconductor memory device 100, if a plurality of memory blocks are to be erased, each memory block is sequentially selected to perform an erase operation.

The semiconductor memory device 100 performs various operations such as a hard erase operation for changing a threshold voltage of a memory cell below 0V and a soft program operation for making a threshold voltage of a memory cell close to 0V during an erase operation. .

Therefore, when erasing several memory blocks, the time for performing an erase operation on each memory block becomes considerably longer.

Since the process of generating the erase voltage, applying it to the P well, and discharging again requires considerable time, the time required to erase several memory blocks becomes longer.

An embodiment of the present invention relates to an erase method for simultaneously performing hard erase.

4 is a timing diagram illustrating an erase method according to an exemplary embodiment of the present invention.

Referring to FIG. 4, addresses ADD1 to ADD3 and first confirmation commands CMD2 of a memory block to be erased are input together with the first multi-block erase command CMD1 to erase a plurality of memory blocks. When the first logic block erase command CMD1 is input, the control logic 160 determines that multi-block erase to erase several memory blocks should be performed.

After the latching of the address of the memory block input together with the first multi-block erase command CMD1, the erase pulse for hard erasing is enabled.

Control logic 160 also enables pump group 141 of voltage supply circuit 140 to generate a voltage for an erase operation. The voltage supply circuit 140 generates a voltage 4.5V and an erase voltage Verase to be provided to the global drain select line DSL and the global source select line SSL, and generate the 0 th to 31 rd global word lines. GWL0 to GWL31) are provided with 0V.

The enable signal is input to the block select switch 131 connected to the memory block to which the first multi-block erase command CMD1 is input.

When the block select switch 131 is enabled, voltages 4.5V to be provided to the global drain select line DSL and the global source select line SSL and the zeroth to thirty-first global word lines GWL0 to GWL31 are provided. 0V is input to the drain select line DSL, the source select line SSL, and the 0th to 31st word lines WL0 to WL31 of the memory block.

The erase voltage Verase is input to the P well of the memory cell array 110 to perform hard erase. The control logic 160 changes the ready busy signal #RB to a low time low level to receive an address of a memory block to be erased next during hard erase. Accordingly, the second multi-block erase command CMD3, the address of the memory block, and the first confirm command CMD2 are input.

When the second logic block erase command CMD3 is input, the control logic 160 distinguishes whether the confirmation command inputted together with the memory block address is the first confirmation command CMD2 or the second confirmation command CMD4. It is determined whether the address of the memory block is input or not.

That is, when the second multi-block erase command CMD3, the memory block address, and the first confirm command CMD2 are input, the control logic 160 latches the address of the second input memory block. The block selection switch 131 connected to the memory block corresponding to the address of the newly input memory block is enabled. That is, while the erase voltage is applied to the P well for erasing the first memory block, the block select switch 131 connected to the new memory block is enabled, and the second memory block is also hard erased.

In the multi-block erase method according to an embodiment of the present invention, only the hard erase operation is performed simultaneously. Therefore, the control logic 160 changes the ready busy signal #RB to a low level during hard erase verification, soft program, and verification except hard erase, thereby preventing a new command from being input.

The hard erase verification, the soft program, and the verification are performed by sequentially selecting the addressed memory blocks. That is, after hard erase verification is performed on the first memory block, hard erase is performed on the second memory block.

In addition, after performing hard erase verification, if hard erase is performed again, the control logic 160 changes the ready busy signal #RB back to a high level so that a new command can be input.

When the resident busy signal #RB is changed to the high level, the second multi-block erase command CMD2 and the address of the memory block and the first confirmation command CMD2 are input. If the address of the last memory block is input, the first confirmation command CMD4 is input instead of the first confirmation command CMD2.

The control logic 160 determines that the address of the memory block is no longer input when the second confirm command CMD4 is input, and keeps the ready busy signal #RB at a low level.

During the hard erase process, the block selection switch 131 of the memory block selected by the input memory block address is enabled to perform hard erase.

By the above operation, hard erase of several memory blocks proceeds at the same time, and hard erase verification, soft program and verification proceed in sequence for each memory block.

Since several memory blocks are hard erased at the same time, the overall erase time can be reduced.

FIG. 5 is a diagram illustrating that a plurality of memory blocks are hard erased by the operation of FIG. 4.

As shown in FIG. 5, voltages are sequentially applied to the global drain select line GDSL and the global source select line GSSL, and when several memory blocks are hard erased, they overlap each other for a predetermined time. As a result, the hard erase time is reduced when compared with each hard erase.

In FIGS. 4 and 5, as the address of the memory block is input, the block select switch is enabled to allow the memory block to enter the hard erase section in turn. As a result, the hard erase time when erasing multiple memory blocks may be reduced. have.

6 is a diagram illustrating a hard erase process when performing multi-block erase according to another exemplary embodiment.

Referring to FIG. 6, after all of the addresses of the last memory block are input, the block select switch 131 connected to the plurality of memory blocks is enabled at the same time, so that the memory blocks are simultaneously erased. At this time, since all selected memory blocks are hard erased at the same time, it is effective to shorten the hard erase time.

7 is a diagram illustrating a hard erase process when performing multi-block erase according to another exemplary embodiment.

Referring to FIG. 7, when an address of a memory block is input, the block selection switch 131 is enabled in turn, but not to overlap each other. Accordingly, while the erase voltage Verase is continuously applied, the memory blocks are sequentially erased. At this time, the erase of the memory blocks is sequentially performed without being overwritten. Using this method, the hard erase time may not be effectively reduced, but at the same time, there is an effect of reducing the peak current because no memory blocks are enabled.

5 to 7 show only a hard erase section, and hard erase verify, soft program, and verify are performed for each memory block.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

110: memory cell array 130: X decoder
131: block selection circuit 140: voltage supply circuit

Claims (14)

Memory blocks;
Block selection switches for enabling a memory block selected in response to the address control signal; And
While the hard erase operation is performed on any one of the memory blocks, a control logic for controlling a hard erase operation to proceed by operating a block selection switch for enabling a new memory block according to a new block erase command. Semiconductor memory device. The method of claim 1,
The control logic is,
And a register for temporarily storing a block address input together with the block erase command. The method of claim 1,
The control logic is,
And confirming whether or not the last block address is input by checking a confirmation command input together with the new block erase command. The method of claim 1,
The control logic is,
When performing the hard erase,
And enabling the block selection switches connected to the memory blocks selected by the block addresses input together with the block erase command to control the selected memory blocks to be hard erased at the same time. The method of claim 1,
The control logic is,
When performing the hard erase,
And enabling block selection switches connected to memory blocks selected by block addresses input together with the block erase command to sequentially hard erase the selected memory blocks. 6. The method of claim 5,
The control logic is,
And when the block select switches connected to the selected memory block are sequentially enabled, after one block select switch is enabled, the next block select switch is enabled. 6. The method of claim 5,
And when the block select switches connected to the selected memory block are in turn enabled, the next block select switch is enabled while one block select switch is being enabled. The method of claim 3, wherein
The control logic is,
And the ready busy signal is controlled to receive a next block address during the hard erase. The method of claim 1,
The control logic is,
And after the hard erase, when performing hard erase verification, soft program and verification, the block selection switches and the voltage supply circuit are controlled to be sequentially executed for each memory block.
Receiving a first multi erase command, a first block address and a first verify command;
Latching the first block address, outputting a ready busy signal indicating that a next instruction can be received, enabling a first block selection switch connected to the first memory block selected by the first block address, Controlling a voltage supply circuit to generate a hard erase voltage;
Selecting a second block connected to a second memory block selected by the second block address when receiving a second multi erase command, a second block address, and a first confirm command while hard erasing the first memory block; Enabling a switch to cause the second memory block to be hard erased by the hard erase voltage along with the first memory block; And
During hard erase of the first and second memory blocks, when a new second multi erase command, a third block address, and a second confirm command are received, a third memory block selected by the third block address is connected. Enabling a third block selection switch to cause the third memory block to be hard erased by the hard erase voltage together with the first and second memory blocks. The method of claim 10,
And the second multi-block erase command, the second block address, and the first verify command are not received during the hard erase verify or soft program and verify operation of the first memory block. The method of claim 10,
Performing hard erase verification on each of the memory blocks after the hard erase of the first to third memory blocks; And
And performing a soft program and verification on the memory block to which the hard erase verification has been passed. The method of claim 12,
When soft programing and verifying a memory block in which the hard erase verification has passed, simultaneously hard erasing the memory blocks in which the hard erase verification has not passed, and performing hard erase verification on each memory block,
And performing a soft program and verification of the memory block in which the hard erase verification has passed. The method of claim 10,
When the first confirmation command is input, it is determined that a second multi-block erase command and a block address are input next.
And determining that the last block address is input when the second confirmation command is input.
KR1020100066512A 2010-07-09 2010-07-09 Semiconductor memory device and method of erasing the same KR20120005836A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733046A (en) * 2013-12-19 2015-06-24 三星电子株式会社 Erase Method Of Nonvolatile Memory Device And Storage Device Employing The Same
US11269769B2 (en) 2019-07-24 2022-03-08 SK Hynix Inc. Memory system and method of operating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733046A (en) * 2013-12-19 2015-06-24 三星电子株式会社 Erase Method Of Nonvolatile Memory Device And Storage Device Employing The Same
CN104733046B (en) * 2013-12-19 2019-12-06 三星电子株式会社 Erasing method of nonvolatile storage device and storage device applying same
US11269769B2 (en) 2019-07-24 2022-03-08 SK Hynix Inc. Memory system and method of operating the same

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