KR100935600B1 - Column Decoder Of Semiconductor Integrated Circuit - Google Patents

Abstract

The column decoder circuit of the present invention includes a control unit which deactivates any one of a first cell region activation signal and a second cell region activation signal for activating the first cell region and the second cell region, respectively, in response to a cell region division signal; A predecoder for decoding the column address and outputting a first pre decoded signal group and a second pre decoded signal group; A pre-decoded signal transmitter for deactivating any one of the first pre-decoded signal group and the second pre-decoded signal group in response to deactivation of one of the first cell region activation signal and the second cell region activation signal; And a first main decoder and a second main decoder which receive the first pre-decoded signal group and the second pre-decoded signal group, respectively, and stop the operation when the signal group input thereto is deactivated.

Column Decoder, Current Reduction

Description

Column decoder of semiconductor integrated circuit

The present invention relates to semiconductor integrated circuits, and more particularly, to a column decoder.

1 is a block diagram showing an input / output configuration of a general semiconductor integrated circuit.

The semiconductor integrated circuit shown in Fig. 1 includes a cell array 1, a bit line sense amplifier 2, a column select transistor section 3, a write driver 4, a main amplifier 5, a data input buffer 6 and A data output buffer 7 is provided.

The cell array 1 is composed of a plurality of memory cells. The bit line sense amplifier 2 senses and amplifies data carried on the bit line BL. The column select transistor unit 3 transfers data carried on the bit line BL to a data bus in accordance with a column select signal Yi. During the write operation, the write driver 4 transmits data loaded on the I / O bus to the data bus.

The main amplifier 5 transmits data loaded on the data bus to the I / O bus during a read operation. The data input buffer 6 buffers the data input to the input / output pad and inputs the input / output bus to the I / O bus. The data output buffer 7 buffers data loaded on the I / O bus and outputs the buffered data to the input / output pad.

In the semiconductor integrated circuit shown in Fig. 1, when reading data written to the cell, a cell is selected in the cell array 1 by an output signal of a decoder that decodes row / column addresses, and stored in the selected cell. Data is loaded on the bit line BL when the word line WL is enabled. The bit line sense amplifier 2 amplifies the data carried on the bit line BL, and when the column select signal Yi is activated, the amplification is performed on the data bus by the column select transistor unit 3. Data is loaded. Data carried on the data bus is loaded on the I / O bus through the main amplifier 5. The data output buffer 7 outputs data loaded on the I / O bus to an input / output pad.

In addition, when data is written to the cell, data is inputted to the input / output pad, the data input buffer 6, the write driver 4, the column select transistor unit 3, and the bit line sense amplifier 2. Is transmitted to and stored in the cell array 1.

Here, the column select signal Yi is generated by the column decoder.

2 is a block diagram of a column decoder according to the prior art.

The column decoder circuit shown in FIG. 2 includes first to third pre decoders 8-1 to 8-3, and first and second main decoders 9-1 and 9-2.

The first predecoder 8-1 predecodes the column addresses CA <2: 4> according to the cell region classification signal, that is, the column address CA <13>, and thus the first up-predecoded signal LAY234_U < 0: 7>) or the first down pre-decode signal LAY234_D <0: 7>.

The cell region division signal CA <13> is an address that divides the cell array 1 into two regions. For example, it is a signal for dividing the cell array 1 into cells located above and cells located below. If the cell region classification signal CA <13> is high, the cells located above are designated. If the cell area classification signal CA <13> is low, the cells located below are designated.

The second and third predecoder 8-2 and 8-3 decode different column addresses CA <5: 7> and CA <8: 9>, respectively, so that the second predecoded signal LAY567 <0: 7>) and the third pre-decoded signal LAY89 <0: 3>.

The first main decoder 9-1 may include the first up pre decoding signal LAY234_U <0: 7>, the second pre decoding signal LAY567 <0: 7>, and the third pre decoding signal LAY89 <0. : 3>) is inputted and decoded to output an up-column selection signal (Yi_UP <0: 255>).

The second main decoder 9-2 may include the first down predecoded signal LAY234_D <0: 7>, the second predecoded signal LAY567 <0: 7>, and the third predecoded signal LAY89 <0. : 3>) is input and decoded to generate a down column selection signal (Yi_DN <0: 255>).

As described above, the first to third pre decoders 8-1 to 8-3 decode portions of the column addresses, respectively, and the first main decoder 9-1 and the second main decoder 9-. 2) decodes the outputs of the first to third pre decoders 8-1 to 8-3 to output a plurality of column selection signals Yi_UP <0: 255> and Yi_DN <0: 255>.

The operation of the column decoder circuit shown in FIG. 2 will now be described.

In the X8 mode, one of the upper cells or the lower cells is selected by the cell region discrimination signal CA <13>. For example, if the cell region classification signal CA <13> is logic high, the cells located above are selected. If the cell region classification signal CA <13> is logic low, the cells located below are selected.

That is, when the cell region classification signal CA <13> is logic high, the first pre decoder 8-1 activates the first up pre decoding signal LAY234_U <0: 7>, but the first down signal. The pre decoding signal LAY234_D <0: 7> is deactivated.

The first up pre-decoded signal LAY234_U <0: 7> is composed of eight decoded signals. Only a signal corresponding to the column address CA <2: 4> is enabled. Seven signals are disabled. For example, when the column address CA <2: 4> is 010, only the first up pre decoding signal LAY234_U <2> of the first up pre decoding signals LAY234_U <0: 7> is enabled. , Other signals are disabled. In addition, all of the first down-free decoding signals LAY234_D <0: 7> are disabled.

In addition, the second pre decoder 8-2 and the third pre decoder 8-3 are second pre-decoded by decoding the column addresses CA <5: 7> and CA <8: 9>. The signal LAY567 <0: 7> and the third pre-decoded signal LAY89 <0: 3> are output.

The first main decoder 9-1 receives the first pre-decoded signal LAY234_U <0: 7> to the third pre-decoded signal LAY89 <0: 3> and receives the column selection signal Yi_UP <0: 255. Activate the column select signal (Yi_UP <i>) corresponding to the column address. The column select signal Yi_UP <i> means any one of the column select signals Yi_UP <0: 255>.

On the other hand, since the second main decoder 9-2 receives the deactivated first pre-decoded signal LAY234_D <0: 7>, one of the column selection signals Yi_DN <0: 255> is activated. none. However, because the second main decoder 9-2 decodes the activated second pre-decode signal LAY567 <0: 7> and the activated third pre-decode signal LAY89 <0: 3>. Unnecessary current consumption is generated.

That is, even if one of the second main decoder 9-2 and the first main decoder 9-1 outputs the deactivated column select signal, the second pre-decoded signal LAY567 <i> and the first predecoder are output. Since it is actually driven by the three pre-decoded signals LAY89 <i>, unnecessary current consumption occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and an object thereof is to provide a column decoder of a semiconductor integrated circuit capable of reducing unnecessary current consumption of a main decoder.

According to an aspect of the present invention, a column decoder circuit includes a first cell region activation signal and a second cell region activation signal for activating a first cell region and a second cell region in response to a cell region division signal. A control unit for deactivating any one; A predecoder for decoding the column address and outputting a first pre decoded signal group and a second pre decoded signal group; A pre-decoded signal transmitter to deactivate any one of the first pre-decoded signal group and the second pre-decoded signal group in response to deactivation of one of the first cell region activation signal and the second cell region activation signal; And a first main decoder and a second main decoder which receive the first pre-decoded signal group and the second pre-decoded signal group, respectively, and stop the operation when the signal group input thereto is deactivated.

The column decoder circuit of the semiconductor integrated circuit according to the present invention can reduce unnecessary operating current of the main decoder.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram of a column decoder according to the present invention.

The column decoder illustrated in FIG. 3 includes a control unit 10, a pre decoder 20, a pre-decoded signal transmitter 30, and a main decoder 40.

The controller 10 activates the first cell region according to an operation mode signal X16 and a cell region division signal CA <13> for selecting one of the first cell region and the second cell region. The cell region activation signal UEQEN and the second cell region activation signal LDQEN for activating the second cell region are output.

The predecoder 20 decodes column addresses CA <2: 4>, CA <8: 9>, and CA <5: 7> to decode the predecoded signals LAY234_1 <0: 7> and LAY89_1 <0: 3. >, LAY234_2 <0: 7>, LAY89_2 <0: 3>, LAY567 <0: 7>.

The free decoder 20 includes an up free decoder 21 and a down free decoder 22.

The up predecoder 21 decodes the column addresses CA <2: 4> and CA <8: 9> to decode the first predecoded signal LAY234_1 <0: 7> and the second predecoded signal LAY89_1 <. 0: 3>).

The up free decoder 21 includes a first free decoder 21-1 and a second free decoder 21-2.

The first pre decoder 21-1 decodes the column addresses CA <2: 4> and outputs the first predecoded signal LAY234_1 <0: 7>.

The second predecoder 21-2 decodes the column address CA <8: 9> and outputs the second predecoded signal LAY89_1 <0: 3>.

The down pre decoder 22 decodes the column addresses CA <2: 4> and CA <8: 9> to decode the third pre-decoded signal LAY234_2 <0: 7> and the fourth pre-decoded signal LAY89_2 <. 0: 3>).

The down free decoder 22 includes a third free decoder 22-1 and a fourth free decoder 22-2.

The third pre decoder 22-1 decodes the column address CA <2: 4> and outputs the third predecoded signal LAY234_2 <0: 7>.

The fourth pre decoder 22-2 decodes the column addresses CA <8: 9> and outputs the fourth predecoded signal LAY89_2 <0: 3>.

In addition, the predecoder 20 decodes the column addresses CA <5: 7> and uses a fifth predecoded signal LAY567 for common input to the first main decoder 41 and the second main decoder 42. And a fifth pre decoder 23 for outputting < 0: 7 >). The output of the up-free decoder 21 is transmitted to the first main decoder 41 and the output of the down-free decoder 22 is only transmitted to the second main decoder 42, whereas the fifth free decoder is output. The output of (23) is input in common to the first main decoder 41 and the second main decoder 42.

The predecoded signal transmitter 30 may transmit the first and second predecoded signals LAY234_1 <0: 7> and LAY89_1 <0: 3> according to whether the first cell region activation signal UEQEN is enabled. Is transmitted to the first main decoder 41 and the third and fourth pre-decoded signals LAY234_2 <0: 7> and LAY89_2 <0: 3 according to whether the second cell region activation signal LDQEN is enabled. &Quot;) is transmitted to the second main decoder 42.

The pre-decoded signal transmitter 30 includes a first pre-decoded signal transmitter 31 and a second pre-decoded signal transmitter 32.

The first pre-decoded signal transmitter 31 includes a first AND operation unit 31-1 and a second AND operation unit 31-2.

The first AND operation unit 31-1 receives the first cell region activation signal UEQEN and the first pre-decoded signal LAY234_1 <0: 7> and performs an AND operation.

The second AND operation unit 31-2 receives the first cell area activation signal UEQEN, the column address enable signal YAE, and the second pre-decoded signal LAY89_1 <0: 3> and receives a logic. Multiply

The second pre-decoded signal transmitter 32 includes a third AND operation unit 32-1 and a fourth AND operation unit 32-2.

The third AND operation unit 32-1 receives the second cell region activation signal LDQEN and the third pre-decoded signal LAY234_2 <0: 7> and performs an AND operation.

The fourth AND operation unit 32-2 receives the second cell region enable signal LDQEN, the column address enable signal YAE, and the fourth predecoded signal LAY89_2 <0: 3>. Boolean operation

The main decoder 40 includes the first main decoder 41 and the second main decoder 42.

The first main decoder 41 outputs the output (LAY234_UP <0: 7>) of the first AND operation unit 31-1 and outputs the LAY89_UP <0: 3 of the second AND operation unit 31-2. >) And the fifth pre-decoded signal LAY567 <0: 7> are decoded to output an up-column selection signal Yi_UP <0: 255>.

The second main decoder 42 outputs the output (LAY234_DN <0: 7>) of the third AND operation unit 32-1 and outputs the LAY89_DN <0: 3 of the fourth AND operation unit 32-2. >) And the fifth pre-decoded signal (LAY567 <0: 7>) are decoded to output a down column selection signal (Yi_DN <0: 255>).

FIG. 4 is a circuit diagram illustrating an embodiment of the controller 10 shown in FIG. 3.

The controller 10 may include a first cell region activation signal UEQEN and a second cell region activation signal according to a test control signal TPARA, an operation mode signal X16 and the cell region identification signal CA <13>. LDQEN) is output.

The controller 10 includes first to third NOR gates NOR1 to NOR3 and first to fourth inverters IV1 to IV4.

The test control signal TPARA may be activated in a test mode for simultaneously activating the first cell region and the second cell region, and may be deactivated in a normal operation mode. The operation mode signal X16 may be logic high when the number of data input / output at one time is determined to be 16.

FIG. 5 is a circuit diagram illustrating a part of the second main decoder 42 shown in FIG. 3.

Some circuits of the second main decoder 42 illustrated in FIG. 5 include a first NAND gate ND1 and first to fourth inverters IV16 to IV16.

The first NAND gate ND1 receives and receives a fifth pre-decoded signal LAY567 <i> and an output LAY89_DN <i> of the fourth AND operation unit 32-2. The fifth pre-decoded signal LAY567 <i> refers to any one of the fifth pre-decoded signals LAY567 <0: 7>, and outputs the LAY89_DN <i> of the fourth end operation unit 32-2. ) Denotes any one of the outputs LAY89_DN <0: 3> of the fourth end operation unit 32-2. Each of the first inverter IV1 to the eighth inverter IV8 receives the output LAY234_DN <0: 7> of the third and operation unit 32-1, respectively, and supplies the first NAND gate ND1. Act on output The ninth inverter IV9 to the sixteenth inverter IV16 receive the inverted outputs of the first inverter IV1 to the eighth inverter IV8, respectively, and invert the column selection signals Yi_DN <0: 7>. )

The second main decoder 42 includes the fifth pre-decoded signal LAY567 <i> and its inverted signals, the output LAY89_DN <i> of the fourth and operation unit 32-2, and its inverted signal. Each possible combination of these has the circuit shown in FIG.

Referring to the operation of the column decoder according to the present invention shown in Figures 3 to 5 as follows.

In the X16 mode or the test mode, the controller 10 of FIG. 4 outputs the activated first cell region activation signal UEQEN and the activated second cell region activation signal LDQEN.

The first and third free decoders 21-1 and 22-1 decode the column addresses CA <2: 4> to decode the first pre-decoded signals LAY234_1 <0: 7> and the third free. The decoded signal LAY234_2 <0: 7> is output. For example, when the column address CA <2: 4> is 011, only the first predecoded signal LAY234_1 <3> of the first predecoded signals LAY234_1 <0: 7> is enabled, and the remaining seven The signal can be disabled.

In addition, the second and fourth pre decoders 21-2 and 22-2 decode column addresses CA <8: 9> to decode the second pre-decoded signals LAY89_1 <0: 3> and fourth. The predecoded signal LAY89_2 <0: 3> is output.

The fifth pre decoder 23 decodes the column addresses CA <5: 7> and outputs the fifth predecoded signal LAY567 <0: 7>.

When the column address enable signal YAE is enabled because the first cell region activation signal UEQEN and the second cell region activation signal LDQEN are enabled, the predecoded signal transmitter 30 The first to fourth AND operations of the same logic level as the first to fourth pre-decoded signals LAY234_1 <0: 7>, LAY89_1 <0: 3>, LAY234_2 <0: 7>, LAY89_2 <0: 3>. Outputs (LAY234_UP <0: 7>, LAY89_UP <0: 3>, LAY234_DN <0: 7>, LAY89_DN <0: 3>) of the units 31-1,31-2,32-1,32-2 All of them are sent to the main decoder 40.

Therefore, the first main decoder 41 and the second main decoder 42 both perform decoding operations and output corresponding column selection signals Yi_UP <0: 255> and Yi_DN <0: 255>.

Meanwhile, in the X8 mode, the controller 10 of FIG. 4 controls one of the first cell region activation signal UEQEN and the second cell region activation signal LDQEN according to the cell region division signal CA <13>. The signal is enabled and the other signal is disabled.

For example, assume that the first cell region activation signal UEQEN is enabled and the second cell region activation signal LDQEN is disabled.

The first to fifth pre decoders 21-1, 21-2, 22-1, 22-2, and 23 are column addresses CA <2: 4>, CA <8: 9>, and CA <5: 7. > To decode the first to fifth pre-decoded signals LAY234_1 <0: 7>, LAY89_1 <0: 3>, LAY234_2 <0: 7>, LAY89_2 <0: 3>, and LAY567 <0: 7>. Output

Since the first cell region activation signal UEQEN is enabled, the first pre-decoded signal transmitter 31 has the first pre-decoded signal LAY234_1 <0: 7> and the second pre-decoded signal ( LAY89_1 <0: 3>) is transmitted to the first main decoder 41. However, since the second cell area activation signal LDQEN is disabled, the second pre-decoded signal transmitter 32 may disable the third pre-decoded signal LAY234_2 <0: 7> and the fourth pre-decoded signal. The transmission of the (LAY89_2 <0: 3>) is blocked, and a signal having a fixed level (for example, a low level) is transmitted to the second main decoder 42.

Accordingly, the first main decoder 41 outputs the output of the first AND operation unit 31-1, the output of the second AND operation unit 31-2, and the fifth pre decoding signal LAY567 <0. (7>) is decoded to output the column selection signal (YiUP <0: 255>).

The first inverter IV1 to the eighth inverter IV8 of the second main decoder 42 may disable the output LAY234_DN <0: 7> of the third and operation unit 32-1. Because of the constant voltage level, the first NAND gate ND1 is operated unless the output of the first NAND gate ND1 is at a high level, and current consumption occurs.

However, when the second main decoder 42 refers to FIG. 5, the output of the fourth AND operation unit 32-2 (LAY89_DN <i>, where i is an integer equal to or greater than 0 and equal to or less than 3) is at a low level. The output of the 1 NAND gate ND1 becomes high level. Since the output of the first NAND gate ND1 is at a high level, the first to eighth inverters IV1 to IV8 are in a floating state and there is no current path, so there is no current consumption. Therefore, the column decoder according to the present invention can reduce the current consumption by the second main decoder 42.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof.

Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram showing an input / output configuration of data of a general semiconductor integrated circuit;

2 is a block diagram of a column decoder circuit according to the prior art;

3 is a block diagram showing an embodiment of a column decoder according to the present invention;

4 is a circuit diagram illustrating an embodiment of a control unit illustrated in FIG. 3, and

FIG. 5 is a circuit diagram illustrating a part of the second main decoder circuit shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

1: cell array 2: bitline sense amplifier

3: column select transistor portion 4: light driver

5: main amplifier 6: data input buffer

7: Data Output Buffers 8-1 to 8-3: First to Third Predecoder

9-1,9-2: first main decoder, second main decoder

10 control unit 20 pre decoder

21: Up Free Decoder 22: Down Free Decoder

21-1, 22-2: first and second pre decoders 22-1, 22-2: third and fourth pre decoders

30: pre-decoded signal transmitter 31,32: first and second pre-decoded signal transmitter

31-1,31-2: first and second end operation unit

32-1,32-2: third and fourth end operation units

40: main decoder 41: first main decoder

42: second main decoder 23: fifth pre decoder

Claims (11)

A controller configured to deactivate any one of a first cell region activation signal and a second cell region activation signal for activating the first cell region and the second cell region, respectively, in response to the cell region division signal; A predecoder for decoding the column address and outputting a first pre decoded signal group and a second pre decoded signal group; A pre-decoded signal transmitter to deactivate any one of the first pre-decoded signal group and the second pre-decoded signal group in response to deactivation of one of the first cell region activation signal and the second cell region activation signal; And A first main decoder and a second main decoder configured to receive the first pre-decoded signal group and the second pre-decoded signal group, respectively, and to stop the operation when the signal group input thereto is deactivated; The predecoder decodes the column address to generate the first pre-decoded signal group and outputs the first pre-decoded signal group to the first main decoder, and decodes the column address to generate the second pre-decoded signal group. 2 down-free decoder output to the main decoder, And a fifth pre decoder which decodes a column address which is not input to the up pre decoder and the down pre decoder, and outputs the same to the first main decoder and the second main decoder in common. The method of claim 1, The control unit, When a mode signal defining an operation mode for activating both the first cell region and the second cell region is activated, Activate both the first cell region activation signal and the second cell region activation signal, And when the mode signal is deactivated, activate one of the first cell region activation signal and the second cell region activation signal according to the cell region identification signal. delete The method of claim 1, The up-free decoder, A first pre decoder for decoding a portion of the column address and outputting a first pre decoding signal included in the first pre decoding signal group; And And a second pre decoder configured to decode another portion of the column address and output a second pre decoded signal included in the first pre decoded signal group. The method of claim 4, wherein The down free decoder, A third pre decoder which decodes a part of the column address and outputs a third pre decoded signal included in the second pre decoded signal group; And And a fourth pre decoder for decoding another part of the column address and outputting a fourth pre decoding signal included in the second pre decoding signal group. delete The method of claim 1, The pre-decoded signal transmission unit, A first pre-decoded signal transmitter for activating and transmitting the first pre-decoded signal group to the first main decoder according to the first cell region enable signal and the column address enable signal; And And a second pre-decoded signal transmitter configured to activate and transmit the second pre-decoded signal group to the second main decoder according to the second cell region enable signal and the column address enable signal. The method of claim 7, wherein The first pre decoding signal transmission unit, A first AND operation unit for performing an AND operation on the first cell region activation signal and the first pre-decoded signal included in the first pre-decoded signal group; And And a second AND operation unit for performing an AND operation on the first cell area enable signal, the column address enable signal, and a second pre-decoded signal included in the first pre-decoded signal group. The method of claim 8, The second pre-decoded signal transmitter, A third AND operation unit for performing an AND operation on the second cell region activation signal and the third pre-decoded signal included in the second pre-decoded signal group; And And a fourth AND operation unit for performing an AND operation on the second cell region enable signal, the column address enable signal, and a fourth pre-decoded signal included in the second pre-decoded signal group. The method of claim 2, The mode signal is, And a test signal and an operation mode signal. The method of claim 10, The operation mode signal is, A column decoder characterized in that the signal defining the number of data input / output at one time during the active operation.

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