KR100924868B1 - Method for fabricating a gate pattern in a cmos image sensor - Google Patents

Abstract

A method of forming a gate pattern of a CMOS image sensor according to the present invention includes the steps of providing a semiconductor substrate consisting of a pixel region and a logic region, sequentially depositing an insulating film and a conductive film on the entire surface of the semiconductor substrate, and a sacrificial insulating film on the conductive film. Forming a dopant, doping the impurity ions into the pixel region opened by the photoresist pattern, doping the impurity ions into the conductive film on the pixel region, and performing the impurity ion implantation process on the conductive film formed on the pixel region. Forming a doped conductive film, removing the sacrificial insulating film after removing the photoresist pattern, and forming a gate pattern by etching the doped conductive film on the pixel region and the conductive film on the logic region. .

As described above, according to the present invention, a sacrificial insulating film of a thin film is formed on the conductive film for forming the gate pattern, and then an impurity ion implantation process is performed by forming an open photoresist pattern in which the conductive film formed in the pixel region is opened. By removing the sacrificial insulating film, residues generated after the impurity ion implantation process can be easily removed to improve the characteristics of the semiconductor device and to improve the semiconductor yield.

CMOS, conductive film, ion implantation, residue

Description

METHODS FOR FABRICATING A GATE PATTERN IN A CMOS IMAGE SENSOR}

The present invention relates to a method of forming a gate pattern of a CMOS image sensor that can easily remove the residue of the photoresist pattern according to the impurity ion implantation process.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes charge capacitors in which individual capacitors are in close proximity to each other. Complementary MOS image sensor uses CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make as many MOS transistors as the number of pixels. It is an element employing a switching method that sequentially detects output using this.

FIG. 1 is a circuit diagram showing a unit pixel composed of one photodiode (PD) and four n-type MOS transistors in a conventional CMOS image sensor. And four n-type MOS transistors (Tx, Rx, Dx, Sx). Here, the four n-type MOS transistors are floated to a desired value with a photodiode that receives light to generate photocharges, and a transfer transistor (Tx) for transporting the photocharges collected from the photodiodes to a floating diffusion region (FD). A drive transistor Dx and a reset transistor Rx for setting the potential of the diffusion region FD and discharging electric charges to reset the floating diffusion region FD and a source follower buffer amplifier. It consists of a select transistor (Sx) that allows addressing in a role.

On the other hand, the conventional CMOS image sensor includes a logic region (not shown) for imaging the signal generated by the photodiode PD. This logic region is located in the periphery of the pixel region in the form of CMOS, that is, PMOS and NMOS.

Generally, as shown in FIG. 2, impurities are implanted into a gate pattern, for example, a polysilicon pattern by performing an impurity ion implantation process after a gate pattern and a gate spacer process to form a MOS transistor.

That is, a gate pattern for forming a transfer, reset, drive, select, NMOS, and PMOS transistor and a photoresist pattern 220 for protecting the photodiode PD of the pixel region 200 after forming spacers on sidewalls thereof. Is formed, and an impurity ion implantation process is performed on the regions exposed by the photoresist pattern.

However, since the gate pattern and the sidewall spacer part (region A) for the transfer transistor are covered by the photoresist pattern 220 formed to protect the photodiode PD, a sufficient amount of impurities may not be implanted in the impurity ion implantation process. There is a problem.

For this reason, as shown in FIG. 3, a conductive film, for example, a polysilicon film 320, is formed on the semiconductor substrate 300 on which the device isolation film 310 is formed, and then the pixel region 345 is deposited. Only the polysilicon layer 320 in the region corresponding to the photoresist pattern 330 may be formed to open, that is, close the region corresponding to the logic region 340.

Then, an impurity ion implantation process using the photoresist pattern 330 as an ion implantation mask is performed to implant impurity ions into the polysilicon film 320 exposed by the photoresist pattern 330. At this time, the impurity ion implantation process uses P (Phosphorous) as impurity ions, and proceeds by providing a dose of 4 to 8E15 atm / cm 2 and 12 to 14 KeV as acceleration energy.

Thereafter, the impurity ions are implanted into the polysilicon layer 320, and then a stripping process is performed to remove the photoresist pattern 330. Thereafter, the polysilicon layer 320 is selectively etched to form gate patterns of transfer, reset, drive, select, NMOS, and PMOS transistors, and sidewall spacers are formed on sidewalls of the gate pattern.

As described above, in the conventional CMOS image sensor manufacturing method, the concentration of impurity ions in the impurity ion implantation process is higher than 4E15atm / cm2 for the polysilicon film formed in the pixel region, and thus, on the polysilicon layer on the logic region after the impurity ion implantation process. Since the formed photoresist pattern is hardened, residues are left without being removed in a subsequent stripping process, and there is a problem of degrading the performance of the semiconductor device by such residues.

According to the present invention, a sacrificial insulating film of a thin film is formed on the conductive film for forming the gate pattern, and then an impurity ion implantation process is performed by forming an open photoresist pattern in which the conductive film formed in the pixel region is opened. By removing, the residue generated after the impurity ion implantation process can be easily removed.

The process of forming a gate pattern of a CMOS image sensor according to the present invention may include providing a semiconductor substrate including a pixel region and a logic region, sequentially laminating an insulating film and a conductive film over the semiconductor substrate, and overlying the conductive film. Forming a sacrificial insulating film, forming a photoresist pattern in which only the pixel region is opened on the sacrificial insulating layer, and performing an impurity ion implantation process on the pixel region opened by the photoresist pattern to form the pixel. Doping the conductive layer on the region, removing the photoresist pattern, and then removing the sacrificial insulating layer; and etching the doped conductive layer on the pixel region and the conductive layer on the logic region to form a gate pattern. Forming a step.

According to the present invention, a sacrificial insulating film of a thin film is formed on the conductive film for forming the gate pattern, and then an impurity ion implantation process is performed by forming an open photoresist pattern in which the conductive film formed in the pixel region is opened. By removing, the residues generated after the impurity ion implantation process can be easily removed to improve the characteristics of the semiconductor device as well as to improve the semiconductor yield.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

4A to 4F are flowcharts illustrating a gate pattern forming process of a CMOS image sensor according to an exemplary embodiment of the present invention.

As shown in FIG. 4A, transfer (Tx), reset (Rx), drive (Dx), and select (Sx) transistors are formed in the pixel region 400 to define an active region in the pixel region 400, and a photo is formed. A gate oxide layer 416 and a conductive layer 418 are sequentially formed on the semiconductor substrate 414 on which the device isolation layer 412 for separating the diode PD region, the pixel region 400, and the logic region 410 is formed. do. In this case, the conductive film 418 may be formed using polysilicon.

Next, as shown in FIG. 4B, a sacrificial insulating film 420 of a thin film is formed on the conductive film 418. In this case, the sacrificial insulating film 420 is formed to have a thickness of 40 kPa to 60 kPa by LP CVD (Low Pressure Chemical Vapor Deposition) method, for example, a silicon nitride film.

Thereafter, as shown in FIG. 4C, after the photoresist is applied on the sacrificial insulating layer 420, the photoresist pattern 422 in which the sacrificial insulating layer 420 of the pixel region 400 is opened by photographing and developing is performed. ), And an impurity ion implantation process using the photoresist pattern 422 as an ion implantation mask is performed to implant impurity ions into the conductive film 418. In the impurity ion implantation process according to the present invention, since impurity ions are implanted into the conductive film 418 through the sacrificial insulating film 420, acceleration energy higher than the acceleration energy in the conventional impurity ion implantation process, for example, 16 to 18 eV. Impurity ions are accelerated by the acceleration energy to implant impurity ions into the conductive film 418.

Thereafter, as shown in FIG. 4D, a stripping process is performed to remove the photoresist pattern 422. Here, a part of the photoresist pattern 422 that is hardened by the impurity ion implantation process after the stripping process, that is, the residue 422a is not removed, but is formed on the sacrificial insulating layer 420 formed in the logic region 410. Will remain.

Then, as shown in FIG. 4E, the entire surface etching process is performed to remove the residue 422a and the sacrificial insulating layer 420. In this case, the front etching process may be, for example, a wet etching process using phosphoric acid.

Thereafter, as shown in FIG. 4F, after the photoresist is coated on the conductive film 418 into which the impurity ions have been implanted, a photoresist pattern (not shown) is formed by performing a photo and development to form a gate pattern. An etch process using the photoresist pattern as an etch mask, and then on the semiconductor substrate 414 in the transfer (Tx), reset (Rx), drive (Dx), select (Sx) regions, and logic regions 410. The gate pattern 424 is formed.

According to the present invention, after the sacrificial insulating film is formed on the conductive film, impurity ions are implanted into the conductive film on the pixel region, and the residue remaining by the photoresist pattern hardened after the impurity ion implantation process is removed. By removing it, the defect of the semiconductor element by the residue can be reduced.

It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1 is a circuit diagram illustrating a unit pixel of an image sensor including one photodiode and four transistors.

2 and 3 are views for explaining an impurity ion implantation process for forming a gate pattern of a conventional CMOS image sensor,

4A to 4F are cross-sectional views illustrating a process of forming a gate pattern of a CMOS image sensor according to an exemplary embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

400: pixel region 410: logic region

412: device isolation layer 414: semiconductor substrate

416: gate oxide film 418: conductive film

420: sacrificial insulating film 422: photoresist pattern

422a: Residue 424: Gate Pattern

Claims (4)

Providing a semiconductor substrate comprising a pixel region and a logic region, Sequentially stacking an insulating film and a conductive film on the entire surface of the semiconductor substrate; Forming a sacrificial insulating film on the conductive film; Forming a photoresist pattern in which only the pixel region is opened on the sacrificial insulating layer; Doping impurity ions into the conductive film on the pixel region by performing an impurity ion implantation process on the pixel region opened by the photoresist pattern; Removing the sacrificial insulating layer after removing the photoresist pattern; Etching the doped conductive layer on the pixel region and the conductive layer on the logic region to form a gate pattern Gate pattern forming method of a CMOS image sensor comprising a. The method of claim 1, The sacrificial insulating film is a silicon nitride film formed by the LP CVD method, the gate pattern forming method of a CMOS image sensor. The method of claim 2, The sacrificial insulating film is formed to a thickness of 40 ~ 60Å, gate pattern forming method of the CMOS image sensor. The method of claim 1, The removing of the sacrificial insulating film may include removing the sacrificial insulating film by a wet etching process using phosphoric acid.

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